S.

1 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada

B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Code No: R22023/R10
II B.Tech. II Semester Regular Examinations
April - 2012
SWITCHING THEORY AND LOGIC DESIGN
( Common to EEE, ECE, BME, EIE, ECC )
Time: 3 Hours Max. Marks: 75
Answer any FIVE Questions
All Questions carry equal marks
- - -
1. (a) Assume an arbitrary number system having a radix of 5 and 0, 1, 2, L and M as its independent digits.
Determine,
(i) The decimal equivalent of (2LM.L1)
(ii) The octal equivalent of (21L.M2)
(iii) The hexagonal equivalent of (LM1.L2)
(iv) The total number of possible four-digit combinations in this arbitrary number system. (Unit-I, Topic No. 1.1)
(b) What is an excess-3 BCD code? Which short coming of the 8421 BCD code is overcome in the excess-3 BCD
code? Illustrate with the help of an example. [8+7] (Unit-I, Topic No. 1.3)
2. (a) (i) Simplify F(A, B, C, D, E) = AB D C + ABCD + ABCD + ABCDE + ABCDE + ABCDE
(ii) Prove that AB + C + D D + (E + F)G =D(AB + C) + DG(E + F)

. (Unit-II, Topic No. 2.1)
(b) With the help of the generalized form of the Hamming code, explain how the number of parity bits required to
transmit a given number of data bits. [8+7] (Unit-II, Topic No. 2.2)
3. (a) Write a simplified maxterm Boolean expression for 0, 4, 5, 6, 7, 10, 14 using the Karnaugh mapping method.
(Unit-III, Topic No. 3.1)
(b) Minimize the following function using the Quine-McCluskey method.
Y = (1, 2, 5, 8, 9, 10, 12, 13, 16, 18, 24, 25, 26, 28, 29, 31) [6+9] (Unit-III, Topic No. 3.2)
4. (a) Discuss the functional principle of 4 - bit ripple carry adder what is its major disadvantage?
(Unit-IV, Topic No. 4.2)
(b) Draw the logic diagram of a three-digit. Excess-3 adder and briefly describe its functional principle?
[8+7] (Unit-IV, Topic No. 4.2)
5. (a) Design a two-level positive logic decimal-to-BCD priority encoder for decimal inputs from 0 to 4.
(Unit-V, Topic No. 5.5)
(b) Implement the following logic function using MUX with three select inputs? [8+7] (Unit-V, Topic No. 5.4)
6. (a) Obtain the programming table for three-digit binary to gray code conversion using PLA.
(Unit-VI, Topic No. 6.1)
(b) How does a programmable logic device differ from a fixed logic device? What are the primary advantages of
using programmable logic devices? [8+7] (Unit-VI, Topic No. 6.1)
Se t - 1
S o l u t i o n s
S. 2 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
7. (a) Design a synchronous counter that counts as 000, 010, 101, 110, 000, 010 ... Ensure that the un used states
of 001, 011, 100 and 111 go to 000 on the next clock pulse. Use J-K flip-flops. (Unit-VII, Topic No. 7.4)
(b) Obtain conversion from D flip-flop to J-K flip-flop [9+6] (Unit-VII, Topic No. 7.3)
8. Derive a circuit that realizes the FSM defined by the state assigned table below using JK flip-flops.
[15] (Unit-VIII, Topic No. 8.2)
D, 0 B, 0 E
E, 0 C, 1 D
A, 0 D, 1 C
D, 0 E, 0 B
E, 0 B, 0 A
X=1 X=0
NS,Z PS
D, 0 B, 0 E
E, 0 C, 1 D
A, 0 D, 1 C
D, 0 E, 0 B
E, 0 B, 0 A
X=1 X=0
NS,Z PS
S. 3 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
SOLUTIONS TO APRIL-2012, SET-1, QP
Q1. (a) Assume an arbitrary number system
having a radix of 5 and 0, 1, 2, L and M
as its independent digits. Determine,
(i) The decimal equivalent of (2LM.L1)
(ii) The octal equivalent of (21L.M2)
(iii) The hexagonal equivalent of (LM1.L2)
(iv) The total number of possible four-digit
combinations in this arbitrary number
system.
Answer : April-12, Set-1, Q1(a) M[8]
Given that,
For an arbitrary number system,
0, 1, 2, L and M are independent digits.
i.e., 0, 1, 2, L = 3 and M = 4
(i) Given Number = (2LM. L1)
5
Conversion from radix 5 to decimal can be obtained
as,
(2LM.L1)
5
= (2 5
2
) + (L 5
1
) + (M 5
0
) + (L 5
1
)
+ (1 5
2
)
= (2 25) + (3 5) + (4 1) + (3/5) + (1/25)
= 50 + 15 + 4 + 0.6 + 0.04
= 69.64

5 10
(2 . 1) (69.64) LM L =
(ii) Given Number = (21L. M2)
5
Conversion from radix 5 to octal can be obtained as,
(21L.M2)
5
= ( )
10
= ( )
8
(21L.M2)
5
= (2 5
2
) + (1 5
1
) + (L 5
0
) + (M 5
1
) + (2 5
2
)
= ( 2 25) + 5 + (3 1) + (4
5
1
) + (2
25
1
)
= 50 + 5 + 3 + 0.8 + 0.08
= 58.880
(21 L.M2)
5
= (58.880)
10
Then, the obtained decimal equivalent number is
converted into octal as described below,
Conversion of Integer Part
(58)
10
= ( )
8

58 8

2 7 8
0 7
(58)
10
= (72)
8
Conversion of Fractional Part
(. 880)
10
= ( )
8
. 880 8= 7.040 - 7
. 040 8= 0.320 - 0

5 8
(21 . 2) (72.70) L M =
(iii) Given Number = (LM1. L2)
5
Conversion from radix 5 to hexadecimal can be
obtained as,
(LM1.L2)
5
= ( )
10
= ( )
16
(LM1.L2)
5
= (L 5
2
) + M 5
1
) + (1 5
0
) + (L 5
1
)
+ (2 5
2
)
= ( 3 25) + ( 4 5) + (1 1) + (3/5) + (2/25)
= 75 + 20 + 1 + 0.6 + 0.08 = 96.68
(LM1.L2)
5
= (96.68)
10
Then, the obtained decimal equivalent number is
converted into hexadecimal as described below,
Conversion of Integer Part
(96)
10
= ( )
16
=
96 16
6 0
(96)
10
= (60)
16
Conversion of Fractional Part
(.68)
10
= ( )
16
. 68 16= 10.880 10 ---- A
. 880 16= 14.080 14 --- E
. 080 16= 1.280 1
. 280 16= 4.480 4
. 480 16= 7.680 7

5 16
( 1. 2) (60. 147) LM L AE =
(iv) The total number of possible four-digit combinations
in the given system is,
4
5 625 =
S. 4 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
(b) What is an excess-3 BCD code? Which short coming of the 8421 BCD code is overcome in the
excess-3 BCD code? Illustrate with the help of an example.
Answer : April-12, Set-1, Q1(b) M[7]
Excess-3 BCD Code
An excess-2 BCD code is an unweighted code. It is derived from natural BCD code (i.e., 8421 BCD code) by adding
3 to each coded number. An excess-3 code of BCD code is given in table (i) below,
Decimal digit BCD
8421 2421 6423
0 0000 0000 0000
1 0001 0001 0101
2 0010 0010 0010
3 0011 0011 1001
4 0100 0100 0100
5 0101 1011 1011
6 0110 1100 0110
7 0111 1101 1101
8 1000 1110 1010
9 1001 1111 1111
Short Comings of 8421 BCD Code
1. The rules of binary addition and subtraction are applicable only for individual 4-bit groups not for complete 8421
number.
2. Arithmetic operations are more difficult to perform.
3. It is less efficient code as it requires more number of bits.
Difficulty in arithmetic operations is, let us perform the following subtraction operation using an excess-3 BCD code.
(185)
10
(8)
10
Step-1
BCD equivalent of (185)
10
is,
(185)
10
= (0001 1000 0101)
BCD
An excess-3 code of (0001 1000 0101)
BCD
is given by,
(0001 1000 0101)
BCD
= (0100 1011 1000)
Step-2
BCD of equivalent of (8)
10
is,
(008)
10
= (0000 0000 1000)
BCD
An excess-3 code of (0000 0000 1000)
BCD
is given by,
(0000 0000 1000)
BCD
= (0011 0011 1011)
Step-3
(185)
10
(8)
10
(0100 1011 1000) S
3
(0011 0011 1011) S
3
=
=
=
177
0001 0111 1101
(185)
10
(8)
10
(0100 1011 1000) S
3
(0011 0011 1011) S
3
=
=
=
177
0001 0111 1101
(177)
BCD
= (0001 0111 0111)
S. 5 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Step-4
In the above operation, the least significant column of four-bit group which is generated incorrect result required a
borrow. By adding 0011 to the result of first two columns and subtracting same from the result of third column (i.e., incorrect
result) we get the required result in excess-3 code.
0001 + 0011 = 0100
0111 + 0011 = 1010
1101 0011 = 1010
(0100 + 011 1000) S
3
(0011 0011 1011) = (0100 1010 1010) S
3
3 10 10
) 10 0100101010 ( ) 8 ( ) 185 ( XS
Q2. (a) (i) Simplify F(A, B, C, D, E) = D C AB + ABCD + ABC D + ABCDE + ABCDE + ABCDE
(ii) Prove that
[ ][ ] ) F G(E D ) C B D(A )G F (E D D C B A + + + = + + + +
Answer : April-12, Set-1, Q2(a) M[8]
(i)
The given function is,
F(A, B, C, D, E) = AB
C D
+ ABC
D
+ AB C D + ABCDE + ABC D E
+ ABC DE
= AB D (
C
+ C) + AB
C
D + ABDE(C +
C
) + ABC
D E
= AB D + ABC D + ABDE + AB
C D E
= E D C AB ABDE D C D AB + + + ] [
= AB )] )( [ D D C D + + + ABDE + AB
C D E
[QFrom distributive law, x + yz = (x + y) ( x + z)]
= AB )] 1 ( [ C D + + ABDE + AB
C D E
= AB D + AB
C
+ ABDE + AB
C D E
= AB ] [ DE D + + AB
C
+ AB
C D E
= AB[ ) ( )] D D D E + + + AB
C
+ AB
C D E
[
Q
From distributive law, x + yz = (x + y) ( x + z)]
= AB )] ( ) 1 [( E D + + AB
C
+ AB
C D E
= AB D + ABE + AB
C
+AB
C D E
= AB[ D+ E +
C
+
C D E]
= )] 1 ( [ E D C E D AB + + +
= AB[ D+ E +
C
(1)] [
Q
1+ x = x]
= AB[ D+ E +
C
]
= AB D + ABE + AB
C
( , , , , ) F A B C D E ABC ABD ABE = + +
S. 6 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
(ii) Note
In the given question R.H.S term is misprinted,
Consider [A
B
+
C
+
D
] [ D + (E +
F
)G]
[A
B
+
C
+
D
] [D +( E +
F
)G] = A B D + A
B
(E +
F
)G +
C
D +
C
(E +
F
)G +
D
.D +
D
(E +
F
)G
= A
B
D + A B EG + A
B F
G +
C
D +
C
EG +
C F
G +
D
G(E +
F
)
[
QD
.D = 0]
= D(A
B
+
C
) + EG(A
B
+
C
) +
F
G(A
B
+
C
]
= (A
B
+
C
) (D + EG +
F
G)
= (A
B
+
C
) ( D + (E +
F
)G]
[ ] [ ( ) ] ( ) [ ( ) ] AB C D D E F G AB C D E F G + + + + = + + +
(b) With the help of the generalized form of the Hamming code, explain how the number of
parity bits required to transmit a given number of data bits.
Answer : April-12, Set-1, Q2(b) M[7]
Hamming code comprises of certain parity bits. The number of parity bits used by the Hamming code depends on the
number of data bits.
For example, we can derive the number of parity bits used by the Hamming code for the given number of data bits
from the equation given below,
1 2 + +
b
P
P n
b
Where, P
b
= Number of parity bits and
n = Number of data bits.
For example, a 4-bit Excess-3 message, the Hamming code uses 3 parity bits (
Q
1 3 4 2
3
+ + satisfies) for detecting
and correcting the single bit errors. Therefore, the total code consists of 7-bits.
The designation of bit starts from the right-most bit i.e., (bit 1)
Bit 7, Bit 6 ...... Bit 1
Parity bits can be placed in powers of 2 i.e., 1, 2, 4.
Therefore, the general 7-bit Hamming code for a 4-bit Excess-3 messages is as follows.
D
7
, D
6
, D
5
, P
4
, D
3
, P
2
, P
1
Where D = Data bits and
P = Parity bits.
Now, for the 4-bit Excess-3 message we have to assign values i.e., 1 or 0 to the parity bits to form a 7-bit Hamming
code.
The parity bit P
1
checks the bits located at positions 1, 3, 5 and 7. So, we have to assign P
1
such that bit locations 1,
3, 5 and 7 must have either even or odd parity. Similarly, P
2
checks for locations 2, 3, 6 and 7 and P
4
, checks for 4, 5, 6 and 7.
Thus, a 7-bit Hamming code is generated for a 4-bit Excess-3 message by assigning values to the three represents
parity bits.
S. 7 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Q3. (a) Write a simplified maxterm Boolean
expression for 0, 4, 5, 6, 7, 10, 14 using
the Karnaugh mapping method.
Answer : April-12, Set-1, Q3(a) M[6]
The given function is,
F(A, B, C, D) = (0, 4, 5, 6, 7, 10, 14)
Then, the above boolean function F can be simplified
using 4-variable Karnaugh map as shown in figure (i) below,
0
0
0
4
12
8
9
11
0
10
0
14
0
6
2 3 1
00 01 11 10
00
01
11
10
(A + C + D)
CD
AB
(A + )
( + + D)
B
A C
13
0
5
0
7
15
0
0
0
4
12
8
9
11
0
10
0
14
0
6
2 3 1
00 01 11 10
00
01
11
10
(A + C + D)
CD
AB
(A + )
( + + D)
B
A C
13
0
5
0
7
15
F = (A +
B
) (A + C + D) (
A
+
C
+ D).
(b) Minimize the following function using
the Quine-McCluskey method.
Y = (1, 2, 5, 8, 9, 10, 12, 13, 16, 18, 24,
25, 26, 28, 29, 31)
Answer : April-12, Set-1, Q3(b) M[9]
The given function is,
y = (1, 2, 5, 8, 9, 10, 12, 13, 16, 18, 24, 25, 26, 28, 29, 31)
Step-1
The given function in tabular form is shown in table (1).
Minterms Binary Representation Number of 1s
1 00001 1
2 00010 1
5 00101 2
8 01000 1
9 01001 2
10 01010 2
12 01100 2
13 01101 3
16 10000 1
18 10010 2
24 11000 2
25 11001 3
26 11010 3
28 11100 3
29 11101 4
31 11111 5
Table (1)
Step-2
Group the minterms based on the number of 1s as
shown in table (2),
Group Minterms Binary representation
1 1 00001
2 00010
8 01000
16 10000
2 5 00101
9 01001
10 01010
12 01100
18 10010
24 11000
3 13 01101
25 11001
26 11010
28 11100
4 29 11101
5 31 11111
Table (2)
Step-3
Now compare each minterm with the adjacent
group and mark them if they differ by single bit as shown in
table (3),
Minterms Binary Representation
(1, 5) 00 - 01
(1, 9) 0 - 001
(2, 10) 0 - 010
(2, 18) - 0010
(8, 9) 0100 -
(8, 10) 010 - 0
(8, 12) 01 - 00
(8,24) - 1000
(16, 18) 100 - 0
(16, 24) 1 - 000
(5, 13) 0 - 101
(9, 13) 01 - 01
(9, 25) - 1001
(10, 26) - 1001
(12, 13) 0110 -
S. 8 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
(12, 28) - 1100
(18, 26) 1 - 010
(24, 25) 1100 -
(24, 26) 110 - 0
(24, 28) 11 - 00
(3, 29) - 1101
(25, 29) 11 - 01
(28, 29) 1110 -
(29, 31) 111 - 1
Table (3)
Step-4
Repeat step 3 until no further possible comparisons can be made. Now, further comparisons make the quards of
minterms as shown in table (4),
Minterm Binary Representation
1, 5, 9, 13 0 - - 01
1, 9, 5, 13 0 - - 01
2, 10, 18 , 26 - - 010
8, 9, 12, 13 01 - 0 -
8, 9, 24, 25 - 100 -
8, 10, 24, 26 - 10 - 0
8, 12, 9, 13 0 1 - 0 -
8, 12, 24, 28 - 1 - 00
8, 24, 9, 25 - 100 -
8, 24, 10, 26 - 100 -
8, 24, 12, 28 - 1 - 00
16, 28, 24, 26 1- 0 - 0
16, 24, 18, 26 1 - 0 - 0
9, 13, 25, 29 - 1- 01
9, 25, 3, 29 - 1- 01
10, 26, 3, 29 - 1 - 01
12, 13, 28, 29 - 110 -
12, 28, 3, 29 - 110 -
24, 25, 28, 29 11 - 0 -
24, 28, 25, 29 11 - 0 -
Table (4)
S. 9 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Step-5
Repeat Step 3
Minterms Binary representation
8, 9, 24, 25, 12, 13, 28, 29 - 1 - 0 -
8, 9, 24, 25, 12, 13, 28, 29 - 1 - 0 -
8, 12, 24, 28, 9, 13, 25, 29 - 1 - 0 -
8, 12, 24, 28, 9, 25, 13, 29 - 1 - 0 -
8, 12, 24, 28, 10, 26, 13, 29 01 - 0 -
8, 24, 9, 25, 12, 13, 28, 29 - 1 - 0 -
8, 24, 9, 25, 13, 29, 12, 28 - 1 - 0 -
8, 24, 10, 26, 12, 13, 28, 29 - 1 - 0 -
8, 24, 10, 26, 12, 28, 13, 29 - 1 - 0 -
8, 24, 12, 28, 9, 13, 25, 29 - 1 - 0 -
8, 24, 12, 28, 9, 25, 13, 29 - 1 - 0 -
8, 24, 12, 28, 10, 26, 13, 29 - 1 - 0 -
Table (5)
In the above steps, the unmarked minterm are referred as prime implicants and are tabulated below,
Prime implicants Binary representation
29, 31 111 - 1
1, 5, 9, 13 0 - - 01
2, 10, 18, 26 - - 010
16, 28, 24, 26 1 - 0 - 0
8, 24, 9, 25, 12, 13, 28, 29 - 1 - 0 -
Table (6)
Prime Implicant Chart
Table (7) represents the prime implicant selection chart.
B 8, 24, 9, 25, 12
13, 28, 29
A 16, 28, 24, 26,
2, 10, 18, 26
1, 5, 9, 13
ABCE 29, 31
31 29 28 26 25 24 18 16 13 12 10 9 8 5 2 1
C D E
E D A
B 8, 24, 9, 25, 12
13, 28, 29
A 16, 28, 24, 26,
2, 10, 18, 26
1, 5, 9, 13
ABCE 29, 31
31 29 28 26 25 24 18 16 13 12 10 9 8 5 2 1
C D E
E D A
Table (7)
From the above chart, the function y can be represented by selecting the minimum number of prime implicants
which cover all he minterms.
y ABCE ADE CDE A B = + + + +
S. 10 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Q4. (a) Discuss the functional principle of 4 - bit ripple carry adder what is its major disadvantage.
Answer : April-12, Set-1, Q4(a) M[8]
4-bit Ripple Carry Adder
For answer refer Unit-IV, Q9.
Disadvantage
The speed of ripple carry adder reduces with the increase in number of bits. This is because, the carry occurring at
the least significant bit (LSB) has to transmit from LSB to MSB.
(b) Draw the logic diagram of a three-digit Excess-3 adder and briefly describe its functional
principle?
Answer : April-12, Set-1, Q4(b) M[7]
Three-Digit Excess-3 Adder
The block diagram of three- digit excess-3 adder is represented in figure (i). It consists of six 4-bit parallel adders, and
three NOT gates.
Working Principle
The three-digit excess-3 addition can be carried out by the following 2 steps,
Step-1
In step-1, addition of three excess-3 code groups is performed.
Step-2
Depending on the produced carry either 0011 or 1101 is added to the sum of the code groups.
4-Bit Parallel Adder
F
3
F
2
F
1
F
0
E
3
E
2
E
1
E
0
S
11
S
10
S
9
S
8
F
3
F
2
F
1
F
0
Adding
13, if carry = 0
3, if carry = 1
S
11
S
10
S
9
S
8
not
used
C
out
digit 3
digit 2
4-Bit Parallel Adder
E
3
E
2
E
1
E
0
1
C
out
4-Bit Parallel Adder
D
3
D
2
D
1
D
0
C
3
C
2
C
1
C
0
S
7
S
6
S
5
S
4
D
3
D
2
D
1
D
0
S
7
S
6
S
5
S
4
not
used
C
out
digit 1
4-Bit Parallel Adder
C
3
C
2
C
1
C
0
1
C
out
4-Bit Parallel Adder
B
3
B
4
B
1
B
0
A
3
A
2
A
1
A
0
S
3
S
2
S
1
S
0
B
3
B
2
B
1
B
0
Adding
13, if carry = 0
3, if carry = 1
S
3
S
2
S
1
S
0
not
used
C
out
digit 0
4-Bit Parallel Adder
A
3
A
2
A
1
A
0
1
C
out
Adding
13, if carry = 0
3, if carry = 1
C
in = 0
4-Bit Parallel Adder
F
3
F
2
F
1
F
0
E
3
E
2
E
1
E
0
S
11
S
10
S
9
S
8
F
3
F
2
F
1
F
0
Adding
13, if carry = 0
3, if carry = 1
S
11
S
10
S
9
S
8
not
used
C
out
digit 3
digit 2
4-Bit Parallel Adder
E
3
E
2
E
1
E
0
1
C
out
4-Bit Parallel Adder
D
3
D
2
D
1
D
0
C
3
C
2
C
1
C
0
S
7
S
6
S
5
S
4
D
3
D
2
D
1
D
0
S
7
S
6
S
5
S
4
not
used
C
out
digit 1
4-Bit Parallel Adder
C
3
C
2
C
1
C
0
1
C
out
4-Bit Parallel Adder
B
3
B
4
B
1
B
0
A
3
A
2
A
1
A
0
S
3
S
2
S
1
S
0
B
3
B
2
B
1
B
0
Adding
13, if carry = 0
3, if carry = 1
S
3
S
2
S
1
S
0
not
used
C
out
digit 0
4-Bit Parallel Adder
A
3
A
2
A
1
A
0
1
C
out
Adding
13, if carry = 0
3, if carry = 1
C
in = 0
Figure (i): Three-Digit Excess-3 Adder
i.e., if carry = 0, add 13 and if carry = 1 add 3 to the respective sum.
For example, consider the excess-2 addition of decimal numbers 123 and 658.
S. 11 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Addition of Decimal Numbers 123 and 658
Step 1
Adding the XS3 number using binary addition.
123 in XS3 = 0100 0101 0110
1001 1000 1011
1101 1110 0001
1(Carry)
123 in XS3 = 0100 0101 0110
1001 1000 1011
1101 1110 0001
1(Carry)
658 in XS3 =
123 in XS3 = 0100 0101 0110
1001 1000 1011
1101 1110 0001
1(Carry)
123 in XS3 = 0100 0101 0110
1001 1000 1011
1101 1110 0001
1(Carry)
658 in XS3 =
Step 2
Adding 0011 to the last group as it produced a carry.
1101 1110 0001
+ 0011
0100
1101 1110 0001
+ 0011
0100
Step 3
Subtracting 0011 from the first two groups, as they
did not produce any carry.
1101 1110 0100
0011 0011
1010 1011 0100
1101 1110 0100
0011 0011
1010 1011 0100
1 8 7
8 5 6
3 2 1
= 1010 1011 0100
781 in XS3 code is,
(781)
10
= (1010 1011 0100)
XS3
Q5. (a) Design a two-level positive logic
decimal-to-BCD priority encoder for
decimal inputs from 0 to 4.
Answer : April-12, Set-1, Q5(a) M[8]
Priority Encoder
Priority encoder is a device that has n input lines
and
n
2
log output lines. Based on priority it processes the
inputs. For example when two or more inputs are applied
then the highest priority input will be encoded first. Priority
encoders are available in standard IC form.
Decimal-to- BCD Priority Encoder for 4 Decimal Inputs
The block diagram and truth table of decimal -to-
BCD priority encoder for 4-decimal inputs are shown in figure
(i) and table (i) respectively,
Decimal
to
BCD
priority
Encoder
D
0
D
1
D
2
D
3
D
4
Q
0
Q
1
Q
2
Decimal
to
BCD
priority
Encoder
D
0
D
1
D
2
D
3
D
4
Q
0
Q
1
Q
2
Figure (i): Block Diagram of Decimal -BCD Priority Encoder
Inputs Outputs
D
0
D
1
D
2
D
3
D
4
Q
2
Q
1
Q
0
Z
0 0 0 0 0 0
1 0 0 0 0 0 0 0 1
1 0 0 0 0 0 1 1
1 0 0 0 1 0 1
1 0 0 1 1 1
1 1 0 0 1
Table (i)
From the truth table, boolean expressions for this
priority encoder are given as,
Q
2
= D
4
Q
1
= D
2
+ D
3
Q
0
= D
1
+ D
3
Z = D
0
+ D
1
+ D
2
+ D
3
+ D
4
Implementation of above expressions using logic
gates is shown in figure (ii),
D
0
D
1
D
2
D
3
D
4
Q
2
= D
4
Q
1
= D
2
+D
3
Q
0
= D
1
+D
3
Z = D
0
+ D
1
+D
2
+ D
3
+D
4
D
0
D
1
D
2
D
3
D
4
Q
2
= D
4
Q
1
= D
2
+D
3
Q
0
= D
1
+D
3
Z = D
0
+ D
1
+D
2
+ D
3
+D
4
Figure (ii): Logic Diagram of Decimal-BCD Priority Encoder for 0
to 4 Inputs
S. 12 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
(b) Implement the following logic function
using MUX with three select inputs?
Answer : April-12, Set-1, Q5(b) M[7]
Note: In the given question logic function is missing. So
consider,
Logic function, F(a, b, c, d) = c d a d bc a + + + .
For remaining answer refer April-12, Set-3, Q5(b).
Q6. (a) Obtain the programming table for three-
digit binary to gray code conversion
using PLA.
Answer : April-12, Set-1, Q6(a) M[8]
Binary to Gray Code Conversion using PLA
The conversion table of 3-digit binary to gray code is
given below,
Binary Gray
B
2
B
1
B
0
G
2
G
1
G
0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
Table (i)
From the above, gray code outputs are expressed as,
G
2
= m (4, 5, 6, 7)
G
1
= m (2, 3, 4, 5)
G
0
= m(1, 2, 5, 6)
The minimal expressions for G
2
, G
1
and G
0
can be
obtained using K-maps and are described as below,
K-Map for G
2
K-Map for G
1
B
2
B
1
B
0
00
01 11 10
0
1
0 1 3 2
6
1 1 1 1
4 5 7
B
2
B
2
B
1
B
0
00
01 11 10
0
1
0 1 3 2
6
1 1 1 1
4 5 7
B
2

B
2
B
1
B
0
00
01 11 10
0
1
0 1 3 2
6
1 1
1 1
4 5 7
2 1
B B
2 1
B B
1 1
B
2
B
1
B
0
00
01 11 10
0
1
0 1 3 2
6
1 1
1 1
4 5 7
2 1
B B
2 1
B B
1 1
2 2
B G =
1 2 1 2 1
G B B B B = +
K-Map for G
0
B
2
B
1
B
0
00
01 11 10
0
1
0 1 3 2
6
1
1
1
4 5 7
1 2
B B
1 1
1 0
B B
B
2
B
1
B
0
00
01 11 10
0
1
0 1 3 2
6
1
1
1
4 5 7
1 2
B B
1 1
1 0
B B
0 1 0 1 0
B B B B G + =
G
2
= B
2
G
1
=
2 1
B B +
1 2
B B
G
0
=
0 1
B B +
0 1
B B
The implementation of above expressions using PLA
is shown in figure,
B
0
B
1
B
2
G
2
G
1
G
0

B
0
B
1
B
2
G
2
G
1
G
0

Figure: Binary to Gray Code Conversion using PLA

(b) How does a programmable logic device
differ from a fixed logic device? What
are the primary advantages of using
programmable logic devices?
April-12, Set-1, Q6(b) M[7]
S. 13 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Answer :
PLA
PLD is an abbreviated form of programmable logic device. It employs large number of gates, registers and flip-flops
interconnected on the chip; The specific function implementation using PLD can be achieved by selective breaking of the
respective interconnections. It can be reprogrammed within few seconds while fixed logic device cannot be, because it is
designed only for specific function.
Primary Advantages of PLDs
The following are the advantages of PLDs,
(i) Programmable logic devices are highly reliable
(ii) They,
Need less space
Consume less power
Can be reprogrammed
provide high design security
Require less time to design the circuit
Provide high switching speed
Are less expensive.
(iii) The circuit testing of PLD use easy.
Q7. (a) Design a synchronous counter that counts as 000, 010, 101, 110, 000, 010 ... Ensure that the un
used states of 001, 011, 100 and 111 go to 000 on the next clock pulse. Use J-K flip-flops.
Answer : April-12, Set-1, Q7(a) M[9]
Given that,
The synchronous counter counts as,
000, 010, 101, 110, 000, 010, ....
The unused states, 001, 011, 100, 110, 111 go to 000 for next clock pulse. By the following steps, the required
synchronous counter can be designed.
Step 1
The counter to be designed has 4 stable states. As the maximum count is 6 it requires, three (6

23) flip-flops.
Since, the unused states are 000 after next clock pulse, no dont cares exist.
Step 2
The state diagram of the counter that count 0, 2, 5, 6, 0 .... is shown in figure (i) below,
5
2
0
1
3
4
7
6
5
2
0
1
3
4
7
6
Figure: (i)
S. 14 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Step 3
The excitation table of the counter using JK flip-flops is given in table (i)
Present state Next state Required Excitations
Q
3
Q
2
Q
1
Q
3
Q
2
Q
1
J
3
K
3
J
2
K
2
J
1
K
1
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 0 1 1 1 1
0 1 1 0 0 0 0 1 1
1 0 0 0 0 0 1 0 0
1 0 1 1 1 0 0 1 1
1 1 0 0 0 0 1 1 0
1 1 1 0 0 0 1 1 1
Table (i)
Step 4
The minimal expressions for J
3
, K
3
, J
2
, K
2
, J
1
and K
1
can be obtained using K-maps as described below,
K-Map for J
3
Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3 2
6

4 5 7
1

2 1
Q Q
Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3 2
6

4 5 7
1

2 1
Q Q
3 2 1
J Q Q =
K-Map for K
3
Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3 2
6
1
1
4 5 7

1

1
Q
Q
2
Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3 2
6
1
1
4 5 7

1

1
Q
Q
2
3 1 2
K Q Q = +
K-Map for J
2
K-map for K
2
Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3
2
6

4
5
7

3 1
Q Q
1
Q
1
Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3
2
6

4
5
7

3 1
Q Q
1
Q
1
Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3 2
6
1
4
5
7
1
1
1

Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3 2
6
1
4
5
7
1
1
1

2 1 3 1
J Q Q Q = +
2
1 K =
S. 15 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
K-map for J
1
K-map for K
1
Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3
2
6 4
5
7
1

Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3
2
6 4
5
7
1

Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3
2
6 4
5
7

1
1
1
1

Q
3
Q
2
Q
1
00
01 11 10
0
1
0 1 3
2
6 4
5
7

1
1
1
1

1 3 2
J Q Q = 1
1
= K
The minimal expressions are,
J
3
= Q
2

1
Q
K
3
=
1
Q +Q
2
J
2
= Q
1
+
1 3
Q Q
K
2
= 1
J
1
=
2 3
Q Q
K
1
= 1
Step 5
The implementation of minimal expressions using J-K flip-flops is shown in figure (ii)
J
1
Q
1
K
1
J
2
Q
2
K
2
J
3
Q
3
K
3 2
Q 1
Q
3
Q
Clock
J
1
Q
1
K
1
J
2
Q
2
K
2
J
3
Q
3
K
3 2
Q 1
Q
3
Q
Clock
Figure (iii): Synchronous Counter Implementation using JK Flip-Flops
(b) Obtain conversion from D flip-flop to JK flip-flop.
Answer : April-12, Set-1, Q7(b) M[6]
For answer refer Unit-VII, Q24.
S. 16 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Q8. Derive a circuit that realizes the FSM defined
by the state assigned table below using JK
flip-flops.
D, 0 B, 0 E
E, 0 C, 1 D
A, 0 D, 1 C
D, 0 E, 0 B
E, 0 B, 0 A
X=1 X=0
NS,Z PS
D, 0 B, 0 E
E, 0 C, 1 D
A, 0 D, 1 C
D, 0 E, 0 B
E, 0 B, 0 A
X=1 X=0
NS,Z PS
Answer : April-12, Set-1, Q8 M[15]
The given FSM state table is,
D, 0 B, 0 E
E, 0 C, 1 D
A, 0 D, 1 C
D, 0 E, 0 B
E, 0 B, 0 A
X=1 X=0
NS,Z
PS
D, 0 B, 0 E
E, 0 C, 1 D
A, 0 D, 1 C
D, 0 E, 0 B
E, 0 B, 0 A
X=1 X=0
NS,Z
PS
Table (i)
From the state table, state diagram can be obtained
as shown in figure (i)
A
B
E D
A
C
x = 0
x = 0
x = 1
x = 0
x = 1
x = 1
x = 1
x

=

1
x = 0
x = 0
A
B
E D
A
C
x = 0
x = 0
x = 1
x = 0
x = 1
x = 1
x = 1
x

=

1
x = 0
x = 0
Figure: (i) State Table
Then, the equivalence classes using partition method
can be obtained as follows,
Consider,
P
0
= (A B C D E)
Partition P
1
States having the same outputs under all input
conditions can be grouped as follows,
P
1
= (A B E) (C D)
Partition P
2
When the machine is in states (ABE), a 1 input
applied will lead to (BEB) states, (B) is the successor of (A)
and (EB) is the successor of (BE). Since (B) and (EB) are
falling in different blocks, P
2
is obtained as,
P
2
= (A) (BE) (CD)
Partition P
3
When the machine is in states (CD), a 1 input applied
will lead to states (AE). (A) is the successor of (C) and (E) is
the successor of (D).
Since (A) and (E) are falling in different blocks. P
3
is
obtained as,
P
3
= (A) (B, E) (C) (D)
Partition P
4
For the inputs 0 and 1, (B, E) successors are in
same block. Thus, no further partition is possible.
The equivalent states are,
B = E
Then, the reduced state table is,
PS NS, Z
x = 0 x =1
A B, 0 B, 0
B B, 0 D, 0
C D, 1 A, 0
D C, 1 B, 0
Table (ii)
As there are 4 states we need two flip-flops. By
assigning state A = 000, B = 01, C = 10 and D = 11, the
excitation table of JK flip-flop can be obtained follows,
S. 17 Switching Theory and Logic Design (April-2012, Set-1) JNTU-Kakinada
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
Inputs PS NS Flip-flop Inputs Outputs
P Q P Q J
P
K
P
J
Q
K
Q
Z
0 0 0 0 1 0 1 0
0 0 1 0 1 0 1 0
0 1 0 1 1 0 1 1
0 1 1 1 0 0 1 1
1 0 0 0 1 0 1 0
1 0 1 1 1 1 0 0
1 1 0 0 0 1 0 0
1 1 1 0 1 1 0 0
Table (iii)
The minimal expressions for J
P
, K
P
, J
Q
, K
Q
and Z can be obtained using K-maps as described below,
K-Map for J
P
K-Map for K
P
X
PQ
00
01 11 10
0
1
0 1 3 2
6

4 5 7
1
1
XQ
X
PQ
00
01 11 10
0
1
0 1 3 2
6

4 5 7
1
1
XQ
X
PQ
00
01 11 10
0
1
0 1 3 2
6
1
4 5 7

1
X

X
PQ
00
01 11 10
0
1
0 1 3 2
6
1
4 5 7

1
X

P Q
J X =
P
K X =
K-Map for J
Q
K-Map for K
Q
X
PQ
00
01 11 10
0
1
0 1 3 2
6 4 5 7

1
X
P
X
PQ
00
01 11 10
0
1
0 1 3 2
6 4 5 7

1
X
P
X
PQ
00
01 11 10
0
1
0 1 3 2
6 4 5 7
1

X
PQ
00
01 11 10
0
1
0 1 3 2
6 4 5 7
1

Q
J P X = +
Q
K X =
K-Map for Z
X
PQ
00
01 11 10
0
1
0 1 3 2
6 4 5 7
1
1
XP
X
PQ
00
01 11 10
0
1
0 1 3 2
6 4 5 7
1
1
XP
Z XP =
S. 18 Spectrum ALL-IN-ONE Journal for Engineering Students, 2013
B.Tech. II-Year II-Sem. ( JNTU-Kakinada )
J
P
= XQ
K
P
= X
J
Q
=
X P +
K
Q
=
X
Z = XP
Implementation of the above expressions using JK flip-flops is shown in figure (ii),
J
P
P
K
P
P
X
J
Q
Q
K
Q
Q
Clk
X
Z
FF
FF
J
P
P
K
P
P
X
J
Q
Q
K
Q
Q
Clk
X
Z
FF
FF
Figure (ii)