4P008-00 03 E-paper+Display+COG+Driver+Interface+Timing

Doc. No.
4P008-00
Rev.: 03 Page: 1 of 31 Date: 2013/07/24
This document is the exclusive property of PDI and shall not be reproduced or copied or transformed to any other format
without prior permission of PDI. ( PDI Confidential )

E-paper Display COG
Driver Interface Timing

Description
Detailed information to design a
timing controller for 1.44, 2,
and 2.7 E-paper panels
Date 2013/07/24
Doc. No. 4P008-00
Revision 03

Design Engineering
Approval Check Design

No.71, Delun Rd., Rende Dist., Tainan City 71743, Taiwan (R.O.C.)
Tel: +886-6-279-5399 Fax: +886-6-279-5300

2013.07.24

2013.07.24

2013.07.24
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 2 of 31 Date: 2013/07/24

Copyright
Pervasive Displays Incorporated All rights reserved.
This document is the exclusive property of Pervasive Displays Inc. (PDI) and shall not be
reproduced or copied or transformed to any other format without prior permission of PDI.
(PDI Confidential)

Pervasive Displays Inc.
No.71, Delun Rd., Rende Dist., Tainan City 71743, Taiwan (R.O.C.)
Tel: +886-6-279-5399
http://www.pervasivedisplays.com
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 3 of 31 Date: 2013/07/24

Table of Contents
Revision History ................................................................................................. 4
Glossary of Acronyms ......................................................................................... 5
1 General Description ....................................................................................... 6
1.1 Overview............................................................................................ 6
1.2 Input Terminal Pin Assignment .............................................................. 8
1.3 Reference Circuit ............................................................................... 10
1.4 EPD Driving Flow Chart ...................................................................... 11
1.5 Controller ......................................................................................... 12
1.6 SPI Timing Format ............................................................................. 14
2 Write to the Memory .................................................................................... 17
3 Power On COG Driver .................................................................................. 18
4 Initialize COG Driver .................................................................................... 19
5 Write data from the memory to the EPD ......................................................... 21
5.1 Data Structure .................................................................................. 21
5.2 Store a line of data in the buffer .......................................................... 23
5.3 Writing to the display in stages ............................................................ 29
6 Power Off COG Driver .................................................................................. 31

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 4 of 31 Date: 2013/07/24

Revision History
Version Date
Page
(New)
Section Description
Ver. 01 2012/05/08 All All Approval specification first issued
Ver. 02 2012/07/27
6 1.1 Modify Overview description
8 1.2
Add Input Terminal Pin Assignment section and
description
10 1.3 Add Reference Circuit section
11 1.4 Modify Flash to memory in the flow chart
12 1.5 Modify Controller and description
13 1.6 Modify SCL to SCLK, SDI to SI in the sheet
16 2
Modify the section name Write to the Flash to Write to the
Memory
16 2 Modify the description of section 2
17 3
Modify Border control to BORDER
Add PWM toggle before V
CC
/V
DD
turn on
18 4
Modify the flow chart and description
Modify the setting of register 0x06 from 0x1F to 0xFF
20 5
Modify the section name Write data from the flash to the
EPD to Write data from the memory to the EPD
20 5.1 Modify the description of section 5
21 5.1 Add 1.44 frame time for V110 FPL
22 5.2 Add 1.44 and 2.7 flow chart
26 5.3 Modify the flow chart and description
Ver. 03 2013/07/24
All All Modify some description in the document
All All Add New border control function for 1.44
10 1.3
Modify Reference Circuit
Modify the voltage proof (16v -> 25v)

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 5 of 31 Date: 2013/07/24

Glossary of Acronyms

EPD Electrophoretic Display (e-Paper Display)
EPD Panel EPD
Tcon Timing Controller
FPL Front Plane Laminate (e-Paper Film)
SPI Serial Peripheral Interface
COG Chip on Glass
PDI, PDi Pervasive Displays Incorporated

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 6 of 31 Date: 2013/07/24

1 General Description
1.1 Overview
This document explains the interface to the COG Driver to operate the EPD for a MCU based
solution using two pages of memory buffer. This document applies to 1.44, 2.0, and 2.7
EPDs.
Both new and previous display images are stored in memory buffer, then the COG Driver is
powered on, initialized, panel updated in stages and then the COG Driver is powered off.
Refer to the EPD controller in section 1.5 to see the complete update cycle from Power On,
Initialize, Update and Power off. To operate the EPDs for the best sharpness and
performance, each update of the panel is divided into a series of stages before the display of
the new image pattern is completed. During each stage, frame updates with intermediate
image patterns are repeated for a specified period of time. The number of repeated frame
updates during each stage is dependent on the Timing Controller speed. After the final stage,
the new pattern is displayed.

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 7 of 31 Date: 2013/07/24

Around the active area of the EPD is a 0.5mm width blank area called the border. When
connected to V
DL
(-15V) to keep the border white. After approximately 10,000 updates with
the constant voltage, the border color may degrade to a gray level that is not as white as the
active area. To prevent this phenomenon, PDI recommends turn on and off border to avoid
the degradation.
Section 1 is an overview and contains supporting information such as the overall theory for
updating an EPD, SPI timing for PDIs EPDs, as well as current profiles.
Section 2 describes a method to write to memory buffer. Previously updated and new
patterns are stored in the memory buffer to compare the old and new image patterns during
the update.
Section 3 describes how to power on the COG Driver which consists of applying a voltage
and generating the required signals for /CS and /RESET.
Section 4 describes the steps to initialize the COG Driver.
Section 5 describes the details on how to update the EPD from the memory buffer, create
a line of data, update in stages, and also power down housekeeping steps.
Section 6 describes how to power off the COG Driver, and discharge voltage from EPD to
ground, make sure there is not any voltage keep in EPD.
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 8 of 31 Date: 2013/07/24

1.2 Input Terminal Pin Assignment
No Signal I/O Connected to Function
1 /CS I Tcon Chip Select. Low enable
2 BUSY O Tcon
When BUSY = HIGH, EPD stays in busy state that
EPD ignores any input data from SPI
3 ID I Ground Connect ID to ground
4 SCLK I Tcon Clock for SPI
5 SI I Tcon Serial input from Timing Controller to EPD
6 SO O Tcon Serial output from EPD to Timing Controller
7 /RESET I Tcon Reset signal. Low enable
8 ADC_IN -
BORDER or
Not connected
For 1.44, connect to BORDER
For 2 & 2.7, Not connected
9 V
CL
C Capacitor -
10 C42P C
Charge-Pump
Capacitor
-
11 C42M C -
12 C41P C
Charge-Pump
Capacitor
-
13 C41M C -
14 C31M C
Charge-Pump
Capacitor
-
15 C31P C -
16 C21M C
Charge-Pump
Capacitor
-
17 C21P C -
18 C16M C
Charge-Pump
Capacitor
-
19 C16P C -
20 C15M C
Charge-Pump
Capacitor
-
21 C15P C -
22 C14M C
Charge-Pump
Capacitor
-
23 C14P C -
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 9 of 31 Date: 2013/07/24

No Signal I/O Connected to Function
24 C13M C
Charge-Pump
Capacitor
-
25 C13P C -
26 C12M C
Charge-Pump
Capacitor
-
27 C12P C -
28 C11M C
Charge-Pump
Capacitor
-
29 C11P C -
30 V
COM_DRIVER
RC Resistor & Capacitor
The signal duty cycle can drive VCOM voltage
from source driver IC
31 V
CC
P V
CC
Power supply for analog part of source driver
32 V
DD
P V
DD
Power supply for digital part of source driver
33 V
SS
P Ground -
34 V
GH
C Capacitor -
35 V
GL
C Capacitor -
36 V
DH
C Capacitor -
37 V
DL
C Capacitor -
38 BORDER I -
For 1.44, connect to ADC_IN
For 2 & 2.7, connect to V
DL
via control circuit for
white frame border
39 V
ST
P V
COM_PANEL
-
40 V
COM_PANEL
C Capacitor V
COM
to panel
Note:
I: Input
O: Output
C: Capacitor
RC: Resistor and Capacitor
P: Power
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 10 of 31 Date: 2013/07/24

1.3 Reference Circuit
Note.1
D2
1N4148W
1
2
2.2u/25V/Y5V C14
2.2u/25V/Y5V C13
C16M
C16P
C15M
C15P
C14M
C14P
C21P
C13M
C13P
C12M
C12P
C11M
C11P
VCC
VDD
C31M
C41M
C41P
VCL
C21M
C31P
VCOM_DRIVER
/RESET
SO
SI
SCLK
/CS
VST
BORDER
VCOM
BUSY
DISCHARGE
VDL
VCC
BORDER_CONTROL
VGL
VGH
VGH
VDH
VCOM
BORDER
BORDER
2N7002KW Q3
1
3 2
2.2u/16V/Y5V C11
2.2u/16V/Y5V C8
100K/5%
R3
2.2u/16V/Y5V C3
2.2u/16V/Y5V C10
2.2u/25V/Y5V C16
E
P
D

P
A
N
E
L

P
C
B

S
I
D
E
4
0
P
I
N

0
.
5
m
m

P
I
T
C
H

C
O
N
N
E
C
T
O
R
/
P
A
D
J 1
ZIF-40-0.5
C21M
16
C31P
15
C31M
14
C41M
13
C41P
12
C42M
11
C42P
10
VCL
9
ADC_IN
8
/RESET
7
SO
6
SI
5
SCLK
4
ID
3
BUSY
2
/CS
1
C21P
17
C16M
18
C16P
19
C15M
20
C15P
21
C14M
22
C14P
23
C13M
24
C13P
25
C12M
26
C12P
27
C11M
28
C11P
29
VCOM_DRIVER
30
VCC
31
VDD
32
VSS
33
VGH
34
VGL
35
VDH
36
VDL
37
BORDER
38
VST
39
VCOM_PANEL
40
2.2u/25V/Y5V C6
2.2u/16V/Y5V C9
1u/10V/X7R
C12
2N7002KW
Q2
1
3
2
BSS84W Q4
1
3
2
2.2u/25V/Y5V C5
2.2u/25V/Y5V C15
2.2u/10V/Y5V C1
2.2u/25V/Y5V C4
100K/5% R5
2K/5%
R2
100K/5%
R4
2.2u/25V/Y5V C7
Connect to Timing Controller GPIO
Connect to Timing Controller SPI
2N7002KW
Q1
1
3
2
Connect to Power Switch
Connect to Power Ground
INPUT
DI SCHARGE: set hi gh f or EPD
di schar ge when EPD power of f
VGL
PWM
BAT54SW
D1
1
3
2
100n/16V/X7R
C17
PWM: 100~300KHz,
50%dut y cycl e,
squar e wave
C42P
C42M
2.2u/16V/Y5V C2
VDH
BORDER_CONTROL : Squar e Pul se
when power on
Connect t o a MOS Swi t ch t o
pr event l eakage cur r ent
0R R1
Note.1
Note.1

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 11 of 31 Date: 2013/07/24

1.4 EPD Driving Flow Chart
The flowchart below provides an overview of the actions necessary to update the EPD. The
steps below refer to the detailed descriptions in the respective sections.
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 12 of 31 Date: 2013/07/24

1.5 Controller
The diagram below provides a signal control overview during an EPD update cycle.
The diagram is segmented into 3. Power On COG Driver, 4. Initialize COG Driver, 5.
Write data from the memory to the EPD, and 6. Power Off COG Driver. The segment
number and title matches a section title in this document which contain the details for
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 13 of 31 Date: 2013/07/24

each segment.
SI
/CS
4. Initialize
COG
Driver
VCC/VDD
SCLK
BORDER
*2
5. Write Data from the memory to the EPD
6. Power Off
COG Driver
3. Power On
COG Driver
PWM
*1
DISCHARGE
/RESET
Ground

Note:
1. PWM: 100~300 KHz Duty= 50% Square wave.
The PWM signal starts before V
CC
/V
DD
input and stops during the initialization of the
COG Driver to ensure there is a negative VGL on the COG Driver. Our reliability
testing shows that with low temperature that the COG Driver has the possibility of
V
CC
/V
DD
generating a slightly positive voltage, and the PWM is an effective solution
for this condition. Refer to the section 4 of this spec.

2. BORDER:
For implement this function, Developer needs to use a pin from Microcontroller to
control. BORDER is used to keep a sharp border while taking care of the electronic ink
particles.
(This function is only used in 2" & 2.7" EPD)
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 14 of 31 Date: 2013/07/24

1.6 SPI Timing Format
SPI commands are used to communicate between the MCU and the COG Driver. The SPI
format used differs from the standard in that two way communications are not used, and CS
is pulled high then low between clocks. When setting up the SPI timing, PDI recommends
verifying the control signals for the overall waveform in Section 1.5, next verify the SPI
command format and SPI command timing both in this section.
The maximum clock speed that the display can accept is 12MHz. The SPI mode is 0.
Below is a description of the SPI Format:
SPI(0xI
1
I
2
, 0xD
1
D
2
D
3
D
4,
D
5
D
6
D
7
D
8
)
Where:
I
m
I
n
is the Register Index and the length is 1 byte
D
m~n
is the Register Data. The Register Data length varies from 1, 2, to 8
bytes depending on which Register Index is selected.
Register Index
Number Bytes of
Register Data
0x01 8
0x02 1
0x03 1
0x04 1
0x05 1
0x06 1
0x07 1
0x08 1
0x09 2
Before sending the Register Index, the SPI (SI) must send a 0x70 header command.
Likewise, the SPI (SI) must send a 0x72 is the header command prior to the Register Data.
The flow chart and detailed description can be found on the next page.

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 15 of 31 Date: 2013/07/24

SPI command signals and flowchart:
SI
/CS
7
SCLK
0 7 2
For example:
To send two SPI commands:
SPI((0x08,0x9D) and SPI(0x09, 0xD010)
If register data is larger than two bytes, you must
input data continuously without setting Register
Index again.
SPI(0xI
1
I
2
,0xD
1
D
2
)
Header
0x70
/CS = 1
Delay 10us
/CS = 0
Register Index
(0xI
1
I
2
)
Header
0x72
Send data
(0xD
1
D
2
)
/CS = 1
Delay 10us
/CS = 0
Yes
No
/CS = 1
Data send
Complete?
Register
Index
Register
Data
Header Header
SI
/CS
7 0 0 8 7 2 9 D 7 0 0 9 7 2 D010
SCLK
/CS must be set High then Low between Register Index and Register Data

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 16 of 31 Date: 2013/07/24

SPI command timing
SI
/CS
SCLK
0.9V
DD
0.1V
DD
tCSS tCHS
tCYS
tWHS tWLS
tDSS tDHS
Serial clock cycle
SCLK high pulse width
SCLK low pulse width
Data setup time
Data hold time
CSB hold time
CSB setup time
VCC = 2.7 to 3.3V Temp = 0 to +50
Item Signal Symbol Min. Typ. Max. Unit Remark
tCYS
tWHS
tWLS
tDSS
tDHS
tCHS
tCSS
80
40
40
20
20
24
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCLK
SCLK
SCLK
SI
SI
/CS
/CS

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 17 of 31 Date: 2013/07/24

2 Write to the Memory
Before powering on COG Driver, the developer should write the new pattern to image
buffer, either SRAM or flash memory. The image pattern must be converted to a 1 bit
bitmap format (Black/White) in prior to writing.
Two buffer spaces should be allocated to store both previous and new patterns. The
previous pattern is the currently displayed pattern. The new pattern will be written to the
EPD. The COG Driver will compare both patterns before updating the EPD. The table
below lists the buffer space size required for each EPD size.

EPD size Image resolution(pixels)
Previous + new image Buffer
(bytes)
1.44 128 x 96 3,072
2" 200 x 96 4,800
2.7 264 x 176 11,616

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 18 of 31 Date: 2013/07/24

3 Power On COG Driver
Start
*1*3
PWM toggle 10ms
PWM toggle 5ms
Section 4
Initialize COG
Driver
PWM
*2
start to
toggle
/CS = 1
/RESET = 1
/RESET = 0
/RESET = 1
PWM toggle 5ms
PWM toggle 5ms
PWM toggle 5ms
This flowchart describes power sequence for the
COG Driver.
1. Start :
Initial State:
V
CC
/V
DD
, /RESET, /CS, BORDER, SI, SCLK = 0
2. PWM:
100~300KHz, 50% duty cycle, square wave to
eliminate the potential negative voltages that could
occur at low temperature. Keeping PWM toggling
until VGL & VDL is on (SPI(0x05,0x03)).
3. BORDER:
For implement this function, developer needs to
use a pin from microcontroller to control. BORDER
is used to keep a sharp border while taking care of
the electronic ink particles.
V
CC
/V
DD
voltage
2.7 to 3.3V
PWM stop to
toggle and set =
0
BORDER
*3
= 1

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 19 of 31 Date: 2013/07/24

4 Initialize COG Driver

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 20 of 31 Date: 2013/07/24

Note:
1. SPI(0x01, Data):
Different by each size
1.44: SPI(0x01, (0x0000,0000,000F,FF00))
2: SPI(0x01, (0x0000,0000,01FF,E000))
2.7: SPI(0x01, (0x0000,007F,FFFE,0000))
Take 2 for example, to send first byte protocol (0x70) before Register Index
(0x01), and then send second byte protocol (0x72) before Register Data
(0x0000,0000,01FF,E000).

2. Set DC/DC Frequency setting by each size.

3. Set Vcom level. If register data is larger than two bytes, the developer must finish
sending the data prior to sending another Register Index command.

4. Gate and Source Voltage Level is different by each size:
Different by each size
Panel Size Data
1.44 0x03
2 0x03
2.7 0x00

5. Should measure VGH >12V and VDH >8V
Should measure VGL <-12V and VDL <-8V

6. PWM: 100~300 KHz, 50% duty cycle, square wave.

7. BUSY: BUSY signal is generated by COG Driver, when COG Driver stays in busy state
(BUSY = 1) that COG Driver ignores any input data from SPI. So its recommended to
check busy state at every update. If users cannot check BUSY signal, use delay at least
1 usec (10
-6
second).
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 21 of 31 Date: 2013/07/24

5 Write data from the memory to the EPD
This section describes how data should be sent to the COG Driver which will update the display.
The COG Driver uses a buffer to store a line of data and then writes to the display.
5.1 Data Structure
EPD Resolutions
EPD size Image resolution(pixels) X Y
1.44 128 x 96 128 96
2" 200 x 96 200 96
2.7 264 x 176 264 176
Data components
- One Bit A bit can be W (White), B (Black) or N (Nothing) bits. Using the N bit
mitigates ghosting.
- One Dot/pixel is comprised of 2 bits.
- One line is the number of dots in a line. For example:
The 1.44 uses 128 Dots to represent 1 Line.
The 2 uses 200 Dots to represent 1 Line.
The 2.7 uses 264 Dots to represent 1 Line.
The COG Driver uses a buffer to write one line of data (FIFO) - interlaced
Data Bytes Scan bytes Data Bytes
1
st
25
th
(Even) 1
st
- 24
th
26
th
50
th
(Odd)
2 Example:
Because method to write is interlaced, write
the even data bytes for a line
{D(200,y),D(198,y),D(196,y),D(194,y)}.
{D(8,y),D(6,y),D(4,y),D(2,y)}
2 Example:
Write bytes for every scan line
{S(1),S(2),S(3),S(4)}.
{S(93),S(94),S(95),S(96)}
2 Example:
Write the odd data bytes for a line
{D(1,y),D(3,y),D(5,y), D(7,y)}.
{D(193,y),D(195,y),D(197,y),D(199,y)}

- One frame of data is the number of lines * rows. For example:
The 1.44 frame of data is 96 lines * 128 dots.
The 2 frame of data is 96 lines * 200 dots.
The 2.7 frame of data is 176 lines * 264 dots.
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 22 of 31 Date: 2013/07/24

- One stage is the number of frames used to write an intermediate pattern. This can vary
based on the MCU choice. PDIs design writes 6 frames of data per stage, and then 4 stages
for 2 and 1.44 to update the display from the previous to the new pattern. 2.7 need 3
frames of data per stage.

Panel Size FPL Stage Time (ms)
MCU Frame Time
(ms)(Recommend)
1.44 V110 480
< 50ms
2 V110 480
2.7 V110 630 < 80ms
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 23 of 31 Date: 2013/07/24

5.2 Store a line of data in the buffer
This section describes the details of how to send data to the COG Driver. The COG Driver uses
a buffer to update the display line by line.

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 24 of 31 Date: 2013/07/24

1.44 Input Data Order
Frame start
1
st
Data Byte
{D(128,y),D(126,y),
D(124,y), D(122,y)}
1
st
Scan Byte
{S(1),S(2),
S(3), S(4)}
24
th
Scan Byte
{S(93),S(94),
S(95), S(96)}
16
th
Data Byte
{D(8,y),D(6,y),
D(4,y), D(2,y)}
17
th
Data Byte
{D(1,y),D(3,y),
D(5,y), D(7,y)}
(1,1) (2,1) (3,1) (128,1)
x
y
(1,2) (2,2) (3,2)
(1,3)
(1,96 ) (128, 96)
32
nd
Data Byte
{D(121,y),D(123,y),
D(125,y), D(127,y)}
y = 97
No
Frame end Yes
Example:
D(128,y) = Black (B) = 11
D(126,y) = White (W)= 10
D(124,y) = Nothing(N) = 01
D(122,y) = Black (B) = 11
1
st
Data Byte= 11,10,01,11
Total displayed data in a
line: (128+96)x2 bits
Sending Data
SPI(0x0A, Data)
Output data from COG
driver to panel.
The operation of
SPI(0x0A,Data) is same as
that when Initialize Driver.
0x0A: index of data register
Turn on Output Enable
SPI(0x02, 0x2F)
bit1 bit0 Input
1 1 Black (B)
1 0 White (W)
0 0/1 Nothing (N)
Data
D(x,y)
x = 1~128
y = 1~96
1 1 Scan on
0 0 Scan off
Scan
S(1) ~S(96)
Example:
When y = 2,
Only S(2) is Scan on (11) while others are
Scan off (00). The image represented by Data
Bytes will be displayed on 2
nd
horizontal line
(i.e. Dot(1,2) ~ Dot(128,2)).
S(1) = Scan off = 00
S(2) = Scan on = 11
:
S(96) = Scan off = 00
1
st
Scan Byte = 00,11,00,00
2
nd
~ 24
th
Scan Byte = 00,00,00,00
bit1 bit0 Input
Note :
1. When start transfer each Data Byte, users need
to check BUSY pin.
2. If users cannot check BUSY pin, use delay at
least 1 usec (10
-6
second) Between byte-byte
data for transfer image data.
BUSY
SCLK
Example :
Border Byte
0x00
Line end
y ++
Set Chargepump
voltage level reduce
voltage shift
SPI(0x04, 0x03)
Line start
y = 1

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 25 of 31 Date: 2013/07/24

2 Input Data Order
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 26 of 31 Date: 2013/07/24

Frame start
1
st
Data Byte
{D(200,y),D(198,y),
D(196,y), D(194,y)}
1
st
Scan Byte
{S(1),S(2),
S(3), S(4)}
24
th
Scan Byte
{S(93),S(94),
S(95), S(96)}
25
th
Data Byte
{D(8,y),D(6,y),
D(4,y), D(2,y)}
26
th
Data Byte
{D(1,y),D(3,y),
D(5,y), D(7,y)}
(1,1) (2,1) (3,1) (200,1)
x
y
(1,2) (2,2) (3,2)
(1,3)
(1,96 ) (200, 96)
50
th
Data Byte
{D(193,y),D(195,y),
D(197,y), D(199,y)}
y = 97
No
Frame end Yes
Example:
D(200,y) = Black (B) = 11
D(198,y) = White (W)= 10
D(196,y) = Nothing(N) = 01
D(194,y) = Black (B) = 11
1
st
Data Byte= 11,10,01,11
0x00
Sending Data
SPI(0x0A, Data)
driver to panel.
The operation of
Add eight bits 0 to
complete a line.
SPI(0x02, 0x2F)
bit1 bit0 Input
1 1 Black (B)
1 0 White (W)
0 0/1 Nothing (N)
Data
D(x,y)
x = 1~200
y = 1~96
1 1 Scan on
0 0 Scan off
Scan
S(1) ~S(96)
Example:
When y = 2,
nd
horizontal line
(i.e. Dot(1,2) ~ Dot(200,2)).
S(2) = Scan on = 11
:
S(96) = Scan off = 00
1
st
Scan Byte = 00,11,00,00
2
nd
~ 24
th
Scan Byte = 00,00,00,00
bit1 bit0 Input
Note :
to check BUSY pin.
least 1 usec (10
-6
BUSY
SCLK
Example :
Line end
y ++
Set Chargepump
voltage shift
SPI(0x04, 0x03)
Line start
y = 1

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 27 of 31 Date: 2013/07/24

2.7 Input Data Order
P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 28 of 31 Date: 2013/07/24

Frame start
1
st
Data Byte
{D(264,y),D(262,y),
D(260,y), D(258,y)}
1
st
Scan Byte
{S(1),S(2),
S(3), S(4)}
44
th
Scan Byte
{S173),S(174),
S(175), S(176)}
33
rd
Data Byte
{D(8,y),D(6,y),
D(4,y), D(2,y)}
34
th
Data Byte
{D(1,y),D(3,y),
D(5,y), D(7,y)}
(1,1) (2,1) (3,1) (264,1)
x
y
(1,2) (2,2) (3,2)
(1,3)
(1,176) (264,176)
66
th
Data Byte
{D(257,y),D(259,y),
D(261,y), D(263,y)}
y = 177
No
Frame end Yes
Example:
D(264,y) = Black (B) = 11
D(262,y) = White (W)= 10
D(260,y) = Nothing(N) = 01
D(258,y) = Black (B) = 11
1
st
Data Byte= 11,10,01,11
0x00
Sending Data
SPI(0x0A, Data)
driver to panel.
The operation of
Add eight bits 0 to
complete a line.
SPI(0x02, 0x2F)
bit1 bit0 Input
1 1 Black (B)
1 0 White (W)
0 0/1 Nothing (N)
Data
D(x,y)
x = 1~264
y = 1~176
1 1 Scan on
0 0 Scan off
Scan
S(1) ~S(176)
Example:
When y = 2,
nd
horizontal line
(i.e. Dot(1,2) ~ Dot(264,2)).
S(2) = Scan on = 11
:
S(176) = Scan off = 00
1
st
Scan Byte = 00,11,00,00
2
nd
~ 44
th
Scan Byte = 00,00,00,00
bit1 bit0 Input
Note :
to check BUSY pin.
least 1 usec (10
-6
BUSY
SCLK
Example :
Line end
y ++
Set Chargepump
voltage shift
SPI(0x04, 0x00)
Line start
y = 1

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 29 of 31 Date: 2013/07/24

5.3 Writing to the display in stages
This section contains the method to write to the display in stages. Each of the 4 stages should
be the same use the same number of frames. Rewrite the frame during each stage.
The flow chart that follows describes how to update an image from a previous displayed image
stored in memory buffer to a new image also stored in memory buffer. See the sample
previous and new images below.

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 30 of 31 Date: 2013/07/24

Initialize Driver
Sense Temperature
to determine
Temperature Factor
(TF)
Stage 2
*1
White
(Stage Time * TF) ms
Stage 3
*2
Inverse
Stage 1
*1
Compensate
*4
bit1 bit0 Input
1 1 Black (B)
1 0 White (W)
0 0/1 Nothing (N)
Data
W B
1. The image stored in memory
is used to determine how to write the
data for both Stage 1 and Stage 2.
2. The image stored in memory is
used to determine how to write the
data for both Stage 3 and Stage 4.
3. Optional: The optical performance is
dependent on Stage Time. If the
ghosting is at unacceptable level, the
EPD can be rewritten and then Stage 4
repeated to write the New image.
4. It needs (Stage Time * TF) ms to finish
a stage.
Panel Size (Stage Time * TF) ms
5. The TF below 0is for reference
only. PDI does not guarantee the
performance and functionality below
0.
6. To redeuce the current consumption,
definition of Nothing is different at
Stage 2 and Stage 3.
Stage 2 Nothing(00)
Stage 3 Nothing(01)
N
*6
W
N
*6
B
Stage 4
*2*3
Normal
B W
New
*2
B W
Stage 4 Data
Input
New
*2
B W
Stage 3 Data
Input
Previous
*1
B W
Stage 2 Data
Input
Previous
*1
B W
Stage 1
Data
Input
W B
New
*2
B W
Stage R
Data
Input
Optional Stage
Repeat
(Stage Time * TF)
ms
Power Off
Ghosting level
is acceptable
*3
Yes
No
Temperature ()
-10
-5 T > -10
5 T > -5
10 T > 5
15 T > 10
20 T > 15
TF
*5
40 T > 20
> 40
W B Display
W W
Display
W B Display
B W
Display
W B Display
1
1
White
2
2
2
Previous
Display
Display
Display
Display
New
Display
Display
17
12
4
3
2
1
0.7
V110
8
1.44"(V110)
2"(V110)
2.7"(V110)
480
480
630

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

Doc. No. 4P008-00
Rev.: 03 Page: 31 of 31 Date: 2013/07/24

6 Power Off COG Driver
Turn off osc
SPI(0x07,0x0D)
Power off
chargepump Vcom
SPI(0x05,0x0E)
Latch reset turn on
SPI(0x03,0x01)
Output enable off
SPI(0x02,0x05)
Input Display Data
Write a
Nothing Frame*
1
Write a
Dummy Line*
2
Delay 25ms
Discharge internal
SPI(0x04,0xA0)
Discharge internal
SPI(0x04,0x00)
Delay 40 ms
Set Powers and
Signals = 0 (VCC, VDD,
/RESET, /CS, SI, SCLK,
BORDER
*3
)
External Discharge*
4
= 1
External
Discharge*
4*5
= 0
Delay 150 ms
Finish
1. Nothing Frame :
A frame, 96 lines/1.44"&2", 176 lines/2.7", whose all
D(x,y) are N(01). Scan Bytes operate normally. Scan
lines are still turned on sequentially. This Frame will
make the image more uniform. Turn on OE
SPI(0x02, 0x2F) at the end of each line.
For 1.44", need to set Border Byte(0x00) before 1
st
Data Byte.
2. Dummy Line :
A line whose all Data Bytes are 0x55 and Scan
Bytes are 0x00. Turning on OE SPI(0x02, 0x2F) to
complete this Dummy Line. Clear the register data
before power off. Detail of data input is on page 23 ~
page 25.
3. BORDER :
For implement this function, users need to use a pin
to control from microcontroller. When = 0, the
BORDER is ON and write to white. When = 1,the
BORDER is OFF. The reason for using BORDER is
to keep a sharp border and not have a charge on the
particles of FPL. Voltage too long on these will
produce a gray effect which is the optimal for long
term operation.
4. External Discharge :
For implement this function, users need to use a pin
from microcontroller to control. This is important to
avoid vertical lines.
5. If you use the flash memory for pattern store,
please recheck flash in this phase and verify the old
image flash is erased.
6. BORDER Dummy Line :
Set Border Byte = 0xAA and write to white. A line
whose a Border Byte is before 1
st
Data Byte and all
Data Bytes are 0x55 and Scan Bytes are 0x00. Then
must to set SPI(0x02,0x2F) in the end of line for turn
on output enable by COG control border and clear
the register data before power off. Detail of
data input is on page 23 ~ page 25.
(This function is only used in 1.44" EPD)
Power off Negative
Chargepump
SPI(0x05,0x02)
Discharge
SPI(0x04,0x0C)
Turn off all
chargepumps
SPI(0x05,0x00)
Delay 120 ms
Discharge internal
SPI(0x04,0x50)
Delay 40 ms
BORDER*
3
= 0
BORDER*
3
= 1
Delay 200~300ms
Write a
BORDER Dummy
Line*
6
Is EPD size
1.44" ?
No Yes
Delay 200~300ms

P
E
R
V
A
S
I
V
E

D
I
S
P
L
A
Y
S

I
N
C
.

4P008-00 03 E-paper+Display+COG+Driver+Interface+Timing

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

4P008-00 03 E-paper+Display+COG+Driver+Interface+Timing

Uploaded by

Copyright:

Available Formats

Doc. No.

You might also like