International Journal of Engineering and Advanced Technology (IJEAT)

ISSN: 2249 9!" #olu$e%&" I''ue%!" June 2(&2

I$)le$entation of an Efficient *ulti)lier
+a'ed on #edic *athe$atic' ,'ing E-A Tool
.u'h)alata #er$a" /0 /0 *ehta

Abstract:% A high speed processor depends greatly on the
multiplier as it is one of the key hardware blocks in most
digital signal processing systems as well as in general
processors. This paper presents a high speed 8x8 bit Vedic
multiplier architecture which is quite different from the
Conventional method of multiplication like add and shift.
The most significant aspect of the proposed method is that
the developed multiplier architecture is based on Vertical
and Crosswise structure of Ancient !ndian Vedic
"athematics. !t generates all partial products and their sum
in one step. This also gives chances for modular design
where smaller block can be used to design the bigger one.
#o the design complexity gets reduced for inputs of larger
no of bits and modularity gets increased. The proposed
Vedic multiplier is coded in V$%& 'Very $igh #peed
!ntegrated Circuits $ardware %escription &anguage(
synthesi)ed and simulated using *%A '*lectronic %esign
Automation( tool + ,ilinx!#*-..-i. /inally the results are
compared with Conventional multipliers to show the
significant improvement in its efficiency in terms of path
delay 'speed(. The high speed processor requires high speed
multipliers and the Vedic "ultiplication technique is very
much suitable for this purpose.
!ndex Terms:% Architecture 0ipple Carry '0C( Adder
"ultiplication Vedic "athematics Vedic "ultiplier 'V"(
1rdhava Tiryakbhyam #utra
I0 INT12-,3TI2N
Multipliers are extensively used in Microprocessors,
DSP and Communication applications. For higher order
multiplications, a huge number of adders are to be used
to perform the partial product addition. The need of
high speed multiplier is increasing as the need of high
speed processors are increasing. igher throughput
arithmetic operations are important to achieve the
desired performance in many real time signal and image
processing applications. !ne of the "ey arithmetic
operations in such applications is multiplication and the
development of fast multiplier circuit has been a sub#ect
of interest over decades. $educing the time delay and
po%er consumption are very essential re&uirements for
many applications0 'n the past multiplication %as
implemented generally %ith a se&uence of addition,
subtraction and shift operations. T%o most common
multiplication algorithms follo%ed in the digital
hard%are are array multiplication algorithm and (ooth
multiplication algorithm. Due to the importance of
digital multipliers in DSP, it has al%ays been an active
area of
research. )edic mathematics is the name given to the
ancient system of mathematics, %hich %as rediscovered
from the
*anu'cri)t received on June 22" 2(&2.
*r'0 .u'h)alata #er$a, M.*. Scholar +CT,-, SSC*T, (hilai,
Chhattisgarh, 'ndia.
-r0 /0 /0 *ehta, .or"ing as Professor / ead of Department in
Computer Science / *ngineering at SSC*T, (hilai, Chhattisgarh,
'ndia.
ancient 'ndian
scriptures bet%een
0100 and 0102 by
3agadguru S%ami Sri
(harati 4risna
Tirtha#i +022560178-,
a scholar of Sans"rit,
mathematics, history
and philosophy. The
%hole of )edic
mathematics is based
on 07 )edic sutras,
%hich are actually
%ord formulae
describing natural
%ays of solving a
%hole range of
mathematical
problems 90:.
The paper is
organi;ed as follo%s.
Section '' describes
the basic methodology
of )edic
multiplication
techni&ue. Section '''
describes the
proposed multiplier
architecture based on
)edic multiplication
and the generali;ed
algorithm for <x< bit
)edic multiplier.
Section ') describes
the design and
implementation of
)edic multiplier
module in
=ilinx'S*0>.0.
Section ) comprises
of $esult and
Discussion in %hich
device utili;ation
summary and
computational path
delay obtained for the
proposed )edic
multiplier +after
synthesis- is
discussed. Finally
Section )' comprises
of Conclusion.
II0 #E-I3
*,4TI.4I3ATI2N
TE35NI6,E
The use of )edic
mathematics lies in
the fact that it reduces the typical calculations
in conventional mathematics to very simple
one. This is so because the )edic formulae are
claimed to be based on the natural principles
on %hich the human mind %or"s. )edic
Mathematics is a methodology of arithmetic
rules that allo% more efficient speed
implementation. 't also provides some
effective algorithms %hich can be applied to
various branches of engineering such as
computing.
A. Urdhva Tiryakbhyam Sutra
The proposed )edic multiplier is based on the
?@rdhv TiryagbhyamA+algorithm-sutra.TheseSutras
have been traditionally used for the multiplication of
t%o numbers in the
decimal number system. 'n this %or", %e
apply the same ideas to the binary number
system to ma"e the proposed algorithm
compatible %ith the digital hard%are. 't is a
general multiplication formula applicable to
all cases of
multiplicationVertically.'tandliterallyCrosswiseA.
't is based on a novel concept through %hich
the generation of all partial products can be
done %ith the
concurrent
addition of these
partial products.
The algorithm
can be
generali;ed for n
x n bit number.
Since the partial
products and
their sums are
calculated in
parallel, the
multiplier is
independent of
the cloc"
fre&uency of the
processor. Due
to its regular
structure, it can
be easily layout
in
microprocessors
and designers
can easily
circumvent these
problems to avoid
catastrophic device
failures. The
processing po%er of
multiplier can easily
be increased by
increasing the input
and output data bus
%idths since it has a
&uite a regular
structure. Due to its
regular structure, it
can be easily layout in
a silicon chip. The
Multiplier based on
this sutra has the
advantage that as the
number of bits
increases, gate delay
and area increases
very slo%ly as
compared to other
conventional
multipliers.
7
!
I$)le$entation of an Efficient *ulti)lier +a'ed on #edic *athe$atic' u'ing E-A Tool
B. Multiplication of two decimal
numbers ! " #$%
To illustrate this scheme, let us
consider the multiplication of t%o
decimal numbers >B> x 257 by
@rdhva6Tirya"bhyam method as sho%n
in Fig. 0. The digits on the both sides
of the line are multiplied and added
%ith the carry from the previous step.
This generates one of the bits of the
result and a carry. This carry is added
in the next step and hence the process
goes on. 'f more than one line are there
in one step, all the results are added to
the previous carry. 'n each step, least
significant bit acts as the result bit and
all other bits act as carry for the next
step. 'nitially the carry is ta"en to be
;ero.
8ig0 & *ulti)lication of t9o
deci$al nu$+er' 2!2 : 4;
III0 T5E .12.2SE-
*,4TI.4IE1 A135ITE3T,1E
The hard%are architecture of >=>,
5x5 and 2x2 bit )edic multiplier
module are displayed in the belo%
sections. ere,
?@rdhva6
TiryagbhyamA+Verticallyand
Crosswise- sutra is used to propose
such architecture for the
multiplication of t%o binary
numbers. The beauty of )edic
multiplier is that here partial product
generation and additions are done
concurrently. ence, it is %ell
adapted to parallel processing. The
feature ma"es it more attractive for
binary multiplications. This in turn
reduces delay, %hich is the primary
motivation behind this %or".
A. Vedic Multiplier for " bit
Module
The method is explained belo% for
t%o, > bit numbers A and B %here A C
a0a8 and B C b0b8 as
sho%n in Fig. >. Firstly,
the least significant bits
are multiplied %hich
gives the least
significant bit of the
final product +vertical-.
Then, the DS( of the
multiplicand is
multiplied %ith the next
higher bit of the
multiplier and added
%ith, the product of
DS( of multiplier and
next higher bit of the
multiplicand
+cross%ise-. The sum
gives second bit of the
final product and the
carry is added %ith the
partial product obtained
by multiplying the most
significant bits to give
the sum and carry. The
sum is the third
corresponding bit and
carry becomes the
fourth bit of the
final product.
s8 C a8b8E
The final
result %ill be
c>s>s0s8. This
multiplication
method is
applicable for
all the cases.
8ig0 2 The #edic
*ulti)licat
ion *ethod
for t9o 2%
+it <inary
Nu$+er'
The >=>
)edic multiplier
module is
implemented
using four input
,<D gates /
t%o half6adders
%hich is
displayed in its
bloc" diagram
in Fig. F. 't is
found that the
hard%are
architecture of
>x> bit )edic
multiplier is
same as the
hard%are
architecture of
>x> bit
conventional
,rray Multiplier
9>:. ence it is
concluded that
multiplication of
> bit binary
numbers by
)edic method
does not made
significant effect in impro
efficiency. )ery precisely
%e can state that the total
delay is
only >6half adder
delays, after final
bit products are
generated, %hich
is very similar to
,rray multiplier.
So %e s%itch
over to the
implementation
of 5x5 bit )edic
multiplier %hich
uses the >x> bit
multiplier as a
basic building
bloc". The same method
can be extended for input
bits 5 / 2. (ut for higher
no. of bits in input, little
modification is re&uired.
8ig0 = <loc> -iagra$ of 2:2
+it #edic
*ulti)lier
B. Vedic Multiplier
for $"$ bit Module
The 5x5
bit )edic
multiplier
module is
implemente
d using four
>x> bit
)edic
multiplier
modules as
discussed in
Fig. F.
DetGs analy;e 5x5,
multiplicat,,,and(C
F
(
F
(
>
(
0
(
8
. The
output line for the
multiplication result is HS
I
S S S S S S S DetGs divide , and, (
i
7 B 5 F > 0 8 . F
,
>
/ ,
0
,
8
for ,
and (
F
(
>
/
(
0
(
8
for (.
@sing the
fundamental of
)edic
multiplication,
ta"ing t%o bit at
a time
and using > bit
multiplier
bloc", %e can
have the
follo%ing
structure for
multiplication
as sho%n in Fig.
5.
c0s0 C a0b8 J a8b0E +>-
cs> C c0 J a&b&E +F-
7;
8ig0 4 Sa$)le .re'entation for 4:4 +it #edic
*ulti)lication
*ach bloc" as sho%n above is >x> bit )edic multiplier.
First >x> bit multiplier inputs are ,
0
,
8
and (
0
(
8
. The last
bloc" is >x> bit multiplier %ith inputs ,
F
,
>
and (
F
(
>
. The
middle one sho%s t%o >x> bit multiplier %ith inputs ,
F
,
>
/ (
0
(
8
and ,
0
,
8
/ (
F
(
>
. So the final result of
multiplication, %hich is of 2 bit, S
I
S
7
S
B
S
5
S
F
S
>
S
0
S
8
. To
understand the concept, the (loc" diagram of 5x5 bit )edic
multiplier is sho%n in Fig. B. To get final product +S
I
S
7
S
B
S
5
S
F
S
>
S
0
S
8
-, four >x> bit )edic multiplier +Fig. F- and
three 56bit $ipple6Carry +$C- ,dders are re&uired.
The proposed )edic multiplier can be used to reduce delay.
*arly literature spea"s about )edic multipliers based on array
multiplier structures. !n the other hand, %e proposed a ne%
architecture, %hich is efficient in terms of speed. The
arrangements of $C ,dders sho%n in Fig. B, helps us to reduce
delay. 'nterestingly, 2x2 )edic multiplier modules are
implemented easily by using four 5x5 multiplier modules.
8ig0 ; <loc> -iagra$ of : +it #edic *ulti)lier
'. (enerali)ed Al*orithm for + " + bit Vedic Multiplier
.e can generali;e the method as discussed in the previous
sections for any number of bits in input. Det, the
multiplication of t%o <6bit binary numbers +%here < C 0, >,
FK<, must be in the form of >
<
- A and B %here , C ,
<
.....,
F
,
>
,
0
and ( C (
<
K.(
F>
(
0
. The final multiplication result
%ill be of +< J <- bits as S C S
+< J <-
....S
F
S
>
S
0
.
Ste) &: Divide the multiplicand , and multiplier ( into t%o
e&ual parts, each consisting of 9< to +<L>-J0: bits and 9<L>
to 0: bits respectively, %here first part indicates the MS( and
8ig0 ! <loc> -iagra$ of 4:4 +it #edic *ulti)lier
other represents DS(.
C. Vedic Multiplier for #"# bit Module
Ste) 2: $epresent the parts of , as ,
M
and ,
D
, and parts of (
The 2x2 bit )edic multiplier module as sho%n in the bloc"
as (
M
and (
D
. <o% represent , and ( as ,
M
,
D
and (
M
(
D
diagram in Fig. 7 can be easily implemented by using four 5x5 respectively.
bit )edic multiplier modules as discussed in the previous
Ste) =: For , = (, %e have general format as sho%n in Fig.
section. DetGs analy;eiplications,say ,C2x2,
I
,
7
,mult
B
,
5
,
F
,
>
,
0
,
8
and (C (
I
(
7
(B(
5
(
F
(
>
(
0
(
8
. The output line
for the multiplication result %ill be of 07 bits as HS
0B
S
05
S
0F
S
0>
S
00
S
08
S
1
S
2
S
I
S
7
S
B
S
5
S
F
S
>
S
0
S
8.
DetGs divide
t%o parts, say the 2 bit multiplicand , can be decomposed
into pair of 5 bits ,6,D. Similarly multiplicand ( can be
I
decomposed into (6(D. The 07 bit product can be %ritten
asM 8ig0 7 ?eneral 1e)re'entation for
77
International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249 9!" #olu$e%&" I''ue%!" June 2(&2
P C , x ( C +,6,D- x +(6(D-
C , x ( J +, x (D J ,D x (- J ,D x (D
@sing the fundamental of )edic multiplication, ta"ing four
bits at a time and using 5 bit multiplier bloc" as discussed %e
can perform the multiplication. The outputs of 5x5 bit
multipliers are added accordingly to obtain the final product.
ere total three 2 bit $ipple6Carry ,dders are re&uired as
sho%n in Fig. 7.
I$)le$entation of an Efficient *ulti)lier +a'ed on #edic *athe$atic' u'ing E-A Tool
#edic
*ulti)lication
Ste) 4: The individual multiplications
product can be obtained by the
partitioning method and applying the
basic building bloc"s.
(y adopting the above generali;ed
algorithm %e can implement )edic
Multiplier for any number of bits say 07,
F>, 75, and so on, as per the re&uirement.
Therefore, it could be possible to
implement this )edic multiplier in the
,D@ +,rithmetic Dogic @nit- %hich %ill
reduce the computational speed
drastically / hence improves the
processors efficiency.
I#0 I*.4E*ENTATI2N IN
@I4IN@ &20&
'n this %or", 2x2 bit )edic multiplier
is designed in )DD
+)ery igh Speed 'ntegrated Circuits
ard%are Description Danguage-. Dogic
synthesis and simulation %as done using
*D, +*lectronic Design ,utomation-
tool in =ilinx'S*0>.0i 6 Pro#ect
<avigator and 'Sim simulator integrated
in the =ilinx pac"age. The performance
of circuit is evaluated on the =ilinx
device family SpartanF, pac"age t&055
and speed grade 6B.
The $TD schematic of 2x2 bit )edic
multiplier
?vedicNmulticomprisesstruct2x2Aoffou
r5x5bit)edic
multipliervedicstruct5x5?N0A6 vm0,
vm>, vmF, vm5 and three I6bit $ipple
Carry ,dder ?rcNadderN2A6r0, r>, rF as
sho%n in Fig. 2 %hile the simulation
results obtained are sho%n in Fig. 1 for
verification. 'n behavioral simulation
%e have tested for the follo%ing input
bitsM 6
8ig0 9 Si$ulation
1
e'
ul
t
of
:

+i
t
#e
di
c
*
ul
ti
)l
ie
r
(!
:;
A=
(
B
:
=A
24
)
#0
1ES,4T
AN-
-IS3,SSI
2N
The synthesis result
obtained from proposed
)edic multiplier is faster
than ,rray and (ooth
multiplier. The device
utili;ation summary of
2x2 bit )edic multiplier
for =ilinx, Spartan
family is sho%n belo%M
-evice ,tiliCation Su$$ary:
Selected DeviceM FsB8at &0556B
<umber of SlicesM 1B out of I85 0FO
<umber of 5 input D@TsM 077 out of 0582 00O
<umber of '!sM F>
<umber of bonded '!(sM F> out of 082 >1O
a- For 2x2 bit )edic multiplier input, the multiplier
aC?88888080A decimal+ number system B- and multiplicand
bC?88888008A
+decimal number076
bitcomputationalsystem
pathdelay7-in
nanosecondsand%e+ns-.
Thegetpath delay
output0C
?8888888888800008A
+decimal-.for2x2bit,rr
aynumberand(oothmul
tiplierssystemhavebeen
F8ta"en from S.S.
4erur et al. 900:. The
timing result sho%s
that )edic b- ,gain,
%e have multiplier
aC88880888A
multiplier+decimalhasth
egreatest advantage as
compared to other
n
u
m
b
e
r
s
y
s
t
e
m

2
-
a
n
d

m
u
l
t
i
p
l
i
c
a
n
d

b
C
?
8
8
8
8
8
0
0
8
A

m
u
l
t
i
p
l
i
e
r
s
+
d
e
c
i
m
a
l
i
n
t
e
r
m
s
o
f

e
x
e
c
u
t
i
o
n

t
i
m
e
.

n
u
m
b
e
r

s
y
s
t
e
m

F
-

%
i
t
h

0
7
6
b
i
t

o
u
t
p
u
t
0
C
?
8
8
8
8
8
8
8
8
8
8
8
0
0
8
8
8
A
+decimal
number
system >5-.
Ta+le & 3o$)ari'on of : +it *ulti)lier' (in n')
-evice: S)artan Array <ooth
:c='!(a%!%tD&44
*ulti)lier *ulti)lier
Path Delay F>.808 ns >1.B51 ns
#I0 32N34,SI2N
This paper presents a highly efficient method of
multiplication H ?@rdhva Tirya"bhyam SutraAbased on
)edic mathematics. 't gives us method for hierarchical
multiplier design and clearly indicates the computational
advantages offered by )edic methods. The computational
path delay for proposed 2x2 bit )edic multiplier is found to
be >0.7I1 ns. ence our motivation to reduce delay is finely
fulfilled. Therefore, %e observed that the )edic multiplier is
much more efficient than ,rray and (ooth multiplier in terms
of execution time +speed-. ,n a%areness of )edic
mathematics can be effectively increased if it is included in
engineering education. 'n future, all the ma#or universities
may set up appropriate research centers to promote research
8ig0 1T4 'che$atic of : +it #edic *ulti)lier
%or"s in )edic mathematics.
7
International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249 9!" #olu$e%&" I''ue%!" June 2(&2
1E8E1EN3ES
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[2] M. Morris Mano, ?Computer System ,rchitectureA, F
rd
edition,
Prientice6all, <e% 3ersey, @S,, 011F, pp. F576F52.
[3] . Thapliyal and 6,rea.$6Po%er,rbania*fficient. ?, Time
Multiplier and S&uare ,rchitecture (ased !n ,ncient 'ndian )edic
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[5] Thapliyal . andigh SpeedSrinivas*fficient<x< (itM .(, ?
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%%%.%aset.orgSpring>882.
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(eom Cho,Multiplier design? based on ancient 'ndian )edic
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>882.
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0B60I, >881.
[10] Sumita )aidya and Deepa"6Po%erPerformanceDande"ar, ?Delay
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>80>.
[15] @mesh ,"are, T.). More and $.S. Don"ar, ?Performance *valuation and Synthesis of )edic MultiplierA, <ational Conference on
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Proceedings published by 'nternational 3ournal of Computer
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*r'0 .u'h)alata #er$a obtained her (. Sc +Computer Science- in >88B
from (.M.M., (hilai and M. Sc. +Computer Science- in >88I from
S.S.M.)., (hilai. She is pursuing her M.*. in Computer Technology and
,pplication +CT,- from Shri Shan"aracharya College of *ngineering /
Technology +SSC*T- (hilai +C.P.- 'ndia. Presently she is %or"ing as
,ssistant Professor in Central College of *ngineering / Technology
+CC*M-, $aipur +C.P.- 'ndia.
-r0 /0 /0 *ehta obtained his (.*. +Computers- in 0115 from 4'TS
$amte" and M.Tech +Computers- from P*C $aipur in >88>. e is Ph.D. in
Computers by Technical @niversity of Chhattisgarh State. Presently he is
%or"ing as Professor / Dept ead at Shri Shan"aracharya College of
*ngineering / Technology +SSC*T- (hilai +C.P.- 'ndia. is research area
includes Do% Po%er Micro *lectronics, (us *ncoding Scheme,
Cryptography and (iometric based application development. e is a life
member of '*', 'ST*, CS' and )S' '<D',.
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