IEP BAHGAT Group ADC001

8-Bit, 27MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES
- INTERNAL/EXTERNAL REFERENCE OPTION
- SINGLE-ENDED OR DIFFERENTIAL ANALOG INPUT
- WIDE INPUT RANGE: 2Vp-p
- +5V SUPPLY OPERATION for Analog Domain
- +3V SUPPLY for Digital Domain
- JLCC-68 PACKAGE

APPLICATIONS
- VIDEO DIGITIZING

DESCRIPTION
The ADC001 is a pipeline, CMOS Analog-to-Digital (A/D) converter that operates from a single +5V
power supply. This converter provides excellent performance with a single ended input and can be
operated with a differential input for added spurious performance. This high performance converter
includes an 8-bit quantizer, and a high accuracy internal reference. It also allows for the user to disable
the internal reference and utilize external references. This external reference option is useful in
applications where DC full
scale range adjustment is required. The ADC001 employs digital error correction techniques to provide
excellent differential linearity for demanding Video applications. The ADC001 is specified at a maximum
sampling frequency of 30MHz and a single-ended input range of 1.5V to 3.5V. The ADC001 is available in
a JLCC-68 package and integrated in the same package is a high speed DAC for Video Applications.



ELECTRICAL CHARACTERISTICS




PARAMETER


CONDITIONS

ADC001

UNITS
Resolution
Analog Input Range
Single Input Range
V-clamp Range
Differential Input Range
Common mode Range
Analog i/p bias current
Input Bandwidth

Conversion characteristics
Sample rate
Data Latency

Digital output range
Analog Power Supply
Digital Power Supply
Dynamic Characteristics
DNL
INL
SFDR
SNR
ENOB












































PIN DESCRIPTIONS

PIN DESIGNATOR DESCRIPTION PIN DESIGNATOR DESCRIPTION
1 Data(1) Memory 35 Vpin_DAC 10KOhm R 1%
2 Data(0) Memory 36 Vclamp ADC input diff
3 oe Memory 37 Vin ADC input
4 we Memory 38 Refp 3V ext ref
5 sel Memory 39 Refn 2V ext ref
6 Vdd_d 3V digital supply 40 Vcm 2.5V ext ref
7 Gnd_d Digital ground 41 Vref_ADC 1.2 V int/ext
8 Q(5) Memory 42 N.C.
9 N.C. 43 N.C.
10 Q(4) Memory 44 Vpin_ADC 10KOhm R 1%
11 Q(3) Memory 45 AGND Analog ground
12 Q(2) Memory 46 AVDD_5V 5V analog supply
13 Q(1) Memory 47 Vdd_d 3V digital supply
14 Q(0) Memory 48 Gnd_d Digital ground
15 Vdd_d 3V digital supply 49 Adc(0) ADC LSB
16 Gnd_d Digital ground 50 Adc(1) ADC o/p
17 Gnd_d Digital ground 51 Adc(2) ADC o/p
18 Clk_DAC DAC 52 Adc(3) ADC o/p
19 Vdd_d 3V digital supply 53 Adc(4) ADC o/p
20 Bit(0) DAC LSB 54 Adc(5) ADC o/p
21 Bit(1) DAC i/p 55 Adc(6) ADC o/p
22 Bit(2) DAC i/p 56 Adc(7) ADC MSB
23 Bit(3) DAC i/p 57 Clk_ADC ADC clk
24 Bit(4) DAC i/p 58 Gnd_d Digital ground
25 Bit(5) DAC i/p 59 Vdd_d 3V digital supply
26 Bit(6) DAC i/p 60 A(4) Memory
27 Bit(7) DAC MSB 61 N.C.
28 N.C. 62 N.C.
29 Blank DAC input 63 A(3) Memory
30 Offset DAC input 64 A(2) Memory
31 AGND Analog ground 65 A(1) Memory
32 AVDD_5V 5V analog supply 66 A(0) Memory
33 Vref_DAC 1.2 V ext/int option 67 Data(3) Memory
34 Ioutp DAC output pin 68 Data(2) Memory











PIN CONFIGURATION



















APPLICATION INFORMATION

THEORY OF OPERATION
The ADC001 is a high-speed CMOS A/D converter which employs a pipelined converter architecture consisting
of 7 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential
linearity and no missing codes at the 8-bit level. The output data becomes valid on the rising clock edge. The
pipeline architecture results in a data latency of 4 clock cycles.
The analog input of the ADC001 is a differential track and hold, see Figure below. The differential topology
along with tightly matched capacitors produces a high level of ac performance while sampling at very high rates.
The ADC001 allows its analog inputs to be driven either single-ended or differentially. The typical configuration
for the ADC001 is for the single-ended mode in which the input track and hold performs a single-ended to
differential conversion of the analog input signal.

In case of single ended operation, Vclamp is the lower level voltage the input signal is clamped too (i.e. it is the
00000000 level)

In case of differential operation, Vin and Vin_diff should be coupled around a common mode voltage equal to
AVDD/2 (2.5 V)










REFERENCE OPERATION
Figure below depicts the simplified model of the internal reference circuit. The internal blocks are the band-gap voltage
reference. The pin Vref_ADC (P 41) is the output of the band-gap reference circuit. This reference is the input of an
opamp circuit used to generate bias currents. In case of the need of higher accuracy, or if the band-gap reference is not
working as required, external reference could be used on this pin of value 1.2 V or what is required.
External biasing should be used on pins refp (P 38), refn (P 39), and vcm (P40)
To ensure proper operation with any reference configurations, it is necessary to provide solid bypassing at the reference
pins in order to keep the clock feed-through to a minimum. All bypassing capacitors should be located as close to their
respective pins as possible. A combination of 0.1uF and 10uF capacitors is recommended to be used on all the reference
pins..






DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high speed, high resolution Analog to Digital Converters. It leads to
aperture jitter which adds noise to the signal being converted. The ADC001 samples the input signal on the rising edge of
the CLK input. Therefore, this edge should have the lowest possible jitter.

Digital Outputs
It is recommended to keep the capacitive loading on the data lines as low as possible (< 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the
analog portion of the ADC001 and affect the performance. If necessary, external buffers or latches close to the converters
output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADC001
from any digital noise activities on the bus coupling back high frequency noise.

Digital Output Driver (VDD_D)
The ADC001 features a dedicated supply pin for the output logic drivers, VDD_D, which is not internally connected to
the other supply pins. The output stages are designed to supply sufficient current to drive a variety of logic families.
However, it is recommended to use the ADC001 with +3V logic supply. This will lower the power dissipation in the output
stages due to the lower output swing and reduce current glitches on the supply line which may affect the ac performance of
the converter. In some applications, it might be advantageous to decouple the VDD_D pin with additional capacitors or a
pi-filter.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high
frequency designs. Multilayer PC boards are recommended for best performance since they offer distinct advantages like
minimizing ground impedance, separation of signal layers by ground layers, etc. The ADC001 should be treated as an
analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most
consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the
converter and degrade the achievable performance.
All ground connections on the ADC001 are internally joined together. The ground pins should directly connect to an analog
ground plane which covers the PC board area around the converter. While designing the layout, it is important to keep the
analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path. Because of its
high sampling rate, the ADC001 generates high frequency current transients and noise (clock feed through) that are fed
back into the supply and reference lines. This requires that all supply and reference pins are sufficiently bypassed.
Figure below shows the recommended decoupling scheme for the ADC001. In most cases 0.1 nF ceramic chip capacitors at
each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. In addition,
a larger bipolar capacitor 1uF to 22uF should be placed on the PC board in proximity of the converter circuit.