a

FUNCTIONAL BLOCK DIAGRAM

12/8
CS
A
0
CE
R/C
REF OUT

AGND

A
AAAA
AA
A
AAAAAA
AA
CONTROL

10V
REF

CLOCK

12

COMP

20k
REF IN

5k

BIP OFF
20V

IN

10VIN

SAR

12

10k

10k

5k

DAC

IDAC

2.5k
2.5k

5k

SHA

REGISTERS / 3-STATE OUTPUT BUFFERS

FEATURES
Complete Monolithic 12-Bit 10 ms Sampling ADC
On-Board Sample-and-Hold Amplifier
Industry Standard Pinout
8- and 16-Bit Microprocessor Interface
AC and DC Specified and Tested
Unipolar and Bipolar Inputs
65 V, 610 V, 0 V10 V, 0 V20 V Input Ranges
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 and SMD Compliant Versions Available

12-Bit 100 kSPS

A/D Converter
AD1674*

12

STS

DB11 (MSB)
DB0 (LSB)

AD1674

PRODUCT DESCRIPTION

PRODUCT HIGHLIGHTS

The AD1674 is a complete, multipurpose, 12-bit analog-todigital converter, consisting of a user-transparent onboard
sample-and-hold amplifier (SHA), 10 volt reference, clock and
three-state output buffers for microprocessor interface.

1. Industry Standard Pinout: The AD1674 utilizes the pinout

established by the industry standard AD574A and AD674A.

The AD1674 is pin compatible with the industry standard

AD574A and AD674A, but includes a sampling function while
delivering a faster conversion rate. The on-chip SHA has a wide
input bandwidth supporting 12-bit accuracy over the full
Nyquist bandwidth of the converter.
The AD1674 is fully specified for ac parameters (such as S/(N+D)
ratio, THD, and IMD) and dc parameters (offset, full-scale
error, etc.). With both ac and dc specifications, the AD1674 is
ideal for use in signal processing and traditional dc measurement applications.
The AD1674 design is implemented using Analog Devices
BiMOS II process allowing high performance bipolar analog circuitry to be combined on the same die with digital CMOS logic.
Five different temperature grades are available. The AD1674J
and K grades are specified for operation over the 0C to +70C
temperature range. The A and B grades are specified from
40C to +85C; the AD1674T grade is specified from 55C
to +125C. The J and K grades are available in both 28-lead
plastic DIP and SOIC. The A and B grade devices are available
in 28-lead hermetically sealed ceramic DIP and 28-lead SOIC.
The T grade is available in 28-lead hermetically sealed ceramic
DIP.

2. Integrated SHA: The AD1674 has an integrated SHA which

supports the full Nyquist bandwidth of the converter. The
SHA function is transparent to the user; no wait-states are
needed for SHA acquisition.
3. DC and AC Specified: In addition to traditional dc specifications, the AD1674 is also fully specified for frequency domain ac parameters such as total harmonic distortion,
signal-to-noise ratio and input bandwidth. These parameters
can be tested and guaranteed as a result of the onboard
SHA.
4. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges:
0 V to +10 V and 0 V to +20 V unipolar, 5 V to +5 V and
10 V to +10 V bipolar. The AD1674 operates on +5 V and
12 V or 15 V power supplies.
5. Flexible Digital Interface: On-chip multiple-mode
three-state output buffers and interface logic allow direct
connection to most microprocessors.

*Protected by U. S. Patent Nos. 4,962,325; 4,250,445; 4,808,908; RE30586 .

REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700
Fax: 617/326-8703

AD1674SPECIFICATIONS
(TMIN to TMAX, VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = 15 V 6 10% or

DC SPECIFICATIONS 12 V 6 5% unless otherwise noted)

Parameter

Min

RESOLUTION

12

AD1674J
Typ

Min

AD1674K
Typ
Max

12

12

Unit
Bits

INTEGRAL NONLINEARITY (INL)

DIFFERENTIAL NONLINEARITY (DNL)
(No Missing Codes)

Max

1/2

12

LSB

Bits

UNIPOLAR OFFSET 1 @ +25C

LSB

BIPOLAR OFFSET1 @ +25C

LSB

0.25

% of FSR

+70

FULL-SCALE ERROR1, 2 @ +25C

(with Fixed 50 Resistor from REF OUT to REF IN)
TEMPERATURE RANGE

0.1
0

0.25
+70

0.1
0

TEMPERATURE DRIFT 3
Unipolar Offset2
Bipolar Offset2
Full-Scale Error2

2
2
6

1
1
3

LSB
LSB
LSB

POWER SUPPLY REJECTION

VCC = 15 V 1.5 V or 12 V 0.6 V
VLOGIC = 5 V 0.5 V
VEE = 15 V 1.5 V or 12 V 0.6 V

2
1/2
2

1
1/2
1

LSB
LSB
LSB

+5
+10
+10
+20

Volts
Volts
Volts
Volts

7
14

k
k

+5.5
+16.5
11.4

Volts
Volts
Volts

ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
POWER SUPPLIES
Operating Voltages
VLOGIC
VCC
VEE
Operating Current
ILOGIC
ICC
IEE

5
10
0
0
3
6

+4.5
+11.4
16.5

POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads) 4
(External Load Should Not Change During Conversion

5
10

9.9

+5
+10
+10
+20

5
10
0
0

7
14

3
6

+5.5
+16.5
11.4

+4.5
+11.4
16.5

5
10

5
10
14

8
14
18

5
10
14

8
14
18

mA
mA
mA

385

575

385

575

mW

10.0

10.1
2.0

10.0

10.1
2.0

Volts
mA

9.9

NOTES
1
Adjustable to zero.
2
Includes internal voltage reference error.
3
Maximum change from 25C value to the value at T MIN or TMAX.
4
Reference should be buffered for 12 V operation.
All min and max specifications are guaranteed.
Specifications subject to change without notice.

REV. C

AD1674

Parameter

Min

RESOLUTION

12

AD1674A
Typ Max

12

BIPOLAR OFFSET @ +25C

FULL-SCALE ERROR1, 2 @ +25C
(with Fixed 50 Resistor from REF OUT to REF IN)

0.1
40

AD1674T
Typ Max

Unit
Bits

1/2
1/2
12

Min
12

1
1

UNIPOLAR OFFSET 1 @ +25C

TEMPERATURE RANGE

AD1674B
Typ Max

12

INTEGRAL NONLINEARITY (INL)

DIFFERENTIAL NONLINEARITY (DNL)
(No Missing Codes)

Min

1/2
1
12

LSB
LSB
Bits

LSB

LSB

0.125

% of FSR

+125

0.25
+85

0.1
40

0.125
+85

0.1
55

TEMPERATURE DRIFT 3
Unipolar Offset2
Bipolar Offset2
Full-Scale Error2

2
2
8

1
1
5

1
2
7

LSB
LSB
LSB

POWER SUPPLY REJECTION

VCC = 15 V 1.5 V or 12 V 0.6 V
VLOGIC = 5 V 0.5 V
VEE = 15 V 1.5 V or 12 V 0.6 V

2
1/2
2

1
1/2
1

1
1/2
1

LSB
LSB
LSB

+5
+10
+10
+20

Volts
Volts
Volts
Volts

5
10

7
14

k
k

+5.5
+16.5
11.4

Volts
Volts
Volts

ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
POWER SUPPLIES
Operating Voltages
VLOGIC
VCC
VEE
Operating Current
ILOGIC
ICC
IEE

5
10
0
0
3
6

+4.5
+11.4
16.5

POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads) 4
(External Load Should Not Change During Conversion

REV. C

5
10

9.9

+5
+10
+10
+20

5
10
0
0

7
14

3
6

5
10

+5.5 +4.5
+16.5 +11.4
11.4 16.5

+5
+10
+10
+20

5
10
0

7
14

3
6

+5.5 +4.5
+16.5 +11.4
11.4 16.5

5
10
14

8
14
18

5
10
14

8
14
18

5
10
14

8
14
18

mA
mA
mA

385

575

385

575

385

575

mW

10.0

10.1
2.0

10.0

10.1
2.0

10.0

10.1
2.0

Volts
mA

9.9

9.9

AD1674SPECIFICATIONS
AC SPECIFICATIONS

(TMIN to TMAX, with VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = 15 V 610% or
12 V 6 5%, fSAMPLE = 100 kSPS, fIN = 10 kHz, stand-alone mode unless otherwise noted)1

Parameter

Min

Signal to Noise and Distortion (S/N+D) Ratio2, 3

AD1674J/A
Typ
Max

69

70

Min

AD1674K/B/T
Typ
Max

70

Units

71

dB

Total Harmonic Distortion (THD)

90

82
0.008

90

82
0.008

dB
%

Peak Spurious or Peak Harmonic Component

92

82

92

82

dB

Full Power Bandwidth

Full Linear Bandwidth

1
500

Intermodulation Distortion (IMD)5

Second Order Products
Third Order Products

90
90

SHA (Specifications are Included in Overall Timing Specifications)

Aperture Delay
Aperture Jitter
Acquisition Time

50
250
1

1
500

MHz
kHz

80
80

90
90

80
80

dB
dB

50
250
1

ns
ps
s

(for all grades TMIN to TMAX, with VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%,
EE = 15 V 6 10% or 12 V 6 5%)

DIGITAL SPECIFICATIONS V
Parameter

LOGIC INPUTS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current (VIN = 5 V)
IIL
Low Level Input Current (VIN = 0 V)
CIN
Input Capacitance
LOGIC OUTPUTS
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOZ
High-Z Leakage Current
COZ
High-Z Output Capacitance

Test Conditions

Min

Max

Units

VIN = VLOGIC
VIN = 0 V

+2.0
0.5
10
10

VLOGIC +0.5 V
+0.8
+10
+10
10

V
V
A
A
pF

+0.4
+10
10

V
V
A
pF

IOH = 0.5 mA
IOL = 1.6 mA
VIN = 0 to VLOGIC

+2.4
10

NOTES
1
fIN amplitude = 0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to 0 dB (9.997 V p-p) input signal unless
otherwise noted.
2
Specified at worst case temperatures and supplies after one minute warm-up.
3
See Figures 12 and 13 for other input frequencies and amplitudes.
4
See Figure 11.
5
fa = 9.08 kHz, fb = 9.58 kHz with f SAMPLE = 100 kHz. See Definition of Specifications section and Figure 15.
All min and max specifications are guaranteed.
Specifications subject to change without notice.

REV. C

AD1674
SWITCHING SPECIFICATIONS

(for all grades TMIN to TMAX with VCC = +15 V 6 10% or +12 V 6 5%,
VLOGIC = +5 V 610%, VEE = 15 V 6 10% or 12 V 6 5%; VIL = 0.4 V,
VIH = 2.4 V unless otherwise noted)

CONVERTER START TIMING (Figure 1)

Parameter
Conversion Time
8-Bit Cycle
12-Bit Cycle
STS Delay from CE
CE Pulse Width
CS to CE Setup
CS Low During CE High
R/C to CE Setup
R/C Low During CE High
A0 to CE Setup
A0 Valid During CE High

J, K, A, B, Grades T Grade
Symbol Min Typ Max Min Typ Max Units
tC
tC
tDSC
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC

7
9

8
10
200

50
50
50
50
50
0
50

7
9
50
50
50
50
50
0
50

tHEC

CE
__
CS

8
s
10 s
225 ns
ns
ns
ns
ns
ns
ns
ns

tHSC
tSSC

_
R/C

tSRC

tSAC

A0

tHRC

tHAC
tC

STS

READ TIMINGFULL CONTROL MODE (Figure 2)

Parameter

J, K, A, B, Grades
T Grade
Symbol Min Typ Max Min Typ Max Units

Access Time
Data Valid After CE Low

tDD1
tHD

Output Float Delay

CS to CE Setup
R/C to CE Setup
A0 to CE Setup
CS Valid After CE Low
R/C High After CE Low
A0 Valid After CE Low

tHL5
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR

75

150

252
203

75
252
154

150
50
0
50
0
0
50

50
0
50
0
0
50

tDSC

DB11 DB0

HIGH IMPEDANCE

Figure 1. Converter Start Timing

150 ns
ns
ns
150 ns
ns
ns
ns
ns
ns
ns

CE
__
CS

tHSR

tSSR
_
R/C

tSSR

A0

NOTES
1
tDD is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
2
0C to TMAX.
3
At 40C.
4
At 55C.
5
tHL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.

tHRR

tSAR

tHAR
tHS

STS

tHD
DB11 DB0

HIGH

HIGH

DATA
VALID

IMPEDANCE

tDD

IMP.

tHL

Figure 2. Read Timing

Test

VCP

COUT

Access Time High Z to Logic Low

Float Time Logic High to High Z
Access Time High Z to Logic High
Float Time Logic Low to High Z

5V
0V
0V
5V

100 pF
10 pF
100 pF
10 pF

IOL

DOUT

VCP
COUT

IOH

Figure 3. Load Circuit for Bus Timing Specifications

REV. C

AD1674
TIMINGSTAND-ALONE MODE (Figures 4a and 4b)

Parameter

Symbol

Data Access Time

Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
STS Delay After Data Valid
High R/C Pulse Width

tDDR
tHRL
tDS
tHDR
tHS
tHRH

Min

J, K, A, B Grades
Typ
Max

T Grade
Typ

Min

150
50

Units

150

ns
ns
ns
ns
s
ns

50
200

25
0.6
150

Max

0.8

225
25
0.6
150

1.2

0.8

1.2

NOTE
All min and max specifications are guaranteed.
Specifications subject to change without notice.
tHRL

_
R/C

_
R/C

tDS

tHRH
tDS

STS

STS

tDDR

tC
tHS

tHDR
DB11 DB0

DATA
VALID

DB11 DB0

HIGH-Z

HIGH-Z

tC

tHDR

HIGH-Z

DATA
VALID

DATA VALID

tHL

Figure 4a. Stand-Alone Mode Timing Low Pulse for R/C

ABSOLUTE MAXIMUM RATINGS*

VCC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to + 16.5 V

VEE to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 to 16.5 V
VLOGIC to Digital Common . . . . . . . . . . . . . . . . . . 0 V to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . . 1 V
Digital Inputs to Digital Common . . . 0.5 V to VLOGIC +0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . VEE to VCC
20 VIN to Analog Common . . . . . . . . . . . . . . . . . VEE to +24 V
REF OUT . . . . . . . . . . . . . . . . . Indefinite Short to Common

Figure 4b. Stand-Alone Mode Timing High Pulse for R/C

. . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead Temperature, Soldering (10 sec) . . . . . . . +300C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . . 65C to +150C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1674 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!
ESD SENSITIVE DEVICE

ORDERING GUIDE

Model1

Temperature Range

INL
(TMIN to TMAX)

S/(N+D)
(TMIN to TMAX)

Package
Description

Package
Option2

AD1674JN
AD1674KN
AD1674JR
AD1674KR
AD1674AR
AD1674BR
AD1674AD
AD1674BD
AD1674TD

0C to +70C
0C to +70C
0C to +70C
0C to +70C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
55C to +125C

1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB

69 dB
70 dB
69 dB
70 dB
69 dB
70 dB
69 dB
70 dB
70 dB

Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP

N-28
N-28
R-28
R-28
R-28
R-28
D-28
D-28
D-28

NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current
AD1674/883B data sheet. SMD is also available.
2
N = Plastic DIP; D = Hermetic Ceramic DIP; R = Plastic SOIC.

REV. C

AD1674
PIN DESCRIPTION

Symbol

Pin No. Type

Name and Function

AGND
A0

9
4

P
DI

BIP OFF

12

AI

CE
CS
DB11DB8

6
3
2724

DI
DI
DO

DB7DB4

2320

DO

DB3DB0

1916

DO

DGND
REF OUT
R/C

15
8
5

P
AO
DI

REF IN
STS

10
28

AI
DO

VCC
VEE
VLOGIC
10 VIN

7
11
1
13

P
P
P
AI

20 VIN

14

AI

12/8

DI

Analog Ground (Common).

Byte Address/Short Cycle. If a conversion is started with A0 Active LOW, a full 12-bit conversion
cycle is initiated. If A0 is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/C = 1) with 12/8 LOW, A0 = LOW enables the 8 most significant bits
(DB4DB11), and A0 = HIGH enables DB3DB0 and sets DB7DB4 = 0.
Bipolar Offset. Connect through a 50 resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
Chip Select. Chip Select is Active LOW.
Data Bits 11 through 8. In the 12-bit format (see 12/8 and A0 pins), these pins provide the upper 4 bits of data. In the 8-bit format, they provide the upper 4 bits when A0 is LOW and are
disabled when A0 is HIGH.
Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when Ao is LOW and all zeroes when A0 is HIGH.
Data Bits 3 through 0. In the 12-bit format these pins provide the lower 4 bits of data. In the
8-bit format these pins provide the lower 4 bits of data when A0 is HIGH, they are disabled
when A0 is LOW.
Digital Ground (Common).
+10 V Reference Output.
Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW
for a convert operation. In the stand-alone mode, the falling edge of R/C initiates a conversion.
Reference Input is connected through a 50 resistor to +10 V Reference for normal operation.
Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
+12 V/+15 V Analog Supply.
12 V/15 V Analog Supply.
+5 V Logic Supply.
10 V Span Input, 0 V to +10 V unipolar mode or 5 V to +5 V bipolar mode. When using the
AD1674 in the 20 V Span 10 VIN should not be connected.
20 V Span Input, 0 V to +20 V unipolar mode or 10 V to +10 V bipolar mode. When using
the AD1674 in the 10 V Span 20 VIN should not be connected.
The 12/8 pin determines whether the digital output data is to be organized as two 8-bit words
(12/8 LOW) or a single 12-bit word (12/8 HIGH).

AI
AO
DI
DO
P

=
=
=
=
=

Analog Input
Analog Output
Digital Input
Digital Output
Power

FUNCTIONAL BLOCK DIAGRAM

12/8
CS
A
0
CE
R/C
REF OUT

AGND

A
AA
AA
AA
A
AA
AAAAAA
AA
CONTROL

10V
REF

CLOCK

12

COMP

20k
REF IN

5k

BIP OFF
20V

IN

10VIN

12

10k

10k

5k

DAC

IDAC

2.5k
2.5k

REV. C

SAR

5k

SHA

AD1674

REGISTERS / 3-STATE OUTPUT BUFFERS

TYPE:

12

PIN CONFIGURATION

STS

DB11 (MSB)
DB0 (LSB)

VLOGIC

28

STS

12/8

27

DB11(MSB)

CS

26 DB10

A0

25

DB9

R/C

24

DB8

CE

23

DB7

VCC

22

DB6

REF OUT

21

DB5

AGND

20

DB4

REF IN

10

19

DB3

VEE 11

18

DB2

BIP OFF

12

17

DB1

10VIN

13

16

DB0(LSB)

20VIN

14

15

DGND

AD1674
TOP VIEW
(Not to Scale)

AD1674
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)

The ideal transfer function for an ADC is a straight line drawn

between zero and full scale. The point used as zero
occurs 1/2 LSB before the first code transition. Full scale is
defined as a level 1 1/2 LSB beyond the last code transition.
Integral nonlinearity is the worst-case deviation of a code from
the straight line. The deviation of each code is measured from
the middle of that code.
DIFFERENTIAL NONLINEARITY (DNL)

A specification which guarantees no missing codes requires that

every code combination appear in a monotonic increasing
sequence as the analog input level is increased. Thus every code
must have a finite width. The AD1674 guarantees no missing
codes to 12-bit resolution; all 4096 codes are present over the
entire operating range.
UNIPOLAR OFFSET

The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the
actual transition from that point at 25C. This offset can be
adjusted as shown in Figure 11.
BIPOLAR OFFSET

In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error specifies the
deviation of the actual transition from that point at 25C. This
offset can be adjusted as shown in Figure 12.
FULL-SCALE ERROR

The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10 volts full scale). The full-scale
error is the deviation of the actual level of the last transition
from the ideal level at 25C. The full-scale error can be adjusted
to zero as shown in Figures 11 and 12.

are present in a sample sequence. The result, called Prime

Coherent Sampling, is a highly accurate and repeatable measure
of the actual frequency-domain response of the converter.
NYQUIST FREQUENCY

An implication of the Nyquist sampling theorem, the Nyquist

Frequency of a converter is that input frequency which is onehalf the sampling frequency of the converter.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO

S/(N+D) is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of a full-scale input signal and is expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
INTERMODULATION DISTORTION (IMD)

With inputs consisting of sine waves at two frequencies, fa and

fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa nfb,
where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for
which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa fb) and the third order terms
are (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb). The IMD
products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals are of equal amplitude and the peak value of
their sums is 0.5 dB from full scale. The IMD products are
normalized to a 0 dB input signal.
FULL-POWER BANDWIDTH

The full-power bandwidth is that input frequency at which the

amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.

TEMPERATURE DRIFT

The temperature drifts for full-scale error, unipolar offset and

bipolar offset specify the maximum change from the initial
(25C) value to the value at TMIN or TMAX.
POWER SUPPLY REJECTION

The effect of power supply error on the performance of the

device will be a small change in full scale. The specifications
show the maximum full-scale change from the initial value with
the supplies at various limits.
FREQUENCY-DOMAIN TESTING

The AD1674 is tested dynamically using a sine wave input and

a 2048 point Fast Fourier Transform (FFT) to analyze the
resulting output. Coherent sampling is used, wherein the ADC
sampling frequency and the analog input frequency are related
to each other by a ratio of integers. This ensures that an integral
multiple of input cycles is captured, allowing direct FFT processing without windowing or digital filtering which could mask
some of the dynamic characteristics of the device. In addition,
the frequencies are chosen to he relatively prime (no common
factors) to maximize the number of different ADC codes that

FULL-LINEAR BANDWIDTH

The full-linear bandwidth is the input frequency at which the

slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than 0.1 dB. Beyond this frequency, distortion of the sampled input signal increases significantly.
APERTURE DELAY

Aperture delay is a measure of the SHAs performance and is

measured from the falling edge of Read/Convert (R/C) to when
the input signal is held for conversion.
APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive

samples and is manifested as noise on the input to the A/D.

REV. C

Typical Dynamic PerformanceAD1674

AAAA
AAAA
AAA
AAA

80

fSAMPLE = 100kSPS

AMPLITUDE dB

20

60
20dB INPUT
S/(N+D) dB

THD

40
60
80

10

100

1000

40
30

60dB INPUT
10

2NDHARMONIC

120

50

20

3RD
HARMONIC

100

0dB INPUT

70

FULL-SCALE = +10V

10000

Figure 5. Harmonic Distortion vs.

Input Frequency

100

10

INPUT FREQUENCY kHz

1000

10000

INPUT FREQUENCY kHz

Figure 6. S/(N+D) vs. Input Frequency

and Amplitude

Figure 7. S/(N+D) vs. Input Amplitude

10
20
30
40
AMPLITUDE dB

AMPLITUDE dB

20

60
80
100

40
50
60
70
80
90
100

120

110
120

140
0

10

15

20

25

30

35

40

45

FREQUENCY kHz

50

130
0

Figure 8. Nonaveraged 2048 Point FFT

at 100 kSPS, fIN = 25.049 kHz

10

30
20
25
FREQUENCY kHz

35

40

45

50

Figure 9. IMD Plot for fIN = 9.08 kHz (fa), 9.58 kHz (fb)

DAC current sum to be greater than or less than the input current. If the sum is less, the bit is left on; if more, the bit is
turned off. After testing all the bits, the SAR contains a 12-bit
binary code which accurately represents the input signal to
within 1/2 LSB.

GENERAL CIRCUIT OPERATION

The AD1674 is a complete 12-bit, 10 s sampling analog-todigital converter. A block diagram of the AD1674 is shown on
page 7.
When the control section is commanded to initiate a conversion
(as described later), it places the sample-and-hold amplifier
(SHA) in the hold mode, enables the clock, and resets the successive approximation register (SAR). Once a conversion cycle
has begun, it cannot be stopped or restarted and data is not
available from the output buffers. The SAR, timed by the internal clock, will sequence through the conversion cycle and return
an end-of-convert flag to the control section when the conversion has been completed. The control section will then disable
the clock, switch the SHA to sample mode, and delay the STS
LOW going edge to allow for acquisition to 12-bit accuracy.
The control section will allow data read functions by external
command anytime during the SHA acquisition interval.

CONTROL LOGIC
The AD1674 may be operated in one of two modes, the fullcontrol mode and the stand-alone mode. The full-control mode
utilizes all the AD1674 control signals and is useful in systems
that address decode multiple devices on a single data bus. The
stand-alone mode is useful in systems with dedicated input ports
available and thus not requiring full bus interface capability.
Table I is a truth table for the AD1674, and Figure 10 illustrates the internal logic circuitry.
Table I. AD1674A Truth Table

During the conversion cycle, the internal 12-bit, 1 mA full-scale

current output DAC is sequenced by the SAR from the most
significant bit (MSB) to the least significant bit (LSB) to provide an output that accurately balances the current through the
5 k resistor from the input signal voltage held by the SHA.
The SHAs input scaling resistors divide the input voltage by 2
for the 10 V input span and by 4 V for the 20 V input span,
maintaining a 1 mA full-scale output current through the 5 k
resistor for both ranges. The comparator determines whether
the addition of each successively weighted bit current causes the
REV. C

15

CE CS

R/C

12/8 A0 Operation

0
X

X
1

X
X

X
X

X
X

None
None

1
1

0
0

0
0

X
X

0
1

Initiate 12-Bit Conversion

Initiate 8-Bit Conversion

Enable 12-Bit Parallel Output

1
1

0
0

1
1

0
0

0
1

Enable 8 Most Significant Bits

Enable 4 LSBs +4 Trailing Zeroes

AD1674
VALUE OF A AT LAST
0
CONVERT COMMAND
D

Q
EN

Q
QB
EN

EOC 12
EOC 8

S
S

SAR RESET

R QB
1s DELAY-HOLD SETTLING

CE

CLK ENABLE
CS
STATUS
R/C
1s DELAY-ACQUISITION
HOLD/SAMPLE

A0
12/8

NYBBLE A
READ

NYBBLE B
NYBBLE C

TO OUTPUT
BUFFERS

NYBBLE B = 0

Figure 10. Equivalent Internal Logic Circuitry

FULL-CONTROL MODE
Chip Enable (CE), Chip Select (CS) and Read/ Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or CS may be used to initiate a conversion. The state of R/C
when CE and CS are both asserted determines whether a data
Read (R/C = 1) or a Convert (R/C = 0) is in progress. R/C
should be LOW before both CE and CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly
resulting in system bus contention.
STAND-ALONE MODE

The AD1674 can be used in a stand-alone mode, which is

useful in systems with dedicated input ports available and thus
not requiring full bus interface capability. Stand-alone mode
applications are generally able to issue conversion start commands more precisely than full-control mode. This improves ac
performance by reducing the amount of control-induced aperture jitter.
In stand-alone mode, the control interface for the AD1674 and
AD674A are identical. CE and 12/8 are wired HIGH, CS and
A0 are wired LOW, and conversion is controlled by R/C. The
three-state buffers are enabled when R/C is HIGH and a conversion starts when R/C goes LOW. This gives rise to two possible control signalsa high pulse or a low pulse. Operation
with a low pulse is shown in Figure 4a. In this case, the outputs
are forced into the high impedance state in response to the falling edge of R/C and return to valid logic levels after the conversion cycle is completed. The STS line goes HIGH 200 ns after
R/C goes LOW and returns low 1 s after data is valid.
If conversion is initiated by a high pulse as shown in Figure 4b,
the data lines are enabled during the time when R/C is HIGH.
The falling edge of R/C starts the next conversion and the data
lines return to three-state (and remain three-state) until the next
high pulse of R/C.
CONVERSION TIMING

Once a conversion is started, the STS line goes HIGH. Convert

start commands will be ignored until the conversion cycle is
complete. The output data buffers will be enabled a minimum
of 0.6 s prior to STS going LOW. The STS line will return
LOW at the end of the conversion cycle.

The register control inputs, A0 and 12/8, control conversion

length and data format. If a conversion is started with A0 LOW,
a full 12-bit conversion cycle is initiated. If A0 is HIGH during a
convert start, a shorter 8-bit conversion cycle results.
During data read operations, A0 determines whether the threestate buffers containing the 8 MSBs of the conversion result (A0
= 0) or the 4 LSBs (A0 = 1) are enabled. The 12/8 pin determines whether the output data is to be organized as two 8-bit
words (12/8 tied LOW) or a single 12-bit word (12/8 tied
HIGH). In the 8-bit mode, the byte addressed when A0 is high
contains the 4 LSBs from the conversion followed by four trailing zeroes. This organization allows the data lines to be overlapped for direct interface to 8-bit buses without the need for
external three-state buffers.
INPUT CONNECTIONS AND CALIBRATION

The 10 V p-p and 20 V p-p full-scale input ranges of the

AD1674 accept the majority of signal voltages without the need
for external voltage divider networks which could deteriorate the
accuracy of the ADC.
The AD1674 is factory trimmed to minimize offset, linearity,
and full-scale errors. In many applications, no calibration trimming will be required and the AD1674 will exhibit the accuracy
limits listed in the specification tables.
In some applications, offset and full-scale errors need to be
trimmed out completely. The following sections describe the
correct procedure for these various situations.
UNIPOLAR RANGE INPUTS

Figure 11 illustrates the external connections for the AD1674 in

unipolar-input mode. The first output-code transition (from
0000 0000 0000 to 0000 0000 0001) should nominally occur
for an input level of +1/2 LSB (1.22 mV above ground for a 10 V
range; 2.44 mV for a 20 V range). To trim unipolar offset to this
nominal value, apply a +1/2 LSB signal between Pin 13 and
ground (10 V range) or Pin 14 and ground (20 V range) and adjust R1 until the first transition is located. If the offset trim is
not required, Pin 12 can be connected directly to Pin 9; the two
resistors and trimmer for Pin 12 are then not needed.
10

REV. C

AD1674
R1
100k
+15V

15V

100k

R2
100

100

12/8

3
4

CS
A

5
6
10
8
12

R/C
CE
REF IN
REF OUT
BIP OFF

REFERENCE DECOUPLING

STS 28
HIGH BITS
24-27

It is recommended that a 10 F tantalum capacitor be connected between REF IN (Pin 10) and ground. This has the
effect of improving the S/(N+D) ratio through filtering possible
broad-band noise contributions from the voltage reference.

MIDDLE BITS
20-23
LOW BITS
16-19

BOARD LAYOUT

AD1674

0 TO +10V
ANALOG
INPUTS
0 TO +20V

13 10VIN
14 20VIN
9 ANA COM

+5V 1
+15V 7
15V 11
DIG COM 15

Figure 11. Unipolar Input Connections with Gain and

Offset Trims

The full-scale trim is done by applying a signal 1 1/2 LSB below

the nominal full scale (9.9963 V for a 10 V range) and adjusting
R2 until the last transition is located (1111 1111 1110 to 1111
1111 1111). If full-scale adjustment is not required, R2 should
be replaced with a fixed 50 1% metal film resistor. If REF
OUT is connected directly to REF IN, the additional full-scale
error will be approximately 1%.
BIPOLAR RANGE INPUTS

The connections for the bipolar-input mode are shown in Figure

12. Either or both of the trimming potentiometers can be
replaced with 50 1% fixed resistors if the specified AD1674
accuracy limits are sufficient for the application. If the pins are
shorted together, the additional offset and gain errors will be
approximately 1%.
To trim bipolar offset to its nominal value, apply a signal 1/2
LSB below midrange (1.22 mV for a 5 V range) and adjust
R1 until the major carry transition is located (0111 1111 1111
to 1000 0000 0000). To trim the full-scale error, apply a signal
1 1/2 LSB below full scale (+4.9963 V for a 5 V range) and
adjust R2 to give the last positive transition (1111 1111 1110 to
1111 1111 1111). These trims are interactive so several iterations may be necessary for convergence.

R2
100

5V
ANALOG
INPUTS
10V

R1
100

12/8
CS
A0
R/C
CE
REF IN
REF OUT
BIP OFF

IN

14 20VIN
9 ANA COM

Analog and digital signals should not share a common path.

Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Separate analog
and digital ground planes are also desirable, with a single interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them (if necessary) only at right angles.

SUPPLY DECOUPLING

The AD1674 power supplies should be well filtered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. A 10 F tantalum capacitor in parallel with a 0.1 F disc ceramic capacitor
provides adequate decoupling over a wide range of frequencies.

STS 28
HIGH BITS
24-27
MIDDLE BITS
20-23

An effort should be made to minimize the trace length between

the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD1674, associated analog input circuitry, and interconnections as far as possible from logic circuitry. A solid analog
ground plane around the AD1674 will isolate large switching
ground currents. For these reasons, the use of wire-wrap circuit
construction is not recommended; careful printed-circuit construction is preferred.

LOW BITS
16-19

AD1674
13 10V

The AD1674 has a wide bandwidth sampling front end. This

means that the AD1674 will see high frequency noise at the
input, which nonsampling (or limited-bandwidth sampling)
ADCs would ignore. Therefore, its important to make an effort
to eliminate such high frequency noise through decoupling or by
using an anti-aliasing filter at the analog input of the AD1674.

The AD1674 incorporates several features to help the users layout. Analog pins are adjacent to help isolate analog from digital
signals. Ground currents have been minimized by careful circuit
architecture. Current through AGND is 2.2 mA, with little
code-dependent variation. The current through DGND is dominated by the return current for DB11DB0.

A single-pass calibration can be done by substituting a negative

full-scale trim for the bipolar offset trim (error at midscale),
using the same circuit. First, apply a signal 1/2 LSB above minus
full scale (4.9988 V for a 5 V range) and adjust R1 until the
minus full-scale transition is located (0000 0000 0001 to 0000
0000 0000). Then perform the gain error trim as outlined above.
2
3
4
5
6
10
8
12

Designing with high resolution data converters requires careful

attention to board layout. Trace impedance is a significant issue.
At the 12-bit level, a 5 mA current through a 0.5 trace will
develop a voltage drop of 2.5 mV, which is 1 LSB for a 10 V
full-scale range. In addition to ground drops, inductive and capacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital signals. Finally, power supplies should be decoupled in order to
filter out ac noise.

+5V 1
+15V 7
15V 11
DIG COM 15

Figure 12. Bipolar Input Connections with Gain and Offset

Trims

REV. C

11

AD1674
GROUNDING

PACKAGE INFORMATION

If a single AD1674 is used with separate analog and digital

ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD1674. If multiple AD1674s are used or the AD1674 shares
analog supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This prevents large ground loops which inductively
couple noise and allow digital currents to flow through the analog system.

Dimensions shown in inches and (mm).

0.505 (12.83)
28

15
0.59 0.01
(14.98 0.254)

PIN 1
14

GENERAL MICROPROCESSOR INTERFACE

CONSIDERATIONS

0.050 0.010
(1.27 0.254)

1.42 (36.07)
1.40 (35.56)

A typical A/D converter interface routine involves several operations. First, a write to the ADC address initiates a conversion.
The processor must then wait for the conversion cycle to complete, since most ADCs take longer than one instruction cycle to
complete a conversion. Valid data can, of course, only be read
after the conversion is complete. The AD1674 provides an output signal (STS) which indicates when a conversion is in
progress. This signal can be polled by the processor by reading
it through an external three-state buffer (or other input port).
The STS signal can also be used to generate an interrupt upon
completion of a conversion, if the system timing requirements
are critical (bear in mind that the maximum conversion time of
the AD1674 is only 10 microseconds) and the processor has
other tasks to perform during the ADC conversion cycle. Another possible time-out method is to assume that the ADC will
take 10 microseconds to convert, and insert a sufficient number
of no-op instructions to ensure that 10 microseconds of processor time is consumed.

0.095
(2.41)

0.145 0.02
(3.68 0.51)
0.125
(3.17)
MIN

0.010 0.002
(0.254 0.05)

0.085
(2.16)
0.017 0.003
(0.43 0.076)

0.047 0.007
(1.19 0.178)

0.1 (2.54)

0.6 (15.24)

SEATING
PLANE

28-Lead Plastic DIP Package (N-28)

15

28

0.550 (13.97)
0.530 (13.462)

PIN 1
1

14
1.450 (38.83)
1.440 (35.576)

0.160 (4.06)
0.140 (3.56)

0.200
(5.080)
MAX

0.175 (4.45)
0.120 (3.05)

0.020 (0.508)
0.015 (0.381)

0.105 (2.67)
0.095 (2.41)

0.606 (15.39)
0.594 (15.09)

15
0

0.065 (1.65)
0.045 (1.14) SEATING
PLANE

0.012 (0.305)
0.008 (0.203)

28-Lead Wide-Body SO Package (R-28)

15

28

0.2992 (7.60)
0.2914 (7.40)
PIN 1
14

0.1043 (2.65)
0.0926 (2.35)

0.7125 (18.10)
0.6969 (17.70)

0.0118 (0.30)
0.0040 (0.10)

0.0500 (1.27)
BSC

0.4193 (10.65)
0.3937 (10.00)

0.0192 (0.49)
0.0138 (0.35)

0.0125 (0.32)
0.0091 (0.23)

0.0291 (0.74)
x 45
0.0098 (0.25)

8
0

0.0500 (1.27)
0.0157 (0.40)

AD1674 Data Format for 8-Bit Bus

12

REV. C

PRINTED IN U.S.A.

Once it is established that the conversion is finished, the data

can be read. In the case of an ADC of 8-bit resolution (or less),
a single data read operation is sufficient. In the case of converters with more data bits than are available on the bus, a choice of
data formats is required, and multiple read operations are
needed. The AD1674 includes internal logic to permit direct interface to 8-bit or 16-bit data buses, selected by the 12/8 input.
In 16-bit bus applications (12/8 HIGH) the data lines (DB11
through DB0) may be connected to either the 12 most significant or 12 least significant hits of the data bus. The remaining
four bits should be masked in software. The interface to an 8-bit
data bus (12/8 LOW) contains the 8 MSBs (DB11 through
DB4). The odd address (A0 HIGH) contains the 4 LSBs (DB3
through DB0) in the upper half of the byte, followed by four
trailing zeroes, thus eliminating bit masking instructions.

C1425b103/94

28-Pin Ceramic DIP Package (D-28)