Signal ow graph modelling of multi-state boost

DCDC converters
M. Veerachary
Abstract: A systematic procedure and guidelines for developing the unied ow graph model of a
multi-state boost DCDC converter is presented. From this unied model it is possible to
predetermine the complete behaviour of the converter system. The proposed method provides ease
of model formulation and avoids the mathematical complexity involved in obtaining the unied
model. Usefulness of the proposed method is demonstrated through an example of three state
boost converters. A simplied procedure is described that can be used to deduce large-signal, small-
signal and steady-state from the unied signal ow graph of the converter. Large-signal models
models have been developed and programmed in the TUTSIM simulator. Large-signal responses
against supply and load disturbances were obtained. Theoretical results, obtained from the
proposed signal ow graph method, are compared with PSIM power electronic simulator results.
Experimental results are provided to validate the proposed modelling method.
1 Introduction
The switch-mode DCDC converter has evolved into an
essential component for electronic equipment [1] and is
nding widespread applications in computers, battery
chargers, solar cell based power converters used in space
power conditioning systems etc. A wide variety of types of
converter topologies have been developed by different
researchers to cater for predened needs. These include
simple basic converters such as buckboost and buck-boost,
isolated converters, complex converters such as cascade,
interleaved converters etc. For front-end applications, boost
topology is a good choice. This boost topology has certain
advantages, such as simplicity of design, low switch stress
and high conversion efciency. However, the conventional
two-state boost converter control-to-output small-signal
transfer function has right-half plane (RHP) zero and it
introduces stability problems [2, 3]. A method to eliminate
the RHP zero is proposed for the simple boost converter, by
introducing an additional degree of control freedom in the
converter. This is done by providing an additional free-
wheeling mode for the inductor in addition to converter
boosting and capacitor charging modes. However, incor-
poration of an extra freewheeling mode for the inductor
requires additional switching elements, and modelling of the
system becomes a difcult task.
The state-space averaging method is the most popular
approach used for modelling of DCDC switching
converters [4]. However, this method is sometimes tedious,
especially when the converter circuit contains a large
number of elements. Furthermore, the linearised models
do not predict large-signal stability information, and are
only sufcient to predict small-signal stability. Large-signal
models are proposed, but these models do not provide a
generalised model, which can predict the complete beha-
viour of the circuit. To overcome some of the problems
described, a signal ow graph (SFG) non-linear modelling
method was developed for PWM converters [57]. The
benets that can be achieved from this method are: (i) it
converts the switching converter, two or multi-state, into a
unied dynamic model, (ii) from the unied model, it is
possible to derive large-signal, small-signal and steady-state
models with minimum effort, (iii) it is easier to arrive at
small-signal models with minimum mathematical manip-
ulations, (iv) it provides the designer with an easy way of
nding large-signal global behaviour when it is combined
with the use of TUTSIM/ SIMULINK simulator: (v) it is
possible to derive various relationships between the circuit
variables without any difculty: and (vi) it is also possible
to incorporate the cause and effect relationship of the
dynamics etc.
However, the SFG method has so far happen applied
only for simple two-state converters like buck, boost and
buckboost converters etc. Furthermore, there are no
prescribed guidelines to be followed while drawing the ow
graphs for DCDC converters. In this paper, general rules
to be followed while developing the signal ow graphs for
the DCDC converter are given and then the SFG method
is applied to the analysis of a three-signal state boost DC
DC converter system. Unied SFG models are developed
and then derivation of large-signal, small-signal and steady-
state models from the unied SFG models is demonstrated.
Simulation and experimental results are given to substanti-
ate the SFG modelling of the multi-state boost DCDC
converters.
2 General rules for drawing signal ow graphs of
DCDC converters
The following general rules must be observed while drawing
the signal ow graphs of DCDC converter systems:
(i) The sequence of nodes should be in the sequence of
elements, (inductors or capacitors), appearing in the circuit.
Improper sequence of nodes results in a graph in which the
The author is with the Department of Electrical Engineering, Indian Institute of
Technology Delhi, New Delhi 110 016, India
r IEE, 2004
IEE Proceedings online no. 20040680
doi:10.1049/ip-epa:20040680
Paper rst received 21st July 2003 and in revised form 30th April 2004.
Originally published online: 10th August 2004
IEE Proc.-Electr. Power Appl., Vol. 151, No. 5, September 2004 583
number of closed loops and forward paths different from
the true graph.
(ii) While drawing the SFGs, rst voltage node and then
current node should be indicated for inductive elements.
For capacitive elements, rst current node should be
indicated and then voltage node should follow.
(iii) Individual loops must be considered while writing down
the circuit loop voltage equations using Kirrchoffs voltage
low (KVL).
(iv) While using Kirrchoffs current low (KCL) at junction
points, shunt branch currents always must be expressed in
terms of other currents.
(v) The source current node is a sink node and receives
signals from all those inductors that have a common
terminal with the source.
(vi) The number of switching functions, (K
1
, K
2
, y, K
n
,
where n is the number of operating modes, in this case
n3), depends on the number of operating modes of the
circuit.
(vii) In the simplied SFG the closed loops are mainly
formed from the inductive and capacitive branch nodes.
The following Section uses the above rules to develop the
unied signal ow graph of the three-state boost converter
system.
3 Development of unied signal ow graph for
three state boost converter
This Section describes the SFG development of three-state
DCDC boost converter as shown in Fig. 1. This converter
has one additional mode of operation compared to the
conventional boost converter, which mainly improves the
dynamics of the converter system. Though the additional
operating mode, freewheeling of the input inductor,
eliminates the problem of the RHP zero, it requires an
additional switching element and increases complexity in
modelling. Particularly, considerable amount of mathema-
tical simplicationis needed in arriving the small-signal
models and controller design for the converter system. As
already shown in the introduction, when the converter
system contains a greater number of stages, then small-
signal transfer functions derivation becomes a complex task.
The proposed signal ow graph approach, given in this
paper, overcomes some of the problems existing in the
conventional methods. For demonstration of SFG model-
ling of multi-state converters, a three-state boost converter
system is considered and a general discussion to obtain the
unied model is given in the rst stage. In the second stage,
development of the remaining models, large-signal, small-
signal and steady-state, of the converter from the unied
SFG is discussed. The assumptions used in the analysis of
the system are: (i) switching elements of the converter
system are assumed to be ideal, (ii) the switches operate in a
predened sequence, (iii) the stray capacitances are
neglected, and (iv) passive components, R, L, and C, are
assumed tobe linear time-invariant.
In the general case for this converter system more
topologies are possible depending on the controlled
methodology employed, arising from the additional degree
of freedom introduced by the freewheeling of the inductor.
As an illustration, detailed analysis ispresented here for the
following steady-state switching cycle sequence 1: free-
wheeling of boost inductor, charging of boost inductor and
charging of output capacitor. However, developing the
unied SFGs for other switching schemes should be similar
to the one presented here.
For the continuous inductor current mode, the switching
sequence 1 described above results in three modes of
operation in one cycle time period and these are: mode 1,
mode 2 and mode 3, respectively. During the time 0otrt
1
(mode-1) the devices S
f
, D
f
; during t
1
otrt
2
(mode-2) the
devices S
f
, S
m
, and during t
2
otrT (mode-3) the device D
m
are conducting, and thus generating three different sub-
circuits. The converter switches between these three sub-
circuits, which are linear, and so a linear, system theory can
be used for them. Considering the mode 1 operation as
reference, signal ow graphs G
1
, G
2
, and G
3
are drawn for
the above three different sub-circuits sharing common
nodes and parts of the branches. These three signal ow
graphs are combined to form a simplied signal ow graph.
While merging the graphs (G
1
, G
2
and G
3
) into a single
graph G, some of the branches may exist in the three graphs
and some may not. Branches that exist in G
1
but not in G
2
,
G
3
are replaced by K
1
branches, and the branches that exist
in G
2
but not in G
1
, G
3
are replaced by K
2
branches and so
on. The resulting graph topology, can be mathematically
written as:
G
X
3
j1
K
j
G
j
1
where K
1
, K
2
and K
3
are the switching functions, whose
values depend on the switching times, dened by the
following expressions:
K
1

for 0ot t
1
for t
1
ot T

2
K
2

0 for 0ot t
1
1 for t
1
ot t
1
0 for t
2
ot t
1
8
<
:
3
K
3

0 for 0ot t
2
1 for t
2
ot T

4
Employing the above switching functions and individual
sub-circuit signal ow graphs, a unied signal ow graph is
generated, as shown in Fig. 2. This is a unied signal ow
graph of the three-state boost DCDC converter system,
from which complete behaviour, dynamic and steady-state,
of the system can be obtained. The same SFG is also valid
even if the converter is realised with an alternative switching
arrangement: S
f
in series with D
f
. On the same lines the
unied SFG for the steady-state switching cycle sequence 2
(charging of boost inductor, freewheeling of boost inductor
and charging of output capacitor) is developed and is
shown in Fig. 3. Systematic procedure is given in the
following Sections for developing the large-signal, small-
signal andsteady-state models from this unied signal ow
graph.
R C
i
g
V
g
i
0
V
0
i
L
r, L
D
f
D
m S
f
S
m
Fig. 1 Three-state boost converter
584 IEE Proc.-Electr. Power Appl., Vol. 151, No. 5, September 2004
3.1 Small-signal model
A small-signal SFG for the three-state boost converter
system can be obtained from the unied signal ow graph
(Fig. 2) by replacing the switching branches (K
1
, K
2
and K
3
)
with their corresponding small-signal equivalent models.
For illustration, we will derive the small-signal equivalent
for the switching branch K
1
. For this switching branch, the
input and output signals are related as
yt xtd
1
t 5
Let X, Y, D be the operating point, and ^xxt, ^ yyt,
^
dd
1
t the
corresponding small-signal perturbations that satisfy
xt X ^xxt, yt Y ^ yyt, and d
1
t D
1

^
dd
1
t.
Inserting these relationships into (5) results in the
following:
Y ^ yyt X ^xxtD
1
d
1
t
XD
1
D
1
^xxt Xd
1
t ^xxtd
1
t
6
Substituting the condition for the operating point, which is
YXD
1
, and on the assumption of neglecting second-order
perturbations, ^xxt
^
dd
1
t, the small-signal switching equa-
tion for the K
1
branch is
^ yyt D
f
^xxt Xd
1
t 7
Mathematical simplication for the K
2
and K
3
branches are
along similar lines to that used for K
1
, and the following
nal equations can easily be obtained:
^ yyt D
b
^xxt X
^
dd
2
t 8
^ yyt D
0
^xxt X
^
dd
1
t X
^
dd
2
t 9
where D
f
, D
b
and D
0
are the duty ratio control functions of
mode 1, mode 2 and mode 3, respectively. These three
duty ratio control functions satisfy the relationship
D
f
+D
b
+D
0
1. The above equations dene the graphical
representation of small-signal switching branches. On
substitution of the above small-signal switch branches in
Fig. 2, and on simplication, a small-signal SFG as shown
in Fig. 4 is generated. This small-signal model shown in
Fig. 4 can be used to derive all the small-signal performance
transfer functions between any two nodes for frequencies up
to about half of the switching frequency f
s
. However, the
derivation of the four most commonly used transfer
functions are given here for illustration. The sample
derivation of the input-to-output transfer function, also
called the audio susceptibility, is given along the following
lines. To start with, various possible forward paths and
loops are identied in the given small-signal SFG (Fig. 4).
There is only one forward path between the nodes ^vv
g
and ^vv
0
^vv
0
^vv
c
. Its transmittance formed by the nodes ^vv
g

^vv
L
i
L

^
ii
c
^vv
c
is:
p
1

RD
0
D
0
D
b

sL r1 sRC
10
In this small-signal ow graph only one loop formed by
nodes ^vv
L

^
ii
L

^
ii
c
^vv
c
^vv
L
exists, and its loop transmit-
tance is:
l
1

RD
2
0
1 sRCsL r
11
The gain between nodes ^vv
0
s and ^vv
g
s is obtained by
employing Masons gain formula [8] given by:
Gain
X
k
P
k
D
k
D
12
where P
k
is the kth forward path gain and D is the
determinant of the graph. Applying Masons gain formula,
the input-to-output transfer function is obtained as:
M
v
s
^vv
0
s
^vv
g
s

ds0
13
Substituting (10)(12) into the above equation and the
simplifying results in the following expression:
^vv
0
s
^vv
g
s

RD
0
D
0
D
b

Ls r1 sRC RD
2
0
14
where r and R are the series resistance of the inductor and
the load resistance respectively. The open-loop input
impedance is derived as:
Z
i
s
^vv
g
s
^
ii
g
s

ds0
15
^vv
g
s
^
ii
g
s

1 sRCsL r RD
2
0

1 sRCD
0
D
b

2
h i 16
The open-loop output impedance is:
Z
0
s
^vv
0
s
^
ii
0
s

ds0
17
^vv
0
s
^
ii
0
s

RsL r
1 sRCsL r RD
2
0
: 18
i
g
V
g
(D
0
+

D
b
)
(
D
0
+
D
b
)
V
g
i
0
D
0
D
0
d
b
V
0
i
L
1
(1+sRC )
R
(sL
1
+r
1
)
1

V
L

Fig. 4 Small-signal SFG of three-state boost converter

i
g
V
g i
0
D
0
D
0
D
0
D
0
D
b
D
b
V
L V
0
i
L
1
(1+sRC )
R
(sL
1
+r
1
)
1
Fig. 2 Unied SFG of three-state boost converter (for switching
sequence 1)
i
g
V
g
V
L
i
0
D
0
D
0
D
0
D
0
D
f
D
b
V
0
i
L
1
(1+sRC )
R
(sL
1
+r
1
)
1
Fig. 3 Unied SFG of three-state boost converter (for switching
sequence 2)
IEE Proc.-Electr. Power Appl., Vol. 151, No. 5, September 2004 585
The control-to-output transfer function is:
T
p
s
^vv
0
s
^
dds

v
g
s0
19
^vv
0
s
^
dds

RV
g
D
0
sL r1 sRC RD
2
0
20
On the assumption of negligible capacitor equivalent series
resistance the above small-signal transfer functions are
derived. However, the ESR of the main lter capacitor has
a signicant affect on the small-signal dynamics. Inclusion
of ESR will change the small-signal transfer functions and
can easily be determined from the SFG. The SFG of the
three-state boost converter including capacitor ESR is
identical to the one shown in Figs. 2 and 3, except that
the transmittance between the nodes i
0
and v
0
is
R1 sCR
c

1 sCR R
c

instead of
R
1sCR
, where R
c
is the
capacitor equivalent series resistance. Taking the above fact
into consideration, the small-signal transfer functions can be
derived and these are tabulated in Table 1 for ready
reference.
3.2 Large-signal and steady-state models
Assuming that the lter corner frequency is much smaller
than the switching frequency, the effective signals carried at
the outputs of K
1
, K
2
and K
3
branches having an average
values d
1
(t), d
2
(t) and d
3
(t), respectively, are:
yt xtd
j
t; where j 1; 2; 3 21
(21) indicates that the output signals, y(t), from the
switching branches K
1
, K
2
and K
3
are the product of the
input signal and the duty ratio control signal: d
1
(t), d
2
(t) or
d
3
(t). From these equations the large-signal models for
switching branches can be developed. Incorporating these
large-signal models for the switching branches into the
graph G, we then obtain the large-signal SFG, as shown in
Fig. 5. This large-signal model can be directly entered into
the TUTSIM simulator tostudy its large-signal behaviour.
The steady state switching branch models are derived
from the large-signal switching branch models. In the steady
state, the K
1
switching branch will have a transmittance of
d
1
(t) D
f
K
2
, the, K
2
switching branch will have a
transmittance of d
2
(t) D
b
and the K
3
switching branch
will have a transmittance of d
3
(t) D
0
, where D
f
, D
b
and D
0
are the duty ratio time intervals of the inductor free-
wheeling, inductor and capacitor charging modes, respec-
tively. Simplifying the large-signal owgraph with the
steady-state switching branch models described above,
and setting the complex frequency s-0, a steady state
model is obtained and is shown in Fig. 6. From this
switching ow graph, various steady state relationships
between the state variables are obtained and these are
shown in Table 2 for ready reference.
The above performance equations, small-signal transfer
functions and steady-state expressions tabulated in Tables 1
and 2, are derived from the SFG method. These expressions
are in agreement with those obtained from the use of the
state-space averaging method.
4 Results and discussion
To investigate the unied ow graph modelling of multi-
state boost converters, steady-state and dynamic perfor-
mance studies were made through computer simulations.
To verify the theoretical analysis and signal ow graph
+
+
+
+
+
+
i
g
V
g
i
0
D
0
D
0
D
0
D
b
D
b
V
0
i
L
1
(1+sRC )
R
(sL
1
+r
1
)
1
V
L
Fig. 5 Large-signal SFG of three-state boost converter
i
g
V
g
(D
0
+

D
b
)
(
D
0
+
D
b
)
i
0
D
0
D
0
V
0
i
L
1
R
r
1
1
V
L
Fig. 6 Steady-state SFG of three-state boost converter
Table 1: Small-signal transfer functions of three-state boost
converter including capacitor ESR
^ vv
0
s
^ vv
g
s
RD
0
D
0
D
b
1 sCR
c

sL r1 sCR R
c
RD
2
0
1 sCR
c

^ vv
0
s
^
ii
0
s
R1 sCR
c
sL r
sL r1 sCR R
c
RD
2
0
1 sCR
c

^ vv
g
s
^
ii
g
s
sL r1 sCR R
c
RD
2
0
1 sCR
c

D
0
D
b

2
1 sCR R
c

^ vv
0
s
^
dd
b
s
RD
0
V
g
1 sCR
c

sL r1 sCR R
c
RD
2
0
1 sCR
c

Table 2: Steady-state performance expressions of converter
V
0
V
g
RD
0
D
0
D
b

r RD
2
0

I
g
V
g
D
0
D
b

2
r RD
2
0

I
0
V
g
D
0
D
0
D
b

r RD
2
0

V
0
I
0
R
r RD
2
0

586 IEE Proc.-Electr. Power Appl., Vol. 151, No. 5, September 2004
modelling equations developed in the preceding Sections,
the following design example of three-state boost converter
was considered. The converter parameters chosen for this
example are: L277 mH, r
1
0.079O, C1000 mF,
R
c
0.091O, and R15O. SFGs are very much compa-
tible with SIMULINK/TUTSIM software simulators and
the performance can be easily analysed. However, TUTSIM
was used in the work described in this paper to simulate the
converter performance from the signal ow graphs. For
verication of SFG analysis results, the commercially
available power electronic simulator PSIM was employed.
To illustrate the large-signal response analysis of the
three-state boost converter system the corresponding large-
signal SFG model developed from the unied SFG, shown
in Fig. 5, was programmed into the TUTSIM simulator.
Large-signal responses of the converter were obtained for
two cases: (i) load resistance is changed from 16 to 5O and
then back to 16O, (ii) supply voltage is changed from 7.38
to 12.82V and then back to 7.38V. For various values of
the duty ratios, the step responses of the load current and
voltage of the converter were obtained. For illustration, a
few sample results were presented here for the duty ratios
D
f
0.25, D
b
0.4, D
0
0.35, and they are shown in
Figs. 710. For the above duty ratio patterns, the three-state
boost converter load voltage, under ideal conditions
V
0
1
D
b
D
0
V
g
, is ideally almost twice the input voltage.
This fact can be seen from the SFG analysis results, as
shown in Figs. 7 and 8. In the ideal case, the load voltage, is
almost constant against load disturbance. But in practice
increase in load slightly decreases the load voltage as
evidenced by Fig. 7. To validate the results of the SFG
analysis, large-signal responses were also obtained through
PSIM simulation software and these results, given below,
closely match those obtained from the signal ow graph
analysis method.
A three-state boost converter model is developed in the
PSIM simulator environment using the parameter values
mentioned above. Large-signal responses for the converter
system were predicted for two cases: (i) load resistance is
changed from 16 to 5O and then back to 16O, (ii) supply
voltage is changed from 7.38 to 12.82V and then back to
7.38V. These results, obtained from PSIM simulator, are
shown in Figs. 9 and 10. Comparing the results shown in
Fig. 7 with Fig. 9 and those in Fig. 8 with Fig. 10, it can be
concluded that the results obtained in both cases closely
match with each other.
5.0
2.5
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
30.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
time, s
R =16 R =16 R =5
v
o
l
t
a
g
e
,

V

/

c
u
r
r
e
n
t
,

A
V
0
I
0
I
ind
Fig. 7 Large-signal response against load disturbance (SFG)
5.0
2.5
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
30.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
time, s
v
o
l
t
a
g
e
,

V
V
g
=7.38 V V
g
=12.82 V V
g
=7.38 V
V
0
I
0
c
u
r
r
e
n
t
,

A
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Fig. 8 Large-signal response against supply voltage disturbance
(SFG)
5.0
2.5
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
30.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
time, s
v
o
l
t
a
g
e
,

V

/

c
u
r
r
e
n
t
,

A
V
0
I
ind
I
0
R =16 R =16 R =5
Fig. 9 Large-signal response against load disturbance (PSIM)
5.0
2.5
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
27.5
30.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
time, s
v
o
l
t
a
g
e
,

V
c
u
r
r
e
n
t
,

A
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
0
I
0
V
g
=7.38 V V
g
=12.82 V V
g
=7.38 V
Fig. 10 Large-signal response against supply voltage disturbance
(PSIM)
IEE Proc.-Electr. Power Appl., Vol. 151, No. 5, September 2004 587
To verify the proposed modelling methodology, an
experimental three-state boost converter circuit with para-
meter values mentioned above has been built and measure-
ments were taken from the prototype. The semiconductor
devices used are an International Rectier IRF530 power
MOSFET and a IXYS DSE1 fast recovery diode. The
inductor is made of a toroidal core, TDK: HF70T, whose
dimensions are 100127mm. Capacitor and load values
were chosen accordingly, as in the simulation studies. The
switching device, MOSFET, is driven by an international
rectier IR2110 gate driver. IC 6N137 is used for isolation
purpose.
Steady-state performance of the converter was observed
for different duty ratios. For illustration, the steady-state
inductor voltage, load voltage and current waveforms for
one particular operating condition are shown in Fig. 11.
These experimental observations indicate that, for a given
input voltage of 12V, the converter is capable of developing
a load voltage of about 20V. This experimental value is less
than the computed value, V
0
25V. This discrepancy is
mainly due to the non-ideal characteristics of the switching
devices and circuit parasitic components. Large-signal
responses of the converter system against load and supply
disturbances were observed for different operating condi-
tions. However, a few experimental large-signal responses
are given here for verication of simulated results obtained
from the proposed modelling method. These results are
shown in Figs. 12 and 13. The results closely match those
obtained from the proposed modelling method. Slight
discrepancies between simulated and experimental results
are mainly due to: (i) the use of available switch models and
integration methods of the simulator, (ii) simplied
assumptions made in the analysis, and (iii) slight errors, if
any, in measuring instruments etc. In simulation, the input
supply voltage is stiff even if the load is increased. However,
in the experimental system, the sourcevoltage decreases
with increase in load. Because of this, the simulation
results are slightly higher than the experimental values
obtained. Furthermore, the analysis was made on the
assumption that all the switching devices are ideal, i.e. in
the modelling, non-idealities of the converter such as
forward voltage drops, on-state resistances of the switching
devices and other parasitic components are not taken into
account.
The above discussion shows that the results obtained
from signal ow graph modelling closely match the PSIM
simulator results and experimental observations. However,
slight differences in these results are attributed to the
Fig. 11
a Steady-state inductor voltage waveform
b Steady-state load voltage and current waveforms
1: voltage; 2: current
Fig. 12 .
a Inductor current response against load disturbance
b Load current response against load disturbance
c Load voltage response against load disturbance
588 IEE Proc.-Electr. Power Appl., Vol. 151, No. 5, September 2004
following factors: (i) in the signal ow graph modelling,
non-idealities of the converter elements, such as forward
voltage drops, on-state resistances of the switching devices
and other parasitics are not taken into account, (ii) use of
built-in device models and integration methods etc.
5 Conclusions
General rules for drawing the signal ow graph of three-
state boost converters and an analysis method have been
presented. Development of unied signal ow graph is
discussed. Large-signal, small-signal and steady-state
models for the three-state boost converters lead to simple
graphical circuits that are very much suitable for analysis
and simulation. Analytical results, obtained from the
proposed modelling method, have been validated with
the PSIM simulator and experimental results. Further,
the performance expressions are in agreement with
those obtained from the use of state-space averaging
method, thus validating the proposed modelling
method.
6 References
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converters, Power Eng. J., 1998, 12, (5), pp. 229236
2 Viswanathan, K., Oruganti, R., and Srinivasan, D.: A novel tri-state
boost converter with fast dynamics, IEEE Trans. Power Electron.,
2002, 17, (5), pp. 677683
3 Himmelstoss, F.A., Kolar, J.W., and Zach, F.C.: Analysis of Smith-
predictor based control concept eliminating the right half plane zero of
continuous mode boost and buck-boost DCDC converters. Proc.
IEEE IECON., Kobe, Japan, 1991, Vol. 1, pp. 423438
4 Middlebrook, R.D., and Cuk, S.: A general unied approach to
modeling switching converter power stages. IEEE Power Electronics
Specialist Conference (PESC), Cleveland, Ohio, USA, 1976, Vol. 4,
pp. 1834
5 Smedley, K., and Cuk, S.: Switching ow-graph nonlinear
modeling technique, IEEE Trans. Circuits Syst. I, 1995, 42,
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6 Veerachary, M., Senjyu, T., and Uezato, K.: Signal ow graph
modeling and analysis of interleaved DCDC parallel converters, Int.
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7 Veerachary, M.: Modelling and control of interleaved boost converters
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8 Gopal, M.: Modren control systems theory (Wiley, New York,
1984)
Fig. 13 .
a Load current response against supply voltage disturbance
b Lod voltage response against supply voltage disturbance
IEE Proc.-Electr. Power Appl., Vol. 151, No. 5, September 2004 589