IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO.

1, JANUARY 2008 133

Analysis of Fourth-Order DCDC Converters:
A Flow Graph Approach
Mummadi Veerachary, Senior Member, IEEE
AbstractThe signal ow graph (SFG) nonlinear modeling
approach is well known for modeling dcdc converters and it
is a powerful analysis tool for higher order converter systems.
Modeling of several specic fourth-order dcdc converter circuits
have been reported using conventional state-space averaging. Par-
ticular emphasis has been given, so far, only to arrive at any
of the large, small-signal (SS) and steady-state models but not
a generalized one. This paper gives the generalized SFG model
of the fourth-order dcdc converter topology that is useful for
generating different types of fourth-order dcdc converter circuits
unied models. Further, it is shown that the deduction of large,
SS and steady-state models from these unied SFGs is easy and
straightforward. All possible fourth-order dcdc converter circuits
from its generalized topology have been identied and an analysis
of a few converter circuits is given here for illustration of the
proposed modeling method. Large-signal (LS) models are devel-
oped for different topology congurations and are programmed in
SIMULINK simulator. LS responses against supply and load dis-
turbances are obtained. Experimental observations are provided
to validate the proposed modeling method.
Index TermsFourth-order converters, large-signal (LS)
model, modeling, signal ow graph (SFG), small-signal (SS)
model.
I. INTRODUCTION
T
HE SWITCH-MODE dcdc converter has evolved into an
essential component in electronic equipment [1], [2] and
nding widespread application in computers, battery chargers,
solar cell-based power converters used in space power con-
ditioning systems, etc. The wide variety of converter topolo-
gies have been developed by different researchers to cater to
predened needs. These include simple basic converters such
as buck, boost and buckboost, isolated converters, complex
converters such as cascade, interleaved converters, etc. A sys-
tematic procedure and classication of pulsewidth-modulation
(PWM) dcdc converters is discussed in [3]. This paper identi-
es the basic fundamental converter cell and then derives var-
ious possible topologies. It is devoted mainly for two and four
switch topologies with two or three energy storage elements.
The exhaustive treatment given is useful for identifying the
nature of conversion, suitability for the given application, etc.
Among the various possibilities the two switch, two inductor
and one capacitor topologies are nding major application
in the area of switch-mode converters. These circuit congu-
rations belong to the fourth-order topologies. Application of
Manuscript received January 29, 2005; revised August 8, 2007.
The author is with the Department of Electrical Engineering, Indian Insti-
tute of Technology Delhi, New Delhi 110016, India (e-mail: mvchary@ee.
iitd.ernet.in).
Digital Object Identier 10.1109/TIE.2007.907677
fourth-order converter for power factor correction has been
reported [4], [5]. Although higher order increases complexity
in the dynamics, they have several desired features such as:
1) step-up/down conversion with continuous input and output
current. This is a desirable feature for high frequency converters
as this reduces the EMI ltering requirement; 2) since the
fourth-order topologies uses two inductors, it is possible to
apply the ripple steering phenomena [6], [7], thereby the con-
verter draws almost constant input current; 3) wide variety of
conversion ratios with single switch topology; and 4) simplicity
in the control, etc.
Modeling of a few individual fourth-order converter circuits
have been addressed in part by several authors. However, there
is a need to develop a generalized model of the fourth-order
topologies from which it should be possible to predetermine a
complete system behavior. State-space averaging method is the
most popular approach used for modeling of the dcdc switch-
ing converters [8]. However, this method is tedious, especially
when the converter circuit contains a large number of elements
[9]. Furthermore, the linearized models do not predict the large-
signal (LS) stability information, and are only sufcient to
predict small-signal (SS) stability [10][15]. LS models are
proposed, but these models do not provide a generalized model
that will predict the complete behavior of the circuit. To over-
come some of the problems previously mentioned, a signal ow
graph (SFG) nonlinear modeling method was developed for the
PWM converters [16][19]. The advantages of this method are:
1) it converts the switching converter, two or multistate, into a
unied dynamic model; 2) from the unied model, it is possible
to derive large, SS and steady-state models with minimum
mathematical manipulations; 3) it provides the designer an easy
way of getting LS global behavior when it is combined with the
TUTSIM and/or SIMULINK simulator; and 4) it is possible to
derive various relationships among the circuit variables without
any difculty, particularly it provides a simple method and
less mathematical manipulations in arriving at the SS transfer
functions of the switch-mode dcdc converter. However, the
SFG method so far applies only for specic converters like
buck, boost and buckboost converters, etc. Furthermore, there
are no prescribed guidelines while drawing the ow graphs for
the dcdc converters. This paper presents a generalized analysis
of fourth-order switch-mode dcdc converter topologies using
SFG theory.
II. GENERAL RULES FOR DRAWING SFGS
The SFG is a pictorial representation of ow of signals
through a network and is helpful in visualizing the operation of
0278-0046/$25.00 2008 IEEE
134 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
a network [21]. For any linear circuit, we can draw a different
number of SFGs depending on the choice of variables. How-
ever, the variables of choice should include the known quan-
tities and the desired quantities. The following are the general
rules useful for drawing the SFGs of the dcdc converter sys-
tem. 1) Formulate the linearly independent system of equations
for the given switch-mode converter so that this equation set
is consistent and completely denes the nature of the system.
2) The sequence of nodes is the sequence of elements, inductor
or capacitor, appearing in the circuit. Improper sequence of
nodes results in a graph in which the number of closed loops
and forward paths are different from the true graph. 3) Draw
the SFGs voltage node rst and then current node should
be indicated for inductive elements. For capacitive elements,
current node rst and then the voltage node should follow.
4) Individual loops must be considered while writing down
the circuit loop voltage equations using Kirchhoff voltage law.
5) Shunt branch currents must be expressed in terms of other
currents at junction points using the Kirchhoff current law.
6) The source current node is a sink node and receives signals
from all those inductors that have a common terminal with the
source. The path transmittance of 1 or switching function de-
pends on the boost or buck mode of operation of the converter.
7) The number of switching functions, (k
1
, k
2
, . . . , k
j
, where
j is no. of operating modes = 2, 3, . . . N), depends on the no.
of operating modes of the circuit. 8) In the simplied SFG,
the closed loops mainly form with the inductive and capacitive
branch nodes. The above general rules are valid for all the
dcdc converters including positive output and negative output
converters.
III. DEVELOPMENT OF UNIFIED SFG (USFG) MODEL
FOR THE FOURTH-ORDER CONVERTER
The switch-mode fourth-order converter mainly consists of
active, passive switch (diode), two inductors and a capacitor
in addition to load capacitance. The generalized representation
is shown in Fig. 1. Depending on the position of the above
elements, different fourth-order converter topologies can be
generated. Although many different circuit topologies can be
generated, by shifting the position of the circuit elements,
only a few of them are physically realizable and are useful
for the power conversion process. All possible topologies are
generated but only the topologies that are useful for switch-
mode conversion are discussed here. The number of physically
realizable converter circuits with: 1) element-1 as switch: 3;
2) element-2 as switch: 3; 3) element-3 as switch: 2; and
4) element-4 as switch: 1. The respective topologies in each
case correspondingly are: a) ZETA converter, buckboost con-
verter with LC output lter, buck converter with LC output
lter; b) SEPIC converter, CUK converter, boost converter with
LC output lter; c) buckboost converter with LC input lter,
buck converter with LC input lter; and d) boost converter with
LC input lter. This section describes the USFG development
of fourth-order converters. In general case many different types
of converter topologies, as discussed above, are possible and
the ow graph development to each and every topology is a
tedious task. A generalized SFG model, useful for analyzing all
Fig. 1. Block diagram of the generalized fourth-order converter topology.
the fourth-order converters, is developed to avoid unnecessary
mathematical work and complexity involved in the model de-
velopment of each and every converter circuit derived from the
general topology.
A. Generalized SFG of the Fourth-Order DCDC
Converter Topology
In this section, a generalized SFG method for the analysis
of the fourth-order dcdc converters operating in a continuous
current mode (CCM) is discussed. The analysis of the system
is carried out under the following assumptions: 1) switching
elements of the converter are assumed to be ideal; 2) the
equivalent series resistance of the capacitance C
1
and stray
capacitances are neglected; 3) passive components (R, L, C)
are assumed to be linear time-invariant; and 4) the two inductor
currents are assumed to be continuous.
To generate the USFG for the fourth order converter, rst we
assume, at random, that the element-1 is inductor-1, element-2
is switch, element-3 is diode, element-4 is capacitor, element-5
is inductor-2. This sequence generates a useful switch-mode
topology. Although the above element sequence results in the
boost converter with load LC-lter, the procedure given in
the following lines is a generalized one and is valid for all
possible element sequence in addition to the one given above.
With single switch topology, if the switch-mode converter is
operating in CCM of operation, it generates two linear circuits:
one for switch-on period and the other for switch-off period.
During the time 0 < t t
ON
, mode-1, the switch S; and during
t
ON
< t T, mode-2, the diodes D are, respectively, conduct-
ing and thus generating two different subcircuits. The converter
switches between these two subcircuits (which are linear) and
a linear system theory can be extended. Considering the switch
S operation as reference, SFGs G
ON
, G
OFF
are generated for
ON, OFF-state subcircuits, respectively, sharing common nodes
and part of the branches. A systematic algorithm, given in
Section II, is used while drawing the SFGs, G
ON
and G
OFF
.
The two SFGs G
ON
, G
OFF
are combined to form a simplied
SFG. While merging the two SFGs, G
ON
and G
OFF
, into a
single graph G, some of the branches exist in the two graphs
and some may not. Branches that exist in G
ON
but not in
G
OFF
are replaced by k
1
branches, and the branches that exist
in G
OFF
but not in G
ON
are replaced by k
2
branches. The
resulting graph topology can be mathematically written as G =
(k
1
G
ON
+ k
2
G
OFF
), where k
1
, k
2
are the switching functions
VEERACHARY: ANALYSIS OF FOURTH-ORDER DCDC CONVERTERS: A FLOW GRAPH APPROACH 135
satisfying the relationship k
1
+ k
2
= 1, whose values depend
on the switching times, dened by the following expressions:
k
1
=

1, for 0 < t t
ON
0, for t
ON
< t T
(1)
k
2
=

0, for 0 < t t
ON
1, for t
ON
< t T.
(2)
Employing the above switching functions and the two SFGs,
G
ON
and G
OFF
, a USFG is generated as shown in Fig. 2. Using
a similar procedure, one more unied graph is generated for
the switching sequence: element-1 is inductor-1, element-2 is
capacitor-1, element-3 is switch, element-4 is inductor-2, and
element-5 is diode. This sequence results into a buckboost
converter with LC input lter and the corresponding graph is
shown in Fig. 3. A similar procedure, not given here to avoid
repetitiveness, is adopted for other elements sequence to draw
the USFG of the corresponding topologies. Close observation
of all these different topologies ow graphs, generated from
Fig. 1, reveals a few important points that lead to the merging
of all graphs into a single generalized graph valid for a dif-
ferent element sequence of the fourth-order converters: 1) all
physically realizable dcdc converter circuits, generated from
fourth-order topology, will generate connected graphs having
identical nodes; 2) two nodes are required for representation of
any electrical element, active or passive, voltage and current
relationship. The total number of nodes in the unied graph
of the fourth-order topology is (2N + 2), where N is no. of
energy storage elements. In this case, there are four energy
storage elements and hence 8 nodes required for these ele-
ments, the remaining two nodes are required for the source;
3) connectivity of various nodes mainly decided by the ele-
ments position, element-1 to 5; and 4) the basic or primitive
graph for all physically realizable dcdc converter circuits,
obtained from the fourth-order topology, is the same but the
branches may have either constant transmittance or a switching
function. The nature of branch transmittance, constant trans-
mittance or a switching function is basically decided by the
position of elements-1 to 5.
Since the energy storage elements are not going to change,
the number of nodes in the generalized graph is xed. The
voltage, current nodes and branch transmittance connecting
these nodes dene each energy storage element. As a general
rule, assign the location and notation of the nodes according to
the sequence in which a particular element comes rst while
traversing from source to load. To ensure simplied layout,
the nal resulting graph should not have any overlapping or
crossover of branches. Once this location and notation is xed,
even if the element position is changed in the actual converter
circuit, the individual nodes position is not going to change. The
only change is that, the branches connecting different element
nodes will be different, which mainly depends on element
position. Employing the steps given above and in Section II a
generalized graph is drawn with xed as well as variable branch
transmittances. The xed transmittances are indicated in the
USFG, shown in Fig. 4, and the variable transmittances value
B
1
to B
12
depends on the position of elements in the fourth-
order topology. The parameter values for these branch transmit-
Fig. 2. USFG model of the fourth-order boost converter with output lter.
Fig. 3. USFGmodel of the fourth-order buckboost converter with input lter.
Fig. 4. Generalized SFG model of the fourth-order dcdc converter topology.
tances are 0, 1, k
1
, k
2
, where 0 branch transmittance
indicates that there will not be any connection between the
two nodes. Branch transmittance is k
1
when switch conducts,
branch transmittance is k
2
when diode conducts. The variable
transmittances, B
1
to B
8
, exists in all the converter circuits
derived from the fourth-order topology. The remaining trans-
mittances (B
9
, B
10
), (B
11
, B
12
) appears only in the specic
converter circuits ZETA and SEPIC, respectively. For ready
reference, the branch transmittances, B
1
to B
12
, are listed in
Table I. Using this table together with generalized SFG given
in Fig. 4, a USFG of any physically realizable dcdc converter
circuit derived from the fourth-order topology can easily be
drawn.
Justication for the Table I entries can easily be done from
the switch position in the fourth-order converter topology,
shown in Fig. 1. For example, for a buckboost converter with
input lter, the incoming branches of nodes v
2
, v
o
become
switching branches, B
4
= k
1
, B
6
= k
2
, due to the presence
of a switch and diode, respectively. Consider another topology,
3: A boost converter with input lter. In this topology, L
1
,
C
1
and L
2
forms a T-network on the supply side and this
is followed by the switch, diode, capacitor C
2
and load. The
load node points v
0
, i
0
receives signal from the inductor node
points v
2
, i
2
only when the diode is conducting. As already
mentioned in the preceding paragraph, when the diode conducts
136 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
TABLE I
VARIABLE BRANCH TRANSMITTANCES
then the switching function k
2
will be the connecting branch
transmittance. From the generalized graph, the branches con-
necting the node variables (i
2
i
0
), (v
2
v
0
), respectively,
are B
5
, B
6
. We can verify this from Table I, where k
2
is the
branch transmittance of B
5
, B
6
, which is in agreement with
our discussion above. Once the USFG of any specic fourth-
order converter is known, then developing large, SS and steady-
state models is a matter of replacing the switching branches
with their corresponding equivalent large, SS and steady-state
branches. A systematic procedure for developing the large, SS
and steady-state models from this USFG is illustrated in the
following sections.
B. LS and Steady-State Models
Assuming the lter corner frequency is much smaller [18],
[19] than the switching frequency, the effective signals carried
at the outputs of k
1
, k
2
switching branches having average
values d
1
(t), d
2
(t), respectively, are
y(t) = x(t)d
i
(t) (3)
where i = 1, 2. Equation (3) indicates that the output signal
y(t) from the switching branches k
1
, k
2
are the product of the
input signal and the duty ratio control signal d
1
(t) or d
2
(t).
From these equations the LS models for switching branches
are developed. Incorporating these LS models for the switching
branches in the graph G results in an LS SFG. This LS model
can be directly entered into any of the system level simulator
such as TUTSIM or SIMULINK to study its LS behavior. From
the LS switching branch models, the steady-state switching
branch models are derived. In the steady-state, k
1
branch
will have a transmittance of D
1
and k
2
branch will have
a transmittance of D
2
. Simplifying the LS ow graph with
the above steady-state switching branch models and setting
complex frequency s 0, a steady-state model is obtained.
From this SFG, various steady-state relations can easily be
derived.
C. SS Model
An SS SFG model for any of the fourth-order converter
system can be obtained from its USFG by simply replacing the
switching branches, k
1
and k
2
, with their corresponding SS
equivalent models. SS equivalents are derived for the switching
branches k
1
, k
2
in the following lines. For the switching
branch k the input and output signals are related as
y(t) = x(t)d
i
(t), i = 1, 2. (4)
Let X, Y , D be the operating points and x(t), y(t),

d
1
(t)
are the corresponding SS perturbations satisfying x(t) = X +
x(t), y(t) = Y + y(t), d
1
(t) = D
1
+

d
1
(t), d
2
(t) = D
2

d
2
(t). Inserting these relationships in (4) results in the follow-
ing equation:
Y + y(t) = (X + x(t))

D
1
+

d
1
(t)

(5)
Y + y(t) = (X + x(t))

D
2

d
2
(t)

. (6)
Substituting the condition for operating point, Y = XD
i
,
and on the assumption of neglecting second-order perturba-
tions, x(t)

d
1
(t), x(t)

d
2
(t), the SS switching equations for k
1
,
k
2
branches, respectively, are
y(t) =D
1
x(t) + X

d
1
(t) (7)
y(t) =D
2
x(t) X

d
2
(t) (8)
where D
1
, D
2
are the duty ratios control functions of switch-
on and switch-off modes, respectively. The above equations
dene the graphical representation of SS switching branches.
Upon substitution of the above SS switch branches in the USFG
and on simplication, an SS SFG can be generated. This SS
model, can be used to derive all the SS performance transfer
functions between any two nodes for frequencies up to about
half of the switching frequency (f
s
). This generalized treatment
is valid for all the fourth-order converter circuits generated
from Fig. 1. To deduce large, SS and steady-state models
from the USFG, some illustrative examples are considered in
the following sections. However, developing the SFGs for the
remaining converter circuits should be quite similar to the one
presented here.
IV. SS, LS AND STEADY-STATE MODELS OF
FOURTH-ORDER CONVERTER TOPOLOGIES
A. SS Models
SS transfer functions are essentially needed to study the SS
behavior and to design the controller. The easiness and simplic-
ity involved in the SFG method, while nding the SS transfer
functions, is demonstrated by considering some fourth-order
converters. As already mentioned in Section III, depending
on the switch position, the converter topologies are going to
change. For example, consider one topology for each switch
position of Fig. 1(b). Namely: 1) element-1: switch buck
boost converter with load output lter; 2) element-2: switch
SEPIC converter; 3) element-3: switch buck converter with
VEERACHARY: ANALYSIS OF FOURTH-ORDER DCDC CONVERTERS: A FLOW GRAPH APPROACH 137
Fig. 5. SS SFG model of the fourth-order SEPIC converter.
Fig. 6. SS SFG model of the boost converter with input lter.
input lter; and 4) element-4: switch boost converter with
input lter.
For the above converters, by substituting the branch trans-
mittances (given in Table I) in the generalized fourth-order
converter graph (given in Fig. 4), USFGs are deduced. Upon
substitution of the SS switching branches dened by (7) and
(8) in the USFGs, an extra branch with node

d is going to
be introduced. Combining all such nodes to one single node re-
quires moving all the

d branches to one common place. While

moving these branches in the signal ow direction, the branch
transmittance is going to multiply with that path transmittance.
On the other hand, if the movement of the branch is opposite
to the signal ow direction, then the branch transmittance is
going to divide by the corresponding path transmittance. Taking
these points into consideration, a simplication is made and the
nal SS SFGs of the above converters are generated. Because
of the limitation on the number of gures here, SS SFG models
are shown (Figs. 5 and 6) only for the SEPIC and boost
converter with output lter. Derivation of SS transfer functions
is given below for the SEPIC converter. Due to the limitation
on the number of pages, detailed derivation of transfer func-
tions for other converters is not given here. However, for the
remaining converters, the nal transfer functions are tabulated
for ready reference and these can easily be obtained with
simple mathematical manipulations as is used for the SEPIC
converter.
To demonstrate the suitability and simplicity of the proposed
SFG method, the following four commonly used transfer func-
tions detailed derivation is given below. In a given graph to
nd the gain, using Masons gain expression between any two
nodes requires identifying the forward paths and loops. Any
discrepancy in identifying the forward paths, individual and
nontouching loops will ultimately lead to improper determi-
nant of the graph . In the SEPIC converter SFG (Fig. 5),
two forward paths ( v
g
v
1

i
1

i
C
1
v
C
1
v
2

i
2

i
0
v
0
),
( v
g
v
1

i
1

i
0
v
0
), exists between v
g
, v
0
, and their path
transmittances, respectively, are
p
1
=
td
1
d
2
2
C
1
s(sL
1
+ r
1
)(sL
2
+ r
2
)
; p
2
=
td
2
(sL
1
+ r
1
)
where t = R(1 + sr
c
C
2
)/[1 + sC
2
(R + r
c
)]. Six loops
formed by nodes ( v
1

i
1

i
C
1
v
C
1
v
1
), ( v
2

i
2

i
0

v
0
v
2
), ( v
1

i
1

i
C
1
v
C
1
v
2

i
2

i
0
v
0
v
1
),
(

i
C
1
v
C
1
v
2

i
2

i
C
1
), ( v
1

i
1

i
0
v
0
v
1
),
( v
1

i
1

i
0
v
0
v
2

i
2

i
C
1
v
C
1
v
1
) exists and
their loop transmittances are given in the following:
l
1
=
d
2
2
C
1
s(sL
1
+ r
1
)
l
2
=
td
2
2
(sL
1
+ r
1
)
l
4
=
d
2
1
C
1
s(sL
2
+ r
2
)
l
3
=l
6
=
td
1
d
3
2
C
1
s(sL
1
+ r
1
)(sL
2
+ r
2
)
l
5
=
td
2
2
(sL
1
+ r
1
)
.
In this SS ow graph, two nontouching loop pairs exist,
which are (l
1
, l
2
), (l
4
, l
5
). The determinant of the graph is
= 1
6

j=1
l
j
+ (l
1
l
2
+ l
4
l
5
). (9)
Applying Masons gain formula [16], the input-to-output (also
called audio susceptibility), which describes the input-to-output
noise transmission is
M
v
(s) =
v
0
(s)
v
g
(s)

d(s)=0
=
p
j

(10)
v
0
(s)
v
g
(s)
=
te
1
d
2

d
1
d
2
+ C
1
e
2
s + d
2
1

[e
1
e
t
+ te
2
d
4
2
]
(11)
where
1
= 1,
2
= (1 l
4
), e = e
1
e
2
e
3
, e
1
= (sL
1
+ r
1
),
e
2
= (sL
2
+ r
2
), e
3
= sC
1
, e
t
= [e + e
2
d
2
2
+ 2te
2
d
2
2
C
1
s +
2td
1
d
3
2
+ e
1
d
2
1
+ td
2
1
d
2
2
]. Adopting a similar procedure, various
other transfer functions can be obtained. The open-loop input
impedance obtained as
Z
i
(s) =
v
g
(s)

i
g
(s)

d(s)=0
=

e
1
e
t
+ te
2
d
4
2

e
1
[e + te
2
e
3
d
2
2
+ e
1
d
2
1
]
. (12)
The open-loop output impedance is
Z
0
(s) =
v
0
(s)

i
0
(s)

d(s)=0
=
e
1

e + e
1
d
2
1
+ e
2
d
2
2

[e
1
e
t
+ te
2
d
4
2
]
. (13)
138 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
TABLE II
SS TRANSFER FUNCTIONS OF THE BUCK
CONVERTER WITH INPUT FILTER
TABLE III
SS TRANSFER FUNCTIONS OF THE BOOST
CONVERTER WITH INPUT FILTER
TABLE IV
SS TRANSFER FUNCTIONS OF THE BUCKBOOST
CONVERTER WITH OUTPUT FILTER
The control-to-output transfer function is
T
p
(s) =
v
0
(s)

d(s)

v
g
(s)=0
=
a
k
e
1

e + e
1
d
2
1
+ e
2
d
2
2

[e
1
e
t
+ te
2
d
4
2
]
(14)
where a
k
= a
k
= d
2
(V
0
+ V
C
1
)/e
2
[1 + (d
1
d
2
/e
1
e
3
)] (I
1
+
I
2
)[1 + (d
1
d
2
/e
2
e
3
)]. Adopting the same procedure given
above, we can easily obtain at the SS transfer functions of
the remaining fourth-order converter topologies and the nal
transfer functions are tabulated in Tables IIIV.
B. LS and Steady-State Models
Adopting the procedure outlined in Section III, the LS SFG
models can easily be obtained. These are identical to USFGs
except that the switching functions are replaced by the corre-
TABLE V
STEADY-STATE EXPRESSIONS OF THE FOURTH-ORDER CONVERTERS
sponding duty ratios. Accordingly, the LS models of fourth-
order converter topologies can be obtained easily from the
USFG (Fig. 4) by substituting the branch transmittances given
in Table I. For the steady-state models, the switching function
k in Table I should read as D.
These models can be directly entered into any of the system
level simulator to study its LS behavior. The detailed simulation
studies have been carried out using the LS SFG models devel-
oped above and these are given in the results and discussion
section. From the LS switching branch models, the steady-
state switching branch models are derived. In the steady-state,
k
1
branch will have a transmittance of D
1
and k
2
branch
will have a transmittance of D
2
. Simplifying the LS ow
graphs with the above steady-state switching branch models
and setting complex frequency s 0, steady-state models are
obtained. Adapting a similar procedure, using Masons gain
formula as outlined in Section IV-A, various relationships
among the state variables are obtained and they are given in
Table V for ready reference. The performance characteristics
tabulated in Tables IIV are derived from the SFG method
and are in agreement with those obtained from state-space
averaging method. Although the method demonstrated here for
CCM operation, it can easily be extended to DCM operation by
simply introducing mode-3 operation in the analysis.
V. RESULTS AND DISCUSSION
Comprehensive simulation studies were made to investigate
the SFG modeling of fourth-order converter topologies. To ver-
ify the generalized SFG of fourth-order topologies and the SFG
models developed from it for different fourth-order converters,
several simulations have been carried out on the LS SFGs.
However, for illustration, some results are given here for: 1)
buckboost converter with output lter; 2) SEPIC converter; 3)
buck converter with input lter; and 4) boost converter with
input lter. The parameters chosen for these converters are
given in Table VI.
To illustrate the LS response analysis of the aforementioned
converter systems, the LS SFG models developed from their
corresponding USFGs are programmed in the SIMULINK sim-
ulator. Several simulations were obtained, but for illustration,
some important results at a duty ratio of D = 0.5 are given
here for two cases: 1) load disturbance; and 2) supply voltage
disturbance. However, due to the limitation on the number
of gures, the simulation and experimental load disturbance
results are given for buckboost converter with output lter and
VEERACHARY: ANALYSIS OF FOURTH-ORDER DCDC CONVERTERS: A FLOW GRAPH APPROACH 139
TABLE VI
CONVERTER PARAMETERS
Fig. 7. Dynamic response of the buckboost converter with output
lter (SFG).
Fig. 8. Dynamic response of the SEPIC converter (SFG).
source voltage disturbance results for the remaining converters.
In the ideal case, the load voltage is almost constant against
load disturbance. But in practice, the increase in load slightly
decreases the load voltage on account of increased voltage drop
in the converter switching devices and parasitic elements. This
phenomenon is observed in all the converters. Converter load
voltage depends on the duty ratio and input supply voltage.
For a given duty ratio the converter load voltage is going to
change whenever there is any change in the supply voltage,
but it undergoes dynamics before it settles to the new steady-
state value. This is veried for all the converters by taking
the corresponding LS models and the results are plotted in
Figs. 710. To validate the SFG analysis results, experimental
LS responses were also obtained and these results, given in
Fig. 9. Dynamic response of the buck converter with input lter (SFG).
Fig. 10. Dynamic response of the boost converter with input lter (SFG).
the next paragraph, closely match with those obtained from the
SFG analysis method.
To verify the proposed modeling method, experimental pro-
totype fourth-order converter topologies with parameter values
given above have been built and measurements were taken from
the prototypes. The semiconductor devices used are MOSFET:
IRF530, Diode: MUR820. Inductor, capacitor and load values
are chosen accordingly as in simulation studies. An Interna-
tional Rectier IR2110 gate driver drives the MOSFET switch-
ing device. The converters dynamic responses against: 1) load
disturbance; and 2) supply voltage disturbances were measured
and they are given in Figs. 1114. Fig. 11 shows the buckboost
converter, Fig. 12 shows the SEPIC converter, Fig. 13 for
the buck converter and Fig. 14 is for the boost converter.
Comparing all these experimental LS response studies with the
corresponding simulated results, given in Figs. 710, it can be
noted that the developed models are able to predetermine the
converter behavior. However, in the simulation during the in-
termediate dynamics period, the response shows an oscillatory
nature, and reaches the nal steady-state values. This behavior
is mainly due to the variable step size used in the simulator
equation solver and also depends on the converter parameters.
As expected, in all converters, the measured load voltage is less
than the simulated value by 1 to 2 V. This is because of the
voltage drop in the converter parasitic components.
140 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008
Fig. 11. Dynamic response of the buckboost converter with output lter.
Fig. 12. Dynamic response of the SEPIC converter.
Experimental results are slightly different from the simulated
values. This difference is due to: 1) the difculty of accurate
representation of the nonidealities of the converter in the sim-
ulations; 2) use of built-in differential equation solvers and
variable step size limitations; 3) errors in the measuring instru-
ments, if any; and 4) in simulation, the step disturbance (source
or load) created is instantaneous while in the experimentation,
the step disturbances were created manually, which may not be
a sudden step as that created in the simulation prole. This is
one of the main reasons that reects the dynamic response of
the system.
VI. CONCLUSION
From the generalized fourth-order topology, all possible
physically realizable dcdc converter circuits were identied.
The general rules for drawing SFGs of dcdc converters
were formulated. A generalized SFG model was developed
for all the fourth-order dcdc converters generated from its
basic topology. Branch transmittances useful in the analysis
of different fourth-order converter circuits were tabulated. For
verication of the generalized model buckboost converter with
Fig. 13. Dynamic response of the buck converter with input lter.
Fig. 14. Dynamic response of the boost converter with input lter.
output lter, SEPIC converter, buck converter with input lter,
boost converter with input lter models are deduced from the
generalized SFG model and then small, LS and steady-state
performance expressions were determined. Models of fourth-
order dcdc converters lead to simple graphical circuits that
are very much suitable for analysis and simulation. Analytical
results, obtained fromthe proposed modeling method, were val-
idated with the experimental results. Further, the performance
expressions are in agreement to those obtained from the state-
space averaging method, thus validating the proposed modeling
method.
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Mummadi Veerachary (SM04) was born in
Survail, India, in 1968. He received the Bachelors
degree from the College of Engineering, Anantapur,
Jawaharlal Nehru Technological University (JNTU),
Hyderabad, India, in 1992, the Master of Technol-
ogy degree from the Regional Engineering College,
Warangal, India, in 1994, and the Dr. Eng. degree
from the University of the Ryukyus, Okinawa, Japan,
in 2002.
From 1994 to 1999, he was an Assistant Professor
in the Department of Electrical Engineering, College
of Engineering, Anatapur, JNTU. From October 1999 to March 2002, he was a
Research Scholar in the Department of Electrical and Electronics Engineering,
University of the Ryukyus. Since July 2002, he has been with the Department of
Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, India,
where he is currently an Associate Professor. His elds of interest are power
electronics and applications, modeling and simulation of large power electronic
systems, design of power supplies for spacecraft systems, control theory
application to power electronic systems, and intelligent controller applications
to power supplies.
Dr. Veerachary was the recipient of the IEEE Industrial Electronics Society
Travel Grant Award for the year 2001, Best Paper Award at the International
Conference on Electrical Engineering (ICEE-2000) held in Kitakyushu, Japan,
and Best Researcher Award for the year 2002 from the President of the
University of the Ryukyus. He is an editorial member of the Journal of Power
Electronics. He is a member of the IEEE Industrial Electronics Society and
the Institution of Engineers India. He is currently serving as an Associate
Editor of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS and IEEE
TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS. He is listed in
Whos Who in Science and Engineering 2003.