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(2)
where [A
j
]- state matrix, [B
j
]- input matrix, [E
j
]- output
matrix, and [x]- state vector, [y]- output vector, [u]- forcing
function vector.
1 1
1 3 3
1
2
1 2
/ 0 0 0
0 / 1/ 0
;
0 1/ 0 0
0 0 0 1/ ( ( ))
c
c
r L
r L L
A
C
C R r
=
+
2
3 3 3 3 3
2
1
2 2 2 2
[ ] / / 1/ / ( * )
/ [ ] / 0 / ( * )
;
1/ 0 0 0 0
/ ( ) / ( ) 0 1/ ( ( ))
e c
c c
c
a r L a L L a r L
a L a r L a r L
A
C
R C R R C R C R r
+
+
=
+
[ ]
2 1
1/ 0 0 0 ;
T
B L = [ ]
2
1/ 0 0 0
T
B L =
C3
1 2
C3 C3
Rr R
E =E = 0 0 0
(R+r ) (R+r )
The above matrices gives an idea of the system that they are
linear in each mode of operation, and the circuit behavior can
easily be obtained by the discrete-time state-model [4] given
by eqns. (3) and (4).
^ ^ ^
[ ] [ 1] [ 1] x n x n d n = + ; (3)
0 k
v = E x ; (4)
s d d 1 2 1
DT -t ) T A ( A A D Ts
=e e e ;
s d 2 1
DT -t ) A A ( D Ts
s
=KTe e
where
[ ]
T
L1 L3 c1 c0
x = i i v v ,
g
u=[V ]. Detailed discrete-
time formulations are reported in ref[4] are used and they are
listed here, eqns. (5)-(9), for ready reference.
-1
vg
G ( ) E (z- ) +F z =
(5)
-1
vd
G ( ) E (z- ) z = (6)
-1
( ) P [(ZI- ) ]
in
Z z = (7)
-1
( ) [E (zI- ) +J ]
o
Z z = (8)
3 2
3 2 1 o
vd
4 3 2
4 3 2 1 o
p z +p z +p z+a
G (z)=
[q z +q z +q +q z+q ] z
(9a)
Substituting the converter parameters, given in Section IV,
results in the following control-to-output transfer function.
3 2
vd
4 3 2
12.68z -31.85z +28.66z-8.982
G (z)=
[z -3.519z +4.833 -3.072z+0.76] z
(9b)
II. DIGITAL CONTROLLER DESIGN GUIDELINES
Fig. 2 shows the digitally controlled SI-SEPIC system,
where the loop gain is defined by ( ) ( ) ( )
v c vd
T z G z G z = . Here,
we need to design a robust digital voltage-mode controller,
G
c
(z), such that the load voltage must be constant irrespective
of the uncertainties in the converter parameters, disturbances
caused by input dc bus, or load fluctuations. The selection of
compensator is more important and its structure depends on
the order of the converter system. The converter under
consideration is fourth order and hence simple compensators,
like one-zero one-pole or one pole and two zeros, will not be
suitable as they will not provide sufficient gain margin (GM)
or phase margin (PM). Simple second order compensator is
the viable solution for this converter. Several other higher
order digital compensators can easily be designed for this
converter, but for the sake of simplicity the 2
nd
order
compensator with two pole two zero configuration is enough
in order to reveal the performance trade-offs. Although this
compensator is simple to implement, judicious selection of
pole-zero location is required to meet robustness performance
specifications. The SI-SEPIC has three zeros and four poles.
The main steps that are useful at the design stage are: (i)
better speed of response can be achieved through higher
bandwidths, but in reality the loopgain crossover frequency
lies somewhere in the range (f
s
/10 < f
c
< f
s
/5), (ii) the pole at
the origin needs to be placed so as to get a higher low
frequency gain, (iii) in the case where the converter transfer
function has RHP zeros, the maximum achievable bandwidth,
with a single-loop control strategy, is limited by the RHP zero
frequency and the pole-zero placement must be such that it
has the effect of reshaping the loopgain well below the
crossover frequency, and (iv) due to the presence of complex
conjugate pole/zero pairs, the loop gain shows up-down
glitches and if these are near the loopgain crossover
frequency, then the controller pole-zero locations must be
properly chosen so as to avoid multiple crossover points.
These are only a few important guidelines to the designer and
the final design trade-off depends on several factors, wherein
the designer has to use engineering judgment to ensure the
nominal as well as robust performance specifications are
achieved.
( ) ( ) ( ) ( ) ,
v c v d p
T z G z G z G z =
(10)
1 2
3
( )( )
( )
( 1)( )
v
cv
k z a z a
G z
z z a
=
(11)
Among the listed transfer functions the control-to-output
transfer function, G
vd
(z), is required while designing the outer
voltage-loop controller. After substituting the required
matrices in the mathematical identities the resulting transfer
function is given by (9). Once having this transfer function
the loop design can easily be carried out and the
corresponding steps explained above the compensator is
designed with the help of MATLAB [11] platform, wherein
almost all linear system theory related functions are readily
available. Check all the closed-loop converter performance
specifications, GM at least 6 dB and PM in between 40
0
~
75
0
, and if the design is not fulfilling the requirements repeat
the process by changing the crossover frequency,
locations of poles/zeros of the compensator.
III. ROBUSTNESS ANALYSIS THROUGH EDGE THEOREM
The presence of uncertain causes variations in the
coefficients of the system's characteristic polynomial. Thus,
the study of uncertain linear time-invariant systems and the
study of families of characteristic polynomials are bound
together. Moreover, if these polynomial families are taken as
sets of coefficient space, then the shape and orientation of
these sets reflect the structure of the uncertainty. Edge
Theorem first introduced by A.C. Bartlett, C.V. Hollot and
Huang Lin based on the above mentioned polynomial
families [8]. The theorem is computationally feasible test for
determining the roots of every member of a polynomial
family. Edge theorem overcomes the disadvantage of the
Kharitonov's Theorem. The polytope of polynomial family
formed, in this theorem will completely describes the case
when the polynomial's coefficients depend linearly on the
uncertainty range and when these parameters are confined to
a specific range. The root locations of the polytope of
polynomial determine the roots of every member of the
polynomial family and decide whether the system is stable
within that uncertain range or not.
Let P
1
(z), P
2
(z) are the polynomials corresponding to the
maximum and minimum uncertain uncertainties. According
to the Edge theorem, the polytope of polynomial is
1 2
( ) ( ) (1 ) ( ) P z P z P z = +
(4)
where, [0, 1]. By changing the value one can easily
generate roots locations against the given parameter
uncertainty.
IV. SIMULATION AND EXPERIMENTAL RESULTS
In order to demonstrate the proposed converter salient
features and its controlling capability a 12 to- 36 V, 25
Watt, split-inductor SEPIC converter has been considered
here, and its parameters are: L
1
=100 H, L
2
=100 H, L
3
=200
H, C
1
=50 F, C
0
=110 F, R= 50 , f
s
= 50 kHz. State-
space models derived in Section II have been used and the
control-to-output transfer function bode plot has been
generated as shown in Fig. 3. It is clear that this transfer
function has flat gain upto the corner frequency and then
dropping at -40 dB/dec in the high frequency region. In order
to stabilize this system a two pole two zero compensators is
now included in the closed-loop and the corresponding
loopgain frequency response plot is also shown in Fig. 3. The
digital controller parameters are: k=0.497, a=0.964, b=0.697,
c=0.867. This loopgain plot is exhibiting a GM= 12 dB,
PM=73
0
which are within the stable limits.
Although higher gain margin is recommended for
robustness point of view, but the corresponding increase in
phase margin gives oscillatory behavior for the dynamic
response, which is indirectly increases the settling time. To
test the controller robustness the roots of polytope
polynomial, generated using edge theorem, have been plotted
for the parameter variation (i) Vg: 15 20 V, (ii) R: 26
50 and the corresponding plots, showing the closed-loop
system pole-zero movement against parameter variation, are
shown in Fig. 4. This clearly indicates that although the
parameter variation is wider range (R: 26 to- 50 ; V
g
: 15
to- 20 V) but, still the designed digital controller maintains
the closed-loop system stability and hence this feature verifies
the robustness of the designed controller.
To validate the analysis and simulation results an
experimental prototype converter with closed controller
realized, controller is realized using ADMC401 DSP, has
been fabricated and then controller regulation capability is
tested for the following cases: (i) load disturbance from 52
26 , (ii) supply voltage change from 15 12 V. The
measured results, Fig. 5, clearly indicate the controller
regulation capability. To test the robustness of the designed
controller the dynamic response of load voltage has been
recorded against gradual variation of the supply voltage V
g
:
15 to- 20 V as shown in Fig. 6. This observation clearly
indicates the robustness of the designed controller and is also
in agreement with the pole-zero plot observations.
Fig. 3. Frequency response bode plot of Gvd, controller and Loopgain
transfer functions.
-1 -0.5 0 0.5 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-1.5 -1 -0.5 0 0.5 1 1.5
x 10
-3
-1.5
-1
-0.5
0
0.5
1
1.5
x 10
-3
0.96 0.97 0.98 0.99 1 1.01 1.02
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
(a) R : 26 250
-80
-60
-40
-20
0
20
40
Magnitude (dB)
10
1
10
2
10
3
10
4
10
5
-720
-540
-360
-180
0
Phase (deg)
Bode Diagram
Frequency (Hz)
Loopgain
vod(z
Gc(z
(b) Vg: 20 15 V
Fig. 4. Trajectory of root of the polytope polynomials, P(z), against
parameter variation.
R: 52 26
Vg: 12 20 V
Fig. 5. Measured dynamic response of the load voltage.
Fig. 6. Controller robustness against gradual supply voltage variation.
IV. CONCLUSIONS
Robust digital voltage-mode controller has been designed
for SI-SEPIC converter and its performance was compared
with the conventional SEPIC converter. These comparisons
suggest that the proposed SI-SEPIC is capable of delivering
higher voltage gains without degrading the steady-state
performance for duty ratios greater than 0.5. Edge theorem
was successfully employed for robustness verification.
Analytical predictions of robustness indicating studies were
validated through experimental results.
References
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conversion ratios, IEEE Trans. Power Electron., 1988, Vol. 3, no. 4,
pp. 484488.
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converters, IEEE Trans. On Circuits and Systems, 2008, Vol. 55(2),
pp.687-696.
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