Digital Two-Loop Controller Design for Fourth

Order Split-Inductor Converter

Mummadi Veerachary
Dept. of Electrical Engineering, IIT Delhi, New Delhi, India
E-mail: mvchary@ee.iitd.ac.in


Abstract- In this paper a digital two-loop controller design
methodology is proposed for the fourth order split inductor
converter load voltage regulation. The salient features of the
split-inductor converter are compared with the conventional
SEPIC converter and then discrete-time mathematical models
are established. Digital two-loop controller, inner current-loop
and outer voltage-loop, is designed using direct digital design
approach. A two-pole two-zero compensator is adopted in the
outer voltage-loop, while one-pole and one zero is used in the
inner current-loop design. Compensator design is validated
through simulations and then experimental measurements. Load
voltage regulation characteristics are obtained against line and
load perturbations. A 25 watt 15 to 36 V prototype converter is
built and experimental investigations are carried out. The
measured results obtained from the prototype converter are in
close agreement with those obtained in the analysis.
I. INTRODUCTION
Application of high frequency switch-mode power
conversion is increasing in the low power compact electronic
circuits. As the power conversion system is becoming
miniaturized, increasing the power density is one of the
challenging issues for the power supply designers. One of the
main orientations in power electronics in the last decade has
been the development of switching-mode converters with
higher power density and low electromagnetic interference
(EMI). Light weight, small size and high power density are
also some of the key design parameters [1]-[3].

Switch-mode power supplies (SMPS) are becoming an
integral part of many electronic systems [1] and the dc-dc
converters are mainly used in these application areas.
Technological developments are is taking place in order to:
(i) improve converter performance, (ii) achieve better
reliability, and (iii) increasing the power density, etc. The
aspect of increasing the power density is mainly related to the
converter design and packaging. Performance improvement
of the dc-dc converter topologies is broadly classified into
two different categories, which are: (i) steady-state
performance, and (ii) dynamic performance. Among these
two, the converter system dynamic performance mainly
governed by the type of controller used. Conventional SEPIC
converter based topologies are well established for
applications requiring both bucking and boosting the up-
stream voltages. However, in the applications where the
voltage gain requirement is higher, not possible to realize
with single conventional converter, then there are two
alternate solutions, which are: (i) cascading the boost
converters, (ii) cascading the SEPIC converters. Although
these methods are capable of resulting higher transformation
ratios, but more number of components are required for their
realization and also results in lesser efficiency. Some times to
realize the predefined transformation ratio the converter
needs to be operated at the extreme duty ratios wherein the
device utilization is poor with increased thermal loading. In
order to alleviate some of these limitations coupled inductor
boost converters and quadratic topologies have been proposed
in the literature [1]-[4]. However, more device stress is the
major limitation of these topologies. By using the split-
inductor [2] concept it is possible to increase the voltage gain
of the conventional SEPIC converter, without increasing the
device stress, and one such fourth order split-inductor
converter (FSC) is discussed in this paper.

The dynamic performance of the converter is primarily
decided by the control strategy employed for a particular
topology. The two most commonly used control schemes in
dc-dc switching power converters are: (i) single loop voltage-
mode control, (ii) current-mode control. It is well known that
the single loop voltage-mode control is slow in its response
against supply disturbances [7]. On the other hand the two-
loop control strategy, inner current mode control together
with outer voltage loop, results in faster dynamic response.
However, selection of a particular control scheme is
essentially decided by the complexity and cost trade-offs
requirements imposed by the end-user. In any case selection
of the control strategy is also depends on the speed of
response and robustness requirement. Considering speed of
response as the requirement a two-loop digital controlling
scheme is designed in this paper for the FSC and detailed
design methodology is given in the following paragraphs.


2 2
, L r
3
3
,

L
r
1 1
,
c
C r
0
0
,

c
C
r
1 1
, L r

Fig. 1. Fourth-Order Split Inductor Converter circuit diagram.
IEEE PEDS 2011, Singapore, 5 - 8 December 2011
978-1-4577-0001-9/11/$26.00 2011 IEEE
1137
Fig. 2. Control block diagram of voltage-mode controlled FSC.

TABLE I. PERFORMANCE COMPARISON


SEPIC FSC
Voltage gain Low High
Efficiency Moderate Moderate
Transient response Moderate Low
Switching stresses
on elements
High Low

II. MODELING AND ANALYSIS OF THE FOURTH ORDER
SPLIT-INDUCTOR CONVERTER
The fourth order split-inductor converter is shown in Fig. 1.
This converter is derived from the conventional SEPIC
converter where-in the source side inductance is divided into
two halves and then arranged in a bridge form as shown in
Fig. 1. In comparison to the conventional SEPIC converter, as
it is indicated within the box, it consists of three additional
diodes (D
1
, D
2
and D
3
) and inductors (L
1
,

L
2
). Due to this
structural arrangement the circuit exhibits more important
features as compared to the conventional SEPIC converter,
which are: (i) the FSC is capable of giving higher load
voltage boosting at lower duty ratios, (ii) switch
voltage/current stress is almost same as conventional
converter, and (iii) inductance requirement is almost same as
the conventional converter. Steady-state performance
comparison of this converter with SEPIC converter is given
in Table I for ready reference.

This FSC can operate either in continuous or discontinuous
inductor current mode of operation. However, for a given
power rating and boosting factor requirement the source
current magnitude is high for most of the loading conditions
and correspondingly the current is continuous in all the three
inductors. In view of this, the FSC analysis as well as its
discrete-time model formulation is discussed here for the
continuous inductor current mode of operation. As stated
earlier the high voltage gain of this converter is mainly due to
the presence of the split inductors (L
1
, L
2
), while there is no
change in the load side ripple current as there is no structural
change in the circuit configuration. The split inductor
combination will draw the energy from the dc-voltage source
during switch-ON time period and then pumps into the load
for the remaining time period. In this process the split
inductors will be connected in series during the switch-OFF
period contributing to additional boosting as compared to
conventional SEPIC converter. The split inductor
combination resulting in an additional boosting at the expense
of increased source current ripple.

A. Converter parameter Design Equations
The steady-state analysis of the FSC is carried out in this
section and the analysis is developed here after including the
following simplifying assumptions: (i) switching devices are
ideal, i.e voltage drops in the switching devices are neglected
and the transition time is very small, (ii) ripple current/
voltage magnitude is very small, (iii) converter time constant
is very high as compared to the switching period, and (iv)
non-idealities of the energy storage elements are neglected.
By employing the KVL and KCL the steady-state
relationships among the various voltage and currents are
established. Assuming voltage drops across inductors L
1
, L
2

are same, various voltages across inductor elements L
1
, L
2

and L
3
during switch-ON/OFF periods respectively are:
Inductor ON-time OFF-Time
L
1
V
g
(V
g
- V
c
- V
o
)/2
L
2
V
g
(V
g
- V
c
- V
o
)/2
L
3
V
c
-V
o


Applying volt-sec balance to the inductor L
1
and L
3
the
following voltage gain [7] of the converter is obtained.
( )
( )
0
1
1 -
g
D D V
V D
+
=
(1)
Using the power balance, V
g
I
g
=V
0
I
0
, and time-domain
analysis the FSC design equations are established. The
minimum and maximum inductor current expressions can
easily be obtained by using the ripple quantities,
L1 g 1
i V DT L ; =
L2 g 2
i V DT L = and the capacitor
voltage ripple relationships are:
C1 L2 1
V I DT C , =
2
C0 g 2 0
V V (DT) (8L C ). = These
expressions together with current/ voltage ripple requirements
give the basis for the design of energy storage components
L
1
, L
2
, L
3
and C
1
, C
2
.

B. State-space Models For Continuous Inductor Current
Mode of Operation

Application of state-space modeling is widely used in the
switch-mode power conversion systems. Conventionally, the
discrete-time models are obtained through suitable
transformation applied to the state-space models. However,
accuracy of such discrete-time models mainly governed by
the type of transformation used and the switching frequency
employed. In ref[4] discrete-time modeling of digitally
controlled converters has been reported, where-in it has been
demonstrated that it is possible to include type of pulse width
modulation strategy as well as the sampling instant
information in the model itself. This methodology is used to
formulate the discrete-time model for the proposed FSC
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operating at trailing-edge OFF-time sampling [7]. In
continuous inductor current mode of operation the circuit has
two operating modes; Mode-1: S-ON (0<t<DT
s
); Mode-2: S-
OFF (DT
s
<t<T
s
). In each mode of operation the circuit is
linear, and its behavior can easily be described by the state-
space model [13] given by
[ ] [ ] [ ]
[ ] [ ]
( 1)
j j
j j
j
x A x B u
t t t
y E x
+
= +

< <
=

(2)
where [A
j
]- state matrix, [B
j
]- input matrix, [E
j
]- output
matrix, and [x]- state vector, [y]- output vector, [u]- forcing
function vector.
1 1
1 3 3
1
2
1 2
/ 0 0 0
0 / 1/ 0
;
0 1/ 0 0
0 0 0 1/ ( ( ))
c
c
r L
r L L
A
C
C R r




=


+



2
3 3 3 3 3
2
1
2 2 2 2
[ ] / / 1/ / ( * )
/ [ ] / 0 / ( * )
;
1/ 0 0 0 0
/ ( ) / ( ) 0 1/ ( ( ))
e c
c c
c
a r L a L L a r L
a L a r L a r L
A
C
R C R R C R C R r
+

+

=


+


[ ]
2 1
1/ 0 0 0 ;
T
B L = [ ]
2
1/ 0 0 0
T
B L =
C3
1 2
C3 C3
Rr R
E =E = 0 0 0
(R+r ) (R+r )




The above matrices gives an idea of the system that they are
linear in each mode of operation, and the circuit behavior can
easily be obtained by the discrete-time state- model [4] given
by eqns. (3) and (4).
^ ^ ^
[ ] [ 1] [ 1] x n x n d n = + ; (3)
0 k
v = E x ; (4)
s d d 1 2 1
DT -t ) T A ( A A D Ts
=e e e ;

s d 2 1
DT -t ) A A ( D Ts
s
=KT e e


where
[ ]
T
L1 L3 c1 c0
x = i i v v ,
g
u=[V ]. Detailed discrete-
time formulations are reported in ref[4] are used and they are
listed here, eqns. (5)-(9), for ready reference.

-1
vg
G ( ) E (z- ) +F z =

(5)
-1
vd
G ( ) E (z- ) z = (6)
-1
( ) P [(ZI- ) ]
in
Z z = (7)
-1
( ) [E (zI- ) +J ]
o
Z z = (8)
3 2
3 2 1 o
vd
4 3 2
4 3 2 1 o
p z +p z +p z+a
G (z)=
[q z +q z +q +q z+q ] z


(9a)

Substituting the converter parameters, given in Section IV,
results in the following control-to-output transfer function.
3 2
vd
4 3 2
12.68z -31.85z +28.66z-8.982
G (z)=
[z -3.519z +4.833 -3.072z+0.76] z


(9b)

3 2
id
4 3 2
6.632z -16.83z +15.64z-5.383
G (z)=
[z -3.519z +4.833 -3.072z+0.76] z


(9c)

TABLE II. FOURTH ORDER SPLIT-INDUCTOR CONVERTER PARAMETERS
Parameter Value
Vg 15 V 20%
Vo 36 V
R 26 50%
L1, r1 100 H, 0.08
L2, r2 100 H, 0.05
L3, r3 200 H, 0.07
C1, rc1 50 F, 0.14
C0, rc0 100 F, 0.22
fs 50 kHz

III. DIGITAL CONTROLLER DESIGN GUIDELINES
Once the power stage transfer functions are known, then
the digital controller can easily be designed to obtain the
desired closed-loop dynamical performance. Several
compensator design approaches [5]-[10] have been reported
in the literature for the analogue controllers. However, there
are two different approaches can be used while designing the
digital compensator, which are: (i) digital redesign approach,
(ii) digital direct design approach (DDDA). The detailed
discussion about these methods have been given in Ref[7].
The second method, DDDA, is used in this paper for digital
controller design. Pole-zero placement technique is used
while arriving at suitable digital compensator, and its brief
description for one such compensator, two-zero two-pole
structure, is given in the following steps: (i) to reduce
regulation error of the load voltage, the loop gain crossover
frequency, f
c
, should be as high as possible, (ii) set the loop
gain crossover frequency, f
c
be in the range of 1/20 ~ 1/50
of the switching frequency f
s
, (iii) select f
3
as multiples of
f
c
like (
3
2
c
f f =
), (iv) select the frequencies f
2

and
f
3
such that they are in geometric mean with respect to f
c

i.e.,
1 3 c
f f f =
, (v) place the two compensator zeroes
below the crossover frequency (f
1
< f
2
< fc), f
1
=f
2
/10, f
2
=f
c
/f
3
,
(vi) place the two compensator poles above the cross over
frequency (f
c
< f
3
< f
4
), f
4
=10f
3
. These design steps have been
taken into consideration while designing the digital
compensator. However, fine tuning of these locations is
needed depending on the nature of converter transfer
functions. The closed-loop block diagram is shown in Fig. 2.
Use of this approach allows the designer to incorporate the
inherent digital delays present in the actual system. By using
above steps the compensator design can be carried out with
the help of any software program. However, MATLAB [11]
platform is the good choice for compensator design as it is
having all the control related functions. Check all the closed-
loop converter performance specifications, and if the design
is not fulfilling the requirements repeat the process by
1139
changing the crossover frequency, location of pole-zeros and
controller gain. By embedding the closed-loop converter into
any of the power electronic simulators it is easy to verify the
time domain responses through simulations. The overall loop
gain of the closed loop system, including inner current-loop
and outer voltage loop, is in the form given in eqn. 10.
( )
i v
T z T T = +
(10)
( ) ( ) ( ) ( ) ,
( ) ( ) ( ) ( ) ,
i c i d p
v c v d p
T z G z G z G z
T z G z G z G z
=
=
(11)
1 2
3
1
( )( )
( )
( 1)( )
( )
( )
( 1)
v
cv
i
ci
k z a z a
G z
z z a
k z b
G z
z

=

(12)
Among all the above equations the control-to-output
transfer function, G
vd
(z), and control-to-inductor current,
G
id
(z), given by eqn. 9, is required while designing the outer
voltage-loop and inner current-loop controllers. After
substituting the required matrices in the mathematical
identities the resulting transfer function is given by (9). Once
having these transfer functions the individual loop design can
easily be carried out and the corresponding steps explained
above the compensator is designed with the help of
MATLAB [8] platform, wherein almost all linear system
theory related functions are readily available. Check all the
closed-loop converter performance specifications, gain
margin (GM) at least 6 dB and phase margin (PM) in between
30
0
~ 75
0
, and if the design is not fulfilling the requirements
repeat the process by changing the crossover frequency,
locations of poles/zeros.

IV. DISCUSSIONS ON THE SIMULATION AND
EXPERIMENTAL RESULTS
In order to demonstrate the proposed converter salient
features and its controlling capability a 25 W, 15 to- 36 V
FSC is considered here and its parameters are listed in Table
II. State-space models, derived in Section II, have been used
and then important small-signal frequency response
characteristics have been obtained, using MATLAB. For
illustration, the overall loop design frequency response bode
plot is shown in Fig. 3. In order to stabilize the two-loop
system, the overall loopgain should follow the T
v
in the low
frequency region and T
i
in the high frequency region. To
achieve this, a two pole two zero compensators in outer loop
and one pole-zero in the inner loop is now included and the
corresponding loopgain frequency response plot is also
shown in Fig. 3. The digital controllers, G
cv
(z) and G
ci
(z),
parameters are: k
v
=0.9123, a
1
=0.941, a
2
=0.704, a
3
=0.849,
k
i
=0.5623, b
1
=0.941. This overall loopgain plot is exhibiting
a GM= 6.11 dB, PM=61
0
which are within the acceptable
stability limits.

To test the designed controller performance several
simulations, using PSIM simulator [12], have been performed
and then found that load regulation together with faster
dynamic response achieved in each case. Detailed simulation
results will be given in the final paper. The steady-state
voltage gain of the FSC has been verified by varying the duty
ratio, and found that the gain is increasing with increased
duty ratios. In order to validate the mathematical analysis and
simulation results a 25 Watts laboratory prototype FSC is
built and tested for its steady-state and dynamic performance.

To validate the developed theoretical analysis and
simulation results, a laboratory prototype closed-loop
converter has been built and then tested for its load voltage
regulation feature against source and load perturbations. The
digital control algorithm has been implemented using a
AMDC401digital signal processor (DSP) [10]. The devices
used in the prototype converter circuits are: Switch IRF540,
Diode MUR860, Driver circuit IR2110, Opto-coupler 6N137.
The load voltage is sensed and is brought down into the range
(0~1 V), which is passed on to the onboard ADC of the DSP.
The digital controller, given by eqn. 12, has been transformed
into a discrete-time control law given by:
( ) 1.849 ( 1) 0.849 ( 2) 0.9123 ( )
1.5 ( 1) 0.6044 ( 2)
v v v v
v v
d n d n d n e n
e n e n
= +
+

( ) ( 1) 0.5623 ( ) 0.5297 ( 1)
i i i i
d n d n e n e n = +
where d(n), d(n-1) and d(n-2) are the new, one-cycle-before
and two-cycles-before duty ratios, respectively; while e(n),
e(n-1) and e(n-2) are the new, one-cycle-before and two-
cycles-before error signals, respectively.

For demonstration of the principle sample experimentally
measured load voltage dynamic response characteristics for
the following cases: (i) load disturbance from 52 26
(50% variation), (ii) supply voltage change from 15 19 V
(20% variation). These measured results, Fig. 5, clearly
indicate that the designed digital controllers are regulating the
load voltage to the reference value of 36 V and exhibiting
faster dynamics response against source and load
disturbances.
-50
0
50
100
M
a
g
n
i
t
u
d
e

(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
-270
-180
-90
0
90
P
h
a
s
e

(
d
e
g
)


Bode Diagram
Frequency (Hz)
Ti
Tv
T1

Fig. 3. Frequency response bode plot of Ti, Tv, overall loopgain T transfer
functions.
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(a) Load perturbation (R: 52 26 )



(b) Source perturbation (Vg: 15 19 V)
Fig. 4. Simulated dynamic response of the load voltage.


(a) Load resistance perturbation (R: 52 26 )

(b) Source voltage perturbation (Vg: 15 19 V)
Fig. 5. Measured dynamic response of the load voltage.

V. CONCLUSION
Digital two-loop controller was designed for fourth order
split inductor converter. The comparative study shown that
the proposed converter has resulted in better performance
over the conventional SEPIC converter. Digital two-loop
controller, with inner current-loop and outer voltage-loop has
resulted better dynamic response against the source and load
perturbations. Simulation and experimental were in close
agreement with each other and thus validating the controller
design.
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1141
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