6.

976
High Speed Communication Circuits and Systems
Lecture 1
Overview of Course
Michael Perrott
Massachusetts Institute of Technology
Copyright 2003 by Michael H. Perrott
M.H. Perrott MIT OCW
Wireless Systems
Direct conversion architecture
sin(w
o
t)
90
o
D/A
D/A
Digital
Processing
Block
Digital
Processing
Block
sin(w
o
t)
90
o
A/D
A/D
Transmit IC Receive IC
LNA
Power
Amp
Transmitter issues
- Meeting the spectral mask (LO phase noise & feedthrough,
quadrature accuracy), D/A accuracy, power amp linearity
Receiver Issues
- Meeting SNR (Noise figure, blocking performance, channel
selectivity, LO phase noise, A/D nonlinearity and noise),
selectivity (filtering), and emission requirements
M.H. Perrott MIT OCW
Future Goals
Low cost, low power, and small area solutions
- New architectures and circuits!
Increased spectral efficiency
- Example: GSM cellphones (GMSK) to 8-PSK (Edge)
Requires a linear power amplifier!
Increased data rates
- Example: 802.11b (11 Mb/s) to 802.11a (> 50 Mb/s)
GFSK modulation changes to OFDM modulation
Higher carrier frequencies
- 802.11b (2.5 GHz) to 802.11a (5 GHz) to ? (60 GHz)
New modulation formats
- GMSK, CDMA, OFDM, pulse position modulation
New application areas
M.H. Perrott MIT OCW
High Speed Data Links
A common architecture
DEMUX
Digital
Processing
Block
Receive IC
Amp
Clock
and Data
Recovery
Clock
Distribution
10 Gb/s
Data Link
MUX Driver
Digital
Processing
Block
Transmit IC
Clock Generation
Transmitter Issues
- Intersymbol interference (limited bandwidth of IC
amplifiers, packaging), clock jitter, power, area
Receiver Issue
- Intersymbol interference (same as above), jitter from
clock and data recovery, power, area
M.H. Perrott MIT OCW
Future Goals
Low cost, low power, small area solutions
- New architectures and circuits!
Increased data rates
- 40 Gb/s for optical (moving to 120 Gb/s!)
Electronics is a limitation (optical issues getting significant)
- > 5 Gb/s for backplane applications
The channel (i.e., the PC board trace) is the limitation
High frequency compensation/equalization
- Higher data rates, lower bit error rates (BER), improved
robustness in the face of varying conditions
- How do you do this at GHz speeds?
Multi-level modulation
- Better spectral efficiency (more bits in given bandwidth)
M.H. Perrott MIT OCW
This Class
Circuit AND system focus
- Knowing circuit design is not enough
- Knowing system theory is not enough
Circuit stuff
- RF issues: transmission lines and impedance transformers
- High speed design techniques
- Basic building blocks: amplifiers, mixers, VCOs, digital
components
- Nonidealities: noise and nonlinearity
System stuff
- Macromodeling and simulation
- Wireless and high speed data link principles
- System level blocks: PLLs, CDRs, transceivers
M.H. Perrott MIT OCW
The Goal Design at Circuit/System Level
1. Design architecture with analytical models
May require new circuits guess what they look like
2. Verify architectural ideas by simulating with ideal
macro-models of circuit blocks
Guess macro-models for new circuits
3. Add known non-idealities of circuit blocks
(nonlinearity, noise, offsets, etc.)
Go back to 1. if the architecture breaks!
4. Design circuit blocks and get better macro-models
Go back to 1. if you cant build the circuit!
Go back to 1. if the architecture breaks!
5. Verify as much of system as possible with SPICE
6. Layout, extract, verify
Do this soon for high speed systems - iteration likely!
M.H. Perrott MIT OCW
Key System Level Simulation Needs
You need a fast simulator
- To design new things well, you must be able to iterate
- The faster the simulation, the faster you can iterate
You need to be able to add non-idealities in a
controlled manner
- Fundamental issues with architectures need to be
separated from implementation issues
An architecture that is fundamentally flawed should be
quickly abandoned
You need flexibility
- Capable of implementing circuit blocks such as filters,
VCOs, etc.
- Capable of implementing algorithms
- Arbitrary level of detail
M.H. Perrott MIT OCW
A Custom C++ Simulator Will Be Used - CppSim
Blocks are implemented with C/C++ code
- High computation speed
- Complex block descriptions
Users enter designs in graphical form using Cadence
schematic capture
- System analysis and transistor level analysis in the
same CAD framework
Resulting signals are viewed in Matlab
- Powerful post-processing and viewing capability
Note: Hspice used for circuit level simulations
CppSim is on Athena and freely downloadable at
http://www-mtl.mit.edu/~perrott
A Quick Preview of Homeworks and Projects
M.H. Perrott MIT OCW
HW1 Transmission Lines and Transformers
High speed data link application:
V
out
C
1
R
L
L
1
Delay = x
Characteristic Impedance = R
o
Ideal Transmission Line
R
o
V
in
Two-Port Model
C
2
E
i1
E
r1
E
i2
E
r2
die
Adjoining pins
Connector
Controlled Impedance
PCB trace
package
On-Chip
Driving
Source
High Speed Trace (RF Connector to Chip Die)
M.H. Perrott MIT OCW
HW2 High Speed Amplifiers
M
4
M
1
M
2
M
3
I
bias
V
in+
R
1
V
in-
R
2
V
o+
V
o-
50
V
in
M
1
M
2
L
s
L
d
L
g
C
big
I
bias
= 1mA
M
3
V
out
C
L
=1pF
5 k
Z
in
x
Broadband
Narrowband
M.H. Perrott MIT OCW
HW3 Amplifier Noise and Nonlinearity
Amplifier circuit
Model
M
1
I
bias
V
out
10
0.18
2
0.18
M
2
R
L
V
in
C
big2
C
big1
R
T
50
V
in
50
50
Nonlinearity
V
out
V
out
= c
o
+ c
1
x + c
2
x
2
+ c
3
x
3
Noise
M.H. Perrott MIT OCW
HW4 Low Noise Amplifiers and Mixers
Narrowband LNA
Passive Mixer
V
in
C
L
R
L
/2 R
L
/2
R
S
/2 C
big
R
S
/2 C
big
LO
LO
LO
LO
V
out
V
out
0 V
0
V
dd
0
V
dd
50
V
in
M
1
M
2
L
s
L
g
C
big
I
bias
= 1mA
M
3
V
out
C
L
=1pF
5 k
Z
in
R
ps
R
pg
R
ps
C
big
L
d
R
pd
M.H. Perrott MIT OCW
HW5 Voltage Controlled Oscillators
Differential CMOS
Colpitts
V
bias
=1.2V
M
1
L
d
=4nH
V
out
C
1
=2pF
I
bias
=100 A
C
2
=8pF
R
d
=10k
M
1
M
2
M
3
V
out
C
tune
3 nH
100/0.18
50/0.18
M
4
100/0.18
50/0.18
V
out
V
in
1.8 V
0 V
M.H. Perrott MIT OCW
Project 1 - High Speed Frequency Dividers
High speed
latches/registers
High speed dual-modulus
divider
L
o
a
d
L
o
a
d
IN IN
OUT OUT

2
2/3
Core
Control
Qualifier
CON
IN OUT
2
A B
2/3
IN
A
B
OUT
CON
*
8 + CON Cycles
CON
*
CON
M.H. Perrott MIT OCW
HW6 Phase Locked Loop Design
Integer-N synthesizer
Phase noise simulation
PFD
Loop
Filter
ref(t) out(t)
Divider
T
T
e(t) vin(t)
div(t)
VCO
N[k] = N
nom
I
cp
out(t) = cos(2 (f
o
+K
v
vin())d)
vin out
t
s
1 + s/(2f
p
)
v
ph
2
S

out
(f)
f
offset
0
-20 dBc/Hz/dec
v
spur
= Asin(2f
s
t)
K
2
dBc
K
1
dBc/Hz
f
p
f
s
M.H. Perrott MIT OCW
Project 2 GMSK Transmitter for Wireless Apps
K
v
= 30 MHz/V
f
o
= 900 MHz
Gaussian
LPF
Data
Generator
Digital I/Q Generation
out(t)
T
T
t
T
d
t
T
Loop Filter
Reference
Frequency
vin(t)
PFD
N
RF Transmit
Spectrum
0
f
f
RF
Trans.
Noise
Power
Amp
K
ph
1 - z
-1
cos()
sin()
D/A
D/A

f
inst
90
o
I
Q
Peak-to-Peak
Frequency
Deviation
T
d
t
I
n
s
t
a
n
t
a
n
e
o
u
s
F
r
e
q
u
e
n
c
y
Data Eye
Limit
Amp
(100 MHz)
=
1
1 MHz
Includes
Zero-Order
Hold
I
cp
H(s)
M.H. Perrott MIT OCW
Project 2 Accompanying Receiver
0
f
f
f
RF
f
RF
Received
Spectrum
Receiver
Noise
f
Baseband
Spectrum
cos(2f
RF
t)
I
R
Q
R
N
R
Receiver
Noise
Modulation
Signal
Transmitter
Noise
S(I
R
+jQ
R
)
Trans.
Noise
LNA
Band
Select
Filter
Channel
Select
Filter
sin(2f
RF
t)
Basics of Digital Communication
M.H. Perrott MIT OCW
Example: A High Speed Backplane Data Link
Suppose we consider packaging issues at the receiver
side (ignore transmitter packaging now for simplicity)
V
out
Delay = 110 ps
Characteristic Impedance = 50
Ideal Transmission Line
100
V
in
Two-Port Model
E
i1
E
r1
E
i2
E
r2
die
Adjoining pins
Controlled Impedance
PCB trace
package
On-Chip
Driving
Source
55
0.5 pF
M
4
M
1
M
2
M
3
I
bias
V
in+
V
in-
V
o+
100 100
Receiver Transmitter
unintentional
mismatch
intentional
mismatch
0.5 pF
1 nH
M.H. Perrott MIT OCW
Modulation Format
Binary, Non-Return to Zero (NRZ), Pulse Amplitude
Modulation (PAM)
- Send either a zero or one in a given time interval T
d
- Time interval set by a low jitter clock
- Ideal signal from transmitter:
0 0.5 1 1.5 2 2.5
x 10
8
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
i
n
TIME
M.H. Perrott MIT OCW
Receiver Function
Two operations
- Recover clock and use it to sample data
- Evaluate data to be 0 or 1 based on a slicer
Slice
Level
Sampling
Instant
Recovered
Clock
Detector
Data
Clock
Recovery
Out
Data
Out
0 1 1 1 1 1 1 0 0 0 0 0 0
Recovered
Clock
M.H. Perrott MIT OCW
Issue: PC Board Trace is Not an Ideal Channel
Chip capacitance and inductance limits bandwidth
Transmission line effects cause reflections in the
presence of impedance mismatch
Example: transmit at 1 Gb/s across link in previous
slide (assume bondwire inductance is zero)
- Signal at receiver termination resistor
0 0.5 1 1.5 2 2.5
x 10
8
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
o
u
t
TIME
M.H. Perrott MIT OCW
Eye Diagram for 1 Gb/s Data Rate
Wrap signal back onto itself every 2*T
d
seconds
- Same as an oscilloscope would do
Allows immediate assessment of the quality of the
signal at the receiver (look at eye opening)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
9
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Time (seconds)
o
u
t
Eye Diagram
M.H. Perrott MIT OCW
Relationship of Eye to Sampling Time and Slice Level
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10
9
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Time (seconds)
o
u
t
Eye Diagram
Slice
Level
Sampling
Instant
Horizontal portion of eye indicates sensitivity to timing
jitter
Vertical portion of eye indicates sensitivity to additional
noise and ISI
M.H. Perrott MIT OCW
What Happens if We Increase the Data Rate?
Limited bandwidth and reflections cause intersymbol
interference (ISI)
Eye diagram at 10 Gb/s for same data link
0 1 2
x 10
10
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (seconds)
o
u
t
Eye Diagram
M.H. Perrott MIT OCW
What is the Impact of the Bondwire Inductance?
Rule of thumb: 1 nH/mm for bondwire
- Assume 1 nH
Impact of inductance here increases bandwidth
- less ISI occurs
0 1 2
x 10
10
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (seconds)
o
u
t
Eye Diagram
M.H. Perrott MIT OCW
How High of a Data Rate Can The Channel Support?
Raise it to 25 Gb/s
However, we havent considered other issues
- PC board trace attenuates severely at high frequencies
Bandwidth is < 5 GHz for 48 inch PC board trace (FR4)
0 2 4 6 8
x 10
11
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (seconds)
o
u
t
Eye Diagram
M.H. Perrott MIT OCW
Multi-Level Signaling
Increase spectral efficiency by sending more than one
bit during a symbol interval
- Example: 4-Level PAM at 12.5 Gb/s on same channel
Effective data rate: 25 Gb/s
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
x 10
10
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
Time (seconds)
o
u
t
Eye Diagram
M.H. Perrott MIT OCW
How Else Can We Reduce ISI?
Consider a system level view of the link
- Channel can be viewed as having an equivalent
frequency response
Assumes linearity and time-invariance (accurate for most
transmission line systems)
Transmitter
Driver
Receiver
Detector
Channel
Transmitter Receiver
M.H. Perrott MIT OCW
Equalization
Undo channel frequency response with an inverse
filter at the receiver
- Removes ISI!
- Can make it adaptive to learn channel
Transmitter
Driver
Receiver
Detector
Channel
Transmitter Receiver
Equalization
M.H. Perrott MIT OCW
The Catch
Equalization enhances noise
- Overall SNR may be reduced
Optimal approach is to make ISI and noise
degradation about equal
Transmitter
Driver
Receiver
Detector
Channel
Transmitter Receiver
Equalization
Noise
M.H. Perrott MIT OCW
Alternative Pre-emphasize at Transmitter
Put inverse filter at transmitter instead of receiver
- No enhancement of noise, but
- Need feedback from receiver to learn channel
- Requires higher dynamic range/power from transmitter
Transmitter
Driver
Receiver
Detector
Channel
Trransmitter Receiver
Noise
Compensation
(Pre-emphasis)
M.H. Perrott MIT OCW
Best Overall Performance
Combine compensation and equalization
- Starting to see this for high speed links
Transmitter
Driver
Receiver
Detector
Channel
Trransmitter Receiver
Equalization
Noise
Compensation
(Pre-emphasis)
M.H. Perrott MIT OCW
What are the Issues with Wireless Systems?
Noise
- Need to extract the radio signal with sufficient SNR
Selectivity (filtering, processing gain)
- Need to remove interferers (which are often much larger!)
Nonlinearity
- Degrades transmit spectral mask
- Degrades selectivity for receiver
Multi-path (channel response)
- Degrades signal nulls rather than ISI usually the issue
- Can actually be used to advantage!
We will look at BOTH broadband data links and
wireless systems in this class