Metrology

Metrology roadmap July 27 2011
METROLOGY
1 INTRODUCTION AND SCOPE 2
1.1 INTRODUCTION.............................................................................................................. 2
1.2 SCOPE.........................................................................................................................
1. IN!R"STRUCTURE NEEDS................................................................................................. #
2 DIFFICULT CHALLENGES 4
3 MICROSCOPY 4
4 LITHOGRAPHY METROLOGY 6
#.1 $INE ROU%&NESS........................................................................................................... '
#.2 ME"SUREMENT UNCERT"INT(........................................................................................... )
#. E*P$"N"TION O! UNCERT"INT( IN T"+$ES MET "ND MET#...............................................11
5 FRONT END PROCESSES METROLOGY 11
,.1 ST"RTIN% M"TERI"$S.................................................................................................... 12
,.2 SUR!"CE PREP"R"TION.................................................................................................. 12
,. T&ERM"$-T&IN !I$MS.................................................................................................... 12
,.# STR"INED SI PROCESSES............................................................................................... 1
,., !ER"M..................................................................................................................... 1
,.. DOPIN% TEC&NO$O%(................................................................................................... 1
6 3D INTERCONNECT METROLOGY14
..1 +ONDIN% O/ER$"(....................................................................................................... 1,
..2 +ONDED INTER!"CE /OID DETECTION...............................................................................1.
.. +ONDED INTER!"CE DE!ECT IDENTI!IC"TION......................................................................1.
..# +ONDED INTER!"CE DE!ECT RE/IE0................................................................................1.
.., ED%E +E/E$ DE!ECTS................................................................................................... 17
... +OND STREN%T& UNI!ORMIT(.........................................................................................17
..7 +ONDED 0"!ER P"IR T&IC1NESS....................................................................................17
..' TS/ ETC& DEPT&......................................................................................................... 1'
..) TS/ ETC& PRO!I$E....................................................................................................... 1'
..10 TS/ $INER2 +"RRIER2 SEED T&IC1NESS.............................................................................1'
..11 S&"PE "ND STRESS...................................................................................................... 1)
..12 D METRO$O%( !OR COPPER N"I$ "ND PI$$"RS................................................................1)
7 INTERCONNECT METROLOGY 20
7.1 CU3$O0 4 MET"$$I5"TION ISSUES "ND METRO$O%( NEEDS...................................20
7.1.1 Cu Metallization Issues........................................................................................ 20
7.1.2 Cu Metallization Metrology..................................................................................21
7.2 $O0 4 DIE$ECTRICS ISSUES "ND METRO$O%( NEEDS.........................................................22
7.2.1 Low Dielectric Issues......................................................................................... 22
7.2.2 Low- Metrology.................................................................................................. 22
8 MATERIALS AND CONTAMINATION CHARACTERIZATION 23
'.1 M"TERI"$S "ND CONT"MIN"TION IN STR"IN3+"SED DE/ICES..................................................2,
9 METROLOGY FOR EMERGING RESEARCH MATERIALS AND DEVICES 26
).1 D "TOMIC IM"%IN% "ND SPECTROSCOP(........................................................................2'
AERRATION CORRECTED TEM AND STEM !"ELS 28
3D ATOM PROE 28
).2 OT&ER MICROSCOP( NEEDS INC$UDIN% SC"NNIN% PRO+E MICROSCOP(.................................2)
). OPTIC"$ PROPERTIES O! N"NOM"TERI"$S.........................................................................0
).# E$ECTRIC"$ C&"R"CTERI5"TION !OR EMER%IN% M"TERI"$S "ND DE/ICES..............................1
Page 1 o6 #
10 REFERENCE MATERIALS 31
11 REFERENCE MEASUREMENT SYSTEM 33
1 Introduction and Scope
1.1 Introduction
Metrology is defined as the science of measurement. The ITRS Metrology Roadmap describes new challenges
facing metrology and describes a pathway for research and development of metrology with the goal of extending
CMOS and accelerating eyond CMOS. Metrology also provides the measurement capability necessary for cost!
effective manufacturing. "s such# the metrology chapter of the ITRS focuses on difficult measurement needs#
metrology tool development# and standards.
The roadmap for feature si$e reduction drives the timeline for metrology solutions for new materials# process# and
structures. Metrology methods must routinely measure near and at atomic scale dimensions which re%uire a
thorough understanding of nano!scale materials properties and of the physics involved in ma&ing the measurement.
'ovel materials and geometries# such as () gates and strained silicon channels# add to the complexity of
measurements. Metrology development must be done in the context of these issues. Metrology enables tool
improvement# ramping in pilot lines and factory start!ups# and improvement of yield in mature factories. Metrology
can reduce the cost of manufacturing and the time!to!mar&et for new products through better characteri$ation of
process tools and processes. The increasing diversity of chip types will spread already limited metrology resources
over a wider range of challenges. The metrology community including suppliers# chip manufacturers# consortia# and
research institutions must provide cooperative research# development# and prototyping in order to meet the ITRS
timeline.
The lac& of certainty in the structures and materials of future technology generations ma&es the definition of future
metrology needs less clear than in the past. *owever# it is clear that () device structures will be introduced by at
least some companies as early as the ++ nm node. Such () device structures invalidate many of the starting
assumptions for the modeling and analyses of conventional metrologies necessitating an increased emphasis on
metrology techni%ues which can provide true () information. The () nature of both front end and interconnect
devices and structures provides many challenges for all areas of metrology including critical dimensions. "lthough
advancements in materials characteri$ation methods# such as aberration corrected transmission electron microscopy#
have achieved atomic resolution for +) materials# including single layer graphene# critical dimension measurement
with nm level precision is difficult to achieve particularly for () structures. ,eature shape characteri$ation and
metrology done largely in +) will need to evolve to (). The +-.. ITRS expands on the new urgency for Metrology
for () Interconnects to include wafer alignment# interface bonding# and through silicon vias /TS01.
Moreover# it is entirely possible that different materials will be used by different manufacturers at a given
technology generation# potentially re%uiring different metrologies. In the near term# advances in electrical and
physical metrology for high! and low!2 dielectric films must continue. The strong interest in 340 5ithography is
driving the need for new mas& metrology. The re%uirement for technology for measurement of devices on ultra!thin
and possibly strained silicon on insulator comes from the best available information that is discussed in the Front
End Processes Roadmap. The increasing emphasis on active area measurements instead of test structures in scribe
/&erf1 lines places new demands on metrology. Measurement of relevant properties# such as stress or strain# in a
nano!si$ed# buried area such as the channel of a small dimension gate is a difficult tas&. Often# one must measure a
film or structure property at the surface and use modeling to determine the resultant property of a buried layer.
5ong!term needs at the sub!.6 nm technology generation are difficult to address due to the lac& of clarity of device
design and interconnect technology. The selection of a replacement for copper interconnect remains a research
challenge. "lthough materials characteri$ation and some existing inline metrology apply to new device and
interconnect structures# development of manufacturing capable metrology re%uires a more certain &nowledge of
materials# devices# and interconnect structures. The +-.. ITRS also includes the addition of a M3MS section/need
metrology71.
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Metrology tool development re%uires access to new materials and structures if it is to be successful. It re%uires state!
of!the!art capabilities to be made available for fabrication of necessary standards and development of metrology
methodologies in advance of production. The pace of feature si$e reduction and the introduction of new materials
and structures challenge existing measurement capability. In some instances# existing methods can be extended for
several technology generations. In other cases# necessary measurements may be done with inade%uate e%uipment.
5ong!term research into nano!devices may provide both new measurement methods and potential test vehicles for
metrology. " greater attention to expanding close ties between metrology development and process development is
needed. 8hen the metrology is well matched to the processes and process tools# ramping times for pilot lines and
factories are reduced. "n appropriate combination of well!engineered tools and appropriate metrology is necessary
to maximi$e productivity while maintaining acceptable cost of ownership.
The fundamental challenge for factory metrology will be the measurement and control of atomic dimensions while
maintaining profitable high volume manufacturing. In manufacturing# metrology is connected to factory!wide
automation that includes database and intelligent information from data capability. Off!line materials
characteri$ation is also evolving toward compatibility with factory!wide automation. "ll areas of measurement
technology /especially those covered in the Yield Enhancement chapter) are being combined with computer
integrated manufacturing /CIM1 and data management systems for information!based process control. "lthough
integrated metrology still needs a universal definition# it has become the term associated with the slow migration
from offline to inline and in situ measurements. The proper combination of offline# inline# and in situ measurements
will enable advanced process control and rapid yield learning.
The expected trend involves the combined use of modeling with measurement of features at the wafer surface. The
Metrology roadmap has repeated the call for a proactive research, development, and supplier base for many years .
The relationship between metrology and process technology development needs fundamental restructuring. In the
past the challenge has been to develop metrology ahead of target process technology. Today we face ma9or
uncertainty from unresolved choices of fundamentally new materials and radically different device designs.
Understanding the interaction between metrology data and information and optimum feedbac!, feed forward, and
realtime process control are !ey to restructuring the relationship between metrology and process technology" " new
section has been added to the Metrology Roadmap that covers metrology needs for emerging technology paradigms.
1.2 Scope
The metrology topics covered in the +-.. Metrology roadmap are microscopy: critical dimension /C)1 and overlay:
film thic&ness and profile: materials and contamination analysis: () metrology: emerging research materials and
devices: and reference materials. These topics are reported in the following sections in this chapter; Microscopy:
5ithography Metrology: ,ront 3nd <rocesses Metrology: () Interconnect Metrology: Traditional Interconnect
Metrology: Materials and Contamination Characteri$ation: Metrology for 3merging Research Materials )evices:
Reference Materials: and Reference Measurement Systems.
International cooperation in the development of new metrology technology and standards will be re%uired. oth
metrology and process research and development organi$ations must wor& together with the industry including both
the supplier and IC manufacturer. 3arlier cooperation between IC manufacturers and metrology suppliers will
provide technology roadmaps that maximi$e the effectiveness of measurement e%uipment. Research institutes
focusing on metrology# process# and standards: standards organi$ations: metrology tool suppliers: and the university
community should continue to cooperate on standardi$ation and improvement of methods and on production of
reference materials. )espite the existence of standardi$ed definitions and procedures for metrics# individuali$ed
implementation of metrics such as measurement precision to tolerance /<=T1 ratio is typical. . The <=T ratio is used to
evaluate automated measurement capability for use in statistical process control and relates the measurement
variation /precision1 of the metrology cluster to the product specification limits. )etermination of measurement tool
variations is sometimes carried out using reference materials that are not representative of the product or process of
interest. Thus# the measurement tool precision information may not reflect measurement!tool induced variations on
product wafers. It is also possible that the sensitivity of the instrument could be insufficient to detect small but
unacceptable process variations. There is a need for metrics that accurately describe the resolution capability of
metrology tools for use in statistical process control. The inverse of the measurement precision!to!process variability
is sometimes called the signal!to!noise ratio or the discrimination ratio. *owever# because the type of resolution
depends on the process# specific metrics may be re%uired /e.g. thic&ness and width re%uire spatial resolution while
levels of metallic contaminants on the surface re%uire atomic percent resolution1. There is a new need for a
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standardi$ed approach to determination of precision when the metrology tool provides discrete instead of continuous
data. This situation occurs# for example# when significant differences are smaller than the instrument resolution.
The principles of integrated metrology can be applied to stand!alone and sensor!based metrology itself. ,actors that
impact tool calibration and measurement precision such as small changes in ambient temperature and humidity
could be monitored and used to improve metrology tool performance and thus improve statistical process control.
8afer manufacturers# process tool suppliers# pilot lines# and factory start!ups all have different timing and
measurement re%uirements. The need for a shorter ramp!up time for pilot lines means that characteri$ation of tools
and processes prior to pilot line startup must improve. *owever# as the process matures# the need for metrology
should decrease. "s device dimensions shrin&# the challenge for physical metrology will be to &eep pace with inline
electrical testing that provides critical electrical performance data.
1.3 Infrastructure Needs
" healthy industry infrastructure is re%uired if suppliers are to provide cost!effective metrology tools# sensors#
controllers# and reference materials. 'ew research and development will be re%uired if opportunities such as
M3MS!based metrology and nanotechnology are to ma&e the transition from R>) to commerciali$ed products.
Many metrology suppliers are small companies that find the cost of providing new tools for leading!edge activities
prohibitive. Initial sales of metrology tools are to tool and process developers. Sustained# high!volume sales of the
same metrology e%uipment to chip manufacturers do not occur until several years later. The present infrastructure
cannot support this delayed return on investment. ,unding that meets the investment re%uirements of the supplier
community is needed to ta&e new technology from proof of concept to prototype systems and finally to volume
sales.
2 Difficult Challenges
3 Microscopy
Microscopy is used in most of the core technology processes where two!dimensional distributions# that is digital
images of the shape and appearance of integrated circuit /IC1 features# reveal important information. 4sually#
imaging is the first# but many times the only step in the ?being able to see it# measure it# and control it@ chain.
Microscopes typically employ light# electron beam# or scanned probe methods. eyond imaging# online microscopy
applications include critical dimension /C)1 and overlay measurements along with detection# review# and automatic
classification of defects and particles. ecause of the high value and %uantity of wafers# the need for rapid# non!
destructive# inline imaging and measurement is growing. )ue to the changing aspect ratios of IC features# besides
the traditional lateral feature si$e /for example# linewidth measurement1 full three!dimensional shape measurements
are gaining importance and should be available inline. )evelopment of new metrology methods that use and ta&e the
full advantage of advanced digital image processing and analysis techni%ues# telepresence# and networ&ed
measurement tools will be needed to meet the re%uirements of near future IC technologies. Microscopy techni%ues
and measurements based on them must serve the technologists better giving fast# detailed# ade%uate information on
the processes in ways that help to establish process control in a more automated manner.
,or all types of microscopy and for the metrology based on them it is becoming increasingly important to develop
and provide reliable and easy!to!use methods that monitor the performance of the instruments. )ue to the small
si$es of the integrated circuit structures these instruments must wor& at their pea& performance# which is not easy to
attain and sustain. Currently only rudimentary methods are available to ensure ade%uate performance. eyond
imaging and measurement resolution# a host of other# tool!dependent parameters also need to be regularly monitored
and optimi$ed. These &ey parameters have significant influence on the results# and it is indispensable to include their
contribution in the uncertainty statements of the measurements.
Electron Microscopy#There are many different microscopy methods that use electron beams as sources of
illumination. These include scanning electron microscopy# transmission electron microscopy# scanning transmission
electron microscopy# electron holography# and low!energy electron microscopy. Scanning electron microscopy and
electron holography are discussed below# and transmission electron microscopy# scanning transmission electron
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microscopy# and low!energy electron microscopy are discussed in the section on Materials and Contamination
Characteri$ation.
$canning Electron Microscopy %$EM)Acontinues to provide at!line and inline imaging for characteri$ation of cross!
sectional samples# particle and defect analysis# inline defect imaging /defect review1# and C) measurements.
Improvements are needed for effective C) and defect review /and S3M detection in pilot lines1 at or beyond the (+
nm generation. 'ew inline S3M technology# such as the use of ultra!low!energy electron beams /B +C- e01 and high
energy S3M /.-&e0!+--&e01 may be re%uired for overcoming image degradation due to charging# contamination#
and radiation damage of the sample surface# while maintaining ade%uate resolution and depth of field. Improving the
resolution of the S3M by the reduction of spherical aberration leads to an unacceptably small depth of field and
S3M imaging with several focus steps and=or use of algorithms that ta&e the beam shape into account might be
needed. "berration correction lens technology has migrated from transmission electron microscopy to S3M
providing a significant increase in capability. Other non!traditional S3M imaging techni%ues# such as the
implementation of nano!tips and electron holography# need further development to be production!worthy
methodologies. " new alternative path could be high!pressure or environmental microscopy# which opens the
possibility for higher accelerating voltage# high!resolution imaging# and metrology. inary and phase!shifting
chromium!on!%uart$ optical photomas&s have been successfully investigated with this mode of high!resolution
scanning electron microscopy. It has been found that the gaseous sample environment minimi$es sample charging
and contamination. This methodology also holds promise for the inspection# imaging# and metrology of wafers.
)ata analysis methods that adhere to the physics of the measurement and use all information collected were
demonstrated to be better than arbitrary methods.C Measured and modeled image and fast and accurate comparative
techni%ues are li&ely to gain importance in S3M dimensional metrology. " better understanding of the relationship
between the physical ob9ect and the waveform analy$ed by the instrument is expected to improve C) measurement.
Sample damage# which arises from direct ioni$ation damage of the sample and deposition of charge in gate
structures# may set fundamental limits on the utility of all microscopies relying on charged particle beams.
Shrin&age# another form of damage often caused by electron beams on polymer layers# including photoresists# is
now better understood and in many cases can now be predicted and compensated for in C) measurement values. (1)
)etermination of the real () shape for sub!D- nm contacts=vias# transistor gates# interconnect lines# or damascene
trenches will re%uire continuing advances in existing microscopy and sample preparation methods. ,ully automated
cross!sectioning by ,I and semi!automated lift!out for imaging in a T3M or a ST3M has been successfully
demonstrated.
&e 'on Microscopy %&'M)#has been proposed as a means of overcoming the issues associated with the spread in
effect probe si$e due to the interaction of finely focused electron beams and the sample. <otential applications of this
technology include C)# defect review# and nanotechnology. Sub!.nm resolution by *IM has been achieved# but
sample interaction %uestions are as yet unanswered. ,or IC manufacturing metrology# current thoughts are that *IM
needs to be able to fill a &ey gap# the imaging of high aspect ratio etched contact holes and trenches without causing
too much damage# to secure its place as an in!line wor&horse wafer metrology solution.
$canning Probe Microscopy %$PM)Amay be used to calibrate C)!S3M measurements. Stylus microscopes# such as
the atomic force microscope /",M1# offer () measurements that are insensitive to the material scanned. ,lexing of
the stylus degrades measurements when the probe is too slender. The stylus shape and aspect ratio must# therefore#
be appropriate for the probe material used and the forces encountered. *igh stiffness probe materials# such as short
carbon nano!tubes# may alleviate this problem" Other types of scanning probe microscopy are discussed in the
metrology for 3merging Research Materials and )evices section.
Farfield (ptical Microscopy#is limited by the wavelength of light. )eep ultraviolet sources and near!field
microscopy are being developed to overcome these limitations. Improved software allowing automatic classification
of defects is needed. Optical microscopes will continue to have application in the inspection of large features# such
as solder bump arrays for multi!chip modules. "lso# other new experimental optical applications that move beyond
directly measuring from images have potential to allow for measurement of smaller features for measurements or for
process excursion flagging# but more wor& is needed to understand if they have a place for in!line metrology. (2, 3)
,or defect detectionAeach technology has limitations. " defect is defined as any physical# electrical# or parametric
deviation capable of affecting yield. 3xisting S3Ms and S<Ms are considered too slow for the efficient detection of
defects too small for optical microscopes. *igh!speed scanning has been demonstrated with arrayed S<Ms# /that
might be faster than S3Ms1 but issues associated with stylus lifetime# uniformity# characteri$ation# and wear need to
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be addressed. This technology should be pursued both by expanding the si$e of the array and in developing
additional operational modes. "rrayed micro!column S3Ms have been proposed as a method of improving S3M
throughput and operation of a single micro!S3M has been demonstrated. Research is needed into the limits of
electrostatic and magnetic lens designs.
!ithography Metrology
5ithography metrology continues to be challenged by rapid advancement of patterning technology. 'ew materials in
all process areas add to the challenges faced by 5ithography metrology. " proper control of the variation in transistor
gate length starts with mas& metrology. "lthough the overall features on a mas& are four times larger than as printed#
phase shift and optical proximity correction features are roughly half the si$e of the printed structures. Indeed# larger
values for mas& error factor /M3,1 might re%uire a tighter process control at mas& level# too: hence# a more accurate
and precise metrology has to be developed. Mas& metrology includes measurements that determine that the phase of
the light correctly prints. oth on!wafer measurement of critical dimension and overlay are also becoming more
challenging. C) control for transistor gate length continues to be a critical part of manufacturing ICs with increasing
cloc& speeds. The metrology needs for process control and dispositioning of product continue to drive improvements
in measurement uncertainty. "cceleration of research and development activities for C) and overlay measurement
are essential if we are to provide viable metrology for future technology generations. "ll of these issues re%uire
improved methods for evaluation of measurement capability. /Refer to the )ithography chapter.1
On!product monitors of effective dose and focus extend utility of conventional microscopy!based C) metrology
systems in process control applications. The same system can output C) and overlay measurements# as well as
lithography process monitors. <rocess control capability and efficiency of such metrology are improving. The
infrastructure to support such new applications is generally available. Monitors of effective dose and focus for
lithography process control have also been developed for conventional optical metrology systems# such as used in
overlay metrology. Similar capabilities# in addition to C)# sidewall# and height metrology# are now emerging in
scatterometry. In all cases# rather than measure C) for the purpose of process control# with every featureEs C) being
a complex function of both dose and focus# these systems output measurements of process parameters themselves#
with metrology errors as low as .F /( G1 for dose and H.- nm /( G1 for focus. TodayEs process monitor performance
levels boast <=T I -.. for lithography process window with .CF for dose and +-- nm for focus# enabling further
reduction of &. in high volume manufacturing and extending the utility of optical microlithography. 8hile the
demands on metrology systemsE stability and matching are li&ely to increase6# wor& in this area has already initiated
the development of tighter control and matching# being a pre!re%uisite of accurate C) metrology# not 9ust of process
control applications and dedicated process monitors.
Capable and efficient direct process monitor!based lithography process control has the potential to overcome
technology limitations of conventional C) metrology. The ongoing change of lithography process control
methodology can be accelerated by industry collaboration to define the expectations in direct process control# with
tests of performance and standards for both new metrology applications and applications environment. This change
will# li&ely# result in the lithography metrology where capable and efficient means of process control are
supplemented by# and are differentiated from# superior critical dimension metrology proper. 'ew levels of absolute
accuracy are re%uired to meet measurement re%uirements for next generation technology especially in the areas of
C) metrology for calibration and verification of compliance for advanced mas& designs /for example# .!) and +!
)=(!) C) metrology through pitch and layouts# in presence of O<C and R3T# at various printing conditions1.
There is no single metrology method or techni%ue that can deliver all needed information. Therefore# in order to be
able to compare the results of various dimensional metrology tools and methods meaningfully# parameters beyond
repeatability and precision need to be addressed. 3ach measurement application re%uires consideration of the need
for relative accuracy /sensitivity to C) variation and insensitivity to secondary characteristic variation1# absolute
accuracy /traceability to absolute length scale1# 53R and sampling# and the destructive nature of the measurement.
It would be ideal to have all metrology tools properly characteri$ed for measurement uncertainty including a
brea&out of the leading contributors to this uncertainty. It is recommended to use internationally accepted methods to
state measurement uncertainty. This &nowledge would help to ma&e the most of all metrology tools# and it would
prevent situations in which the measured results do not provide the re%uired information. ,inally# once the largest
contributors to measurement errors are &nown# a faster development of better instruments could ta&e place. It is now
recommended to state the measurement uncertainty of various dimensional metrology tools according to
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internationally accepted methods and to identify /%uantify1 the leading contributors.J "nother possibility is the
combination of information from multiple metrology techni%ues into ?hybrid metrology@# where separate# different
dimensional metrology tools not only are calibrated together but can either communicate to each other to share extra
information to improve each otherEs uncertainties and rectify inter!variable correlations. ()
Often# special test structures are measured during manufacturing. 8hen this is the case# active device dimensions are
not measured. C)!S3M continues to be used for wafer and mas& measurement of lines and via=contact. "
considerable effort has been aimed at overcoming electron beam damage to photoresist used by .D( nm exposures K
and that will continue when alternative lithography techni%ues# li&e 340# are introduced: as discussed above in the
microscopy section# these efforts are starting to yield real results. Stac& materials# surface condition# line shape# and
even layout in the line vicinity may affect C)!S3M waveform and# therefore# extracted line C). These effects#
unless they are accurately modeled and corrected# increase measurement variation and total uncertainty of C)!S3M
measurements. )evelopments in electron beam source technology that improve resolution and precision are being
tested. C)!S3M is facing an issue with poor depth of field unless a new approach to S3M!based C) measurement
is found. *igh!voltage C)!S3M and low loss detectors have been proposed as means of extending C)!S3M.
To be able to ma&e statistically sound S3M measurements it is essential to collect the right &ind and amount of
information. The collection of excess information leads to loss of throughput# and by the contrary# collection of not
enough or of the wrong type of information leads to loss of process control. It is important to develop metrology
methods that reveal and express the needed information with the indication of the validity of the measurements.
5arger usable image field!of!view at image resolution!level pixel density allows for much greater utili$ation of
multiple feature measurement /M,M1 applications for increased information per unit time# and thus improved
validity of measurement results# through increased sampling without throughput penalty.
,or C)!S3Ms# )esign!ased Metrology /)M1 applications# which include automatic recipe setup from design
information# allow for practical use of S3Ms for large!scale verification of design intent# through the collection of
feature +) contour shape information and comparison to L)S files. )M applications are becoming very important
for development and verification of lithographic optical proximity corrections /O<C1# as the number of
measurements for successfully developing O<C is expected to grow exponentially with technology generation. "lso#
)M applications for )ouble <atterning are being explored. This is a ma9or role where metrology interfaces with
the )esign for Manufacturing /),M1 community. "lso# collecting and applying C) information from reticle
measurements for comparison to wafer C) measurements is an important application in some cases# and would be
most efficient if done through contours.
*owever# much wor& remains to be done in defining contour error source testing methodologies# contour reference
metrology# and S3M modeling for contours.. .+ .(. Contour fidelity is a prevailing challenge and an area where
improvements in the state of the art could yield value to the industry. Laps or missing segments in contours can
occur for reasons related to both the sample and metrology tool. Ma9or contributors are wea& signal and brea&s
along edges parallel to the /fast1 scan axis and contrast variation along the contour# which could be due to underlying
variations in the structure /e.g.# changes in sidewall angle or reentrance1 or instrumental artifacts# such as edge
proximity effects in an scanning electron microscope /S3M1. In some cases# brea&s in the contour are inherent when
referencing one level to another /e.g.# poly over active1. This sub9ect of contour integrity is closely related to the
accuracy of contour extraction. Contour extraction algorithms employ +!) image processing and thus function
differently than conventional single!measurand critical dimension /C)1 extraction algorithms# which are applied to
individual line scans. There are &nown significant differences specifically with regard to edge detection and the
inherent degree of signal averaging. Sampling can also have a large impact# as averaging as few as five contours can
significantly improve precision and# due to averaging out local roughness effects in discrete features# also improve
agreement between extracted contours and simulation.
"ttention must also be paid to the re%uirements for registration between the S3M contours and the design for
successful O<C. Models must be able to compensate for rotational and lateral offsets between the S3M contour and
the design# as well as for potential field distortions. This relates somewhat to the %uestion of metrology accuracy
versus production accuracy. The extent to which it is acceptable to remove metrology errors when matching
contours to the design is not agreed upon. ,or example# a uniform magnification error removed by stretching the
contour could be less problematic than non!linearity across the S3M field of view.
"nother area in which useful improvements could be made in contour metrology accuracy lies in the statistical
sophistication of the contour extraction and modeling software# for example# the inclusion of a DC F confidence
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interval for the extracted contour. It should be noted that the final metrics in measuring contours should be
compatible with the same conventional linewidth metrics used in this roadmap.
Scatterometry has moved into manufacturing# and does provide line shape metrology. Scatterometry refers to both
single wavelengthAmulti angle optical scattering and to multi!wavelengthAsingle angle methods. Recent advances
have resulted in the ability to determine C) and line shape without the aid of a library of simulated results.
Scatterometry has already been shown to provide a tighter distribution of &ey transistor electrical properties when
used in an advanced process control mode. One next step is the development of scatterometry for contact and via
structures# and for features with complexity which re%uire many parameters to model. Scatterometry models assume
uniform optical property of line and bac&ground materials. Surface anomalies and non!uniform dopant distribution
may affect scatterometry results. Therefore# scatterometry models need calibration and periodic verification.
5ithography and etch microloading effects may noticeably affect line C). Since scatterometry ma&es measurements
on special test structures# other C) metrology techni%ues /such as S3M# ",M# or T3M1 need to be employed to
establish correlation between C) of the scatterometry structure and C)s of the circuit. Scatterometry needs to be
capable of measuring smaller test structures while improving measurement precision. The increasing usage of
double patterning may create some issues in measurement of double!patterned features# as many more parameters
must be measured and controlled# potentially including two statistically distinct C)# sidewall# roughness# and pitch
/overlay1 populations. In some schemes# an "RC may prevent the 40 light from penetrating deeper layers.
'ew C) measurement methods have been proposed# and it seems li&ely the first opportunity for them to move into
manufacturing is at the .6 nm )R"M half pitch. The ++ nm half pitch is already well into the development stage
and beta e%uipment is available for all process areas. The new potential solutions include the *e ion microscope
/discussed in the microscopy section1 and small angle x!ray scattering /C)!S"MS1. 4sing transmission
measurements and a grating structure# C)!S"MS has shown the ability to measure average C)# sidewall roughness#
and C) variation from an individual line in a grating structure# and for more complex lines through multiple layers.
The use of ?feed forward@ control concepts must be extended to lithography metrology ta&ing data at least from
resist and mas& measurements and controlling subse%uent processing# such as etch# to improve product performance.
?,eed bac&@ controlling strategy is re%uired as well to set properly process parameter setup from a huge amount of
previously collected data. The use of overlay measurement e%uipment for C) control has also been reported. This
method is based on the fact that the change in line width also affects the length of the photoresist lines that can then
be measured using the optical microscope of the overlay system. " special test structure with arrays of line and
arrays of spaces is re%uired.
C)!",M measurements can be used to verify line shape and calibrating C) or contour measurements. 'ew probe
tip technology and (!) tiltable cantilever is re%uired if C)!",M is to be applied to dense line measurement below
C- nm. ,ocusN3xposure correlation studies /especially for contact=via1 can be using all of the above methods as well
as by the dual column ,I /S3M plus ,ocused Ion eam1 where there is an immediate correlation with line shape.
3lectron holography has been proposed as a long term C) measurement technology.
"t some upcoming technology node# some say .6 nm# the bul& of logic manufacturing will leave the simpler realm
of planar devices and move to non!planar architectures such as ,im,3Ts# and a similar transition for memory
architecture is already imminent. This will cause many new issues to metrology# where the main variables for
process control may not be the bottoms of profiles. Thus# truly () metrology with great sensitivity will be re%uired.
.1 !ine "oughness
5ine edge roughness /53R1 is an important part of lithography process control# and line width roughness /58R1 is
an important part of etch process control. The 5ithography Roadmap provides metrics for both 53R and 58R. 58R
correlates to an increase in transistor lea&age current but not to changes in drive current. 53R and 58R are
determined per the S3MI standard definition..C It is important to note that the precision re%uirements for 53R and
58R are several years ahead of those re%uired for C) as indicated below. C)!S3M and lithography process
simulation systems have software that determines 53R and 58R# but not all systems yet adhere to the S3MI
standard for 53R and 58R measurement.
53R=58R is evaluated by two methods; spectral analysis and measurement of 53R=58R amplitude=degree
/generally# ( G of residuals from average position or average C)1. ,ourier spectrum of 53R=58R is becoming
popular in R>): however# ( G is still the most useful index for practical in!line metrology. In evaluating 53R=58R#
Page ' o6 #
length of the inspected edge# 5# and sampling interval of edge!detection# Oy# are the most important measurement
parameters because ( G strongly depends upon these values.
The recommended 53R=58R metric is thus defined as the (G of residuals measured along +! P m!long line for the
present: however# transistor performance could be more sensitive against in!gate roughness in the future. In that
case# a new index for in!gate roughness /such as high!fre%uency 58R1 should be additionally defined. To evaluate
58R!caused gate!C) variation separately# low!fre%uency 58R index should also be defined.
"nother important factor in measurement of 58R=53R on imaging tools is edge detection noise. This noise has the
effect of adding a positive bias to any roughness measurement. This is shown by the e%uation 58Rmeas+ I 58Ractual+
Q GR+ where 58Rmeas is the measured value# 58Ractual is the actual roughness of the target# and GR is the noise term#
defined as the reproducibility of locating an edge along one single sampling point. The si$e of GR has been measured
to be on the order of + nm# which means that at future technology generations this measurement artifact could mas&
the actual roughness to be measured. " methodology has been demonstrated to remove this noise term# leading to an
unbiased estimation of the roughness. 4se of this is deemed very important to ensuring accuracy of roughness
measurement in the future# and should be a &ey ingredient in allowing for intercomparison of data across the litho!
metrology community. It should be noted that 58R metrology becomes more challenging when the resolution of the
metrology tool becomes close to the 58R re%uirement. "t the ++ nm node the 58R re%uired is ..( nm. Current C)!
S3M e%uipment has comparable resolution performance.
.2 Measure#ent $ncertainty
Critical dimension measurement capability does not meet uncertainty re%uirements that comprehend measurement
variation from individual tool reproducibility# tool!to!tool matching and sample!to!sample measurement bias
variation. <recision is defined by S3MI as a multiple of reproducibility. Reproducibility includes repeatability#
variation from reloading the wafer# and long!term drift. In practice# reproducibility is determined by repeated
measurements on the same sample and target over an extended period of time. "lthough the precision re%uirements
for C) measurement in the ITRS have always included the effects of line shape and materials variation# repeated
measurements on the same sample would never detect measurement uncertainty related to sample!to!sample bias
variation. Therefore# with the current methodology the uncertainty of measurement associated with variation of line
shape# material# layout# or any other parameters will not be included in the precision. Typically# reference materials
for C) process control are specially selected optimum or ?golden@ wafers from each process level. Thus# industry
practice is to determine measurement precision as a reproducibility of the measurement for each process level. The
measurement bias is not detected. This approach misses measurement bias variation component of measurement
uncertainty. In light of this# a metric# total measurement uncertainty /TM41 can be used. The TM4 is determined
using a technology representative set of samples that accounts for variations in measurement bias associated with
each process level. This idea can be extended to use with a production fleet of tools through another metric ,leet
Matching <recision /,M<1. These metrics assume accuracy for all tools# and that a fleet of tools behave as well as a
single tool would be re%uired. It should be noted that other metrics for accuracy and matching are also available.
Calibration of inline C) metrology e%uipment re%uires careful implementation of the calibration measurement
e%uipment referred to as reference metrology. ,or example# laboratory based T3M or C)!",M must have precision
that matches or exceeds inline C) and have to be fre%uently calibrated. Reference materials used during
manufacturing must be representative to the actual process level and structure and reflect the pertinent process
variations to be evaluated by the tool under test. Reports of this approach already exist.
C) measurement has been extended to line shape control. Tilt beam C)!S3M# comparison of line scan intensity
variation versus line scans from a golden wafer# scatterometry# C)!",M# dual beam /electron and gallium ion beam
systems1 and triple beam /electron# Lallium ion beam and "rgon ion beam systems1 have all been applied to line
shape measurement. Sidewall angle has been proposed as the &ey process variable. "lready# photoresist lines have
shapes that are not well described by a single planar description of the sidewall. 5ine edge and line width roughness
along a line# vertical line edge roughness# and rounded top shapes are important considerations in process control.
"s mentioned above# precision values change with each process level. This adds to the difficulty in determination of
etch bias /the difference in C) before and after etch1. 3lectrical C) measurements provide a monitoring of gate and
interconnect line width# but only after the point where rewor&ing the wafers is no longer possible and does not allow
a real!time correction of process parameter. 3lectric C) measurements are limited in their applicability to
conducting samples.
Page ) o6 #
Mas& metrology is moving beyond the present optical technology. inary and phase!shifting chromium on %uart$
optical photomas&s have been successfully investigated with high!pressure=environmental scanning electron
microscopy. 3nvironmental S3M instrumentation e%uipped with high!resolution# high!signal# field emission
technology in con9unction with large chamber and sample transfer capabilities are in use in the semiconductor
industry for mas& C). The high!pressure S3M methodology employs a gaseous environment to help to compensate
for the charge build!up that occurs under irradiation with the electron beam. "lthough potentially very desirable for
the charge neutrali$ation# this methodology has not been seriously employed in photomas& or wafer metrology until
now. This is a new application of this technology to this area# and it shows great promise in the inspection# imaging#
and metrology of photomas&s in a charge!free operational mode. This methodology also holds the potential of
similar implications for wafer metrology. ,or accurate metrology# high!pressure S3M methodology also affords a
path that minimi$es# if not eliminates# the need for charge modeling.
5ithography metrology consists not only of overlay and C) metrology# but also includes the process control and
characteri$ation of materials needed for lithography process# especially photoresists# phase shifters# and
antireflective coatings /"RCs1. "s these lithography materials become more complex# the materials characteri$ation
associated with them also increases in difficulty. "dditionally# most non!lithography materials used in the wafer
fabrication process /gate oxides# metals# low!2 dielectrics# SOI substrates1 enter the lithography process indirectly#
since their optical properties affect the reflection of light at a given wavelength. 3ven a small variation in process
conditions for a layer not normally considered critical to the lithography process /such as the thic&ness of the buried
oxide in SOI wafers1 can change the dimensions or shapes of the printed feature# if this process change affected the
optical response of the layer.
"s a minimum# the complex refractive index /refractive index n and extinction coefficient 21 of all layers needs to
be &nown at the lithography wavelength. 5iterature data for such properties are usually not available or obsolete and
not reliable /derived from obsolete reflectance measurements on materials of un&nown %uality followed by
Sramers!Sronig transform1. In ideal cases# n and 2 can be measured inline using spectroscopic ellipsometry at the
exposure wavelength. 3specially below .D( nm# such measurements are very difficult and usually performed outside
of the fab by engineering personnel. 340 optical properties can only be determined using speciali$ed light sources
/such as a synchrotron or a 340 source for a 340 litho tool1. Therefore# materials composition is often used as a
figure of merit# when direct measurement of the optical properties is not practical. ut even two materials with the
same composition can have different optical properties /ta&e amorphous and crystalline Si as an example1.
"dditional complications in the determination of the optical properties of a material arise from surface roughness#
interfacial layers# birefringence# or optical anisotropy /often seen in photoresists or other organic layers responding
to stress1# or depth!dependent composition. ,or some materials for a wafer fab# it is impossible to determine the
optical properties of such material# since the inverse problem of fitting the optical constants from the ellipsometric
angles is underdetermined. Therefore# physical materials characteri$ation must accompany the determination of
optical properties# since physical characteristics# materials properties# and optical constants are all inter!related.
Overlay measurements are challenged by phase shift mas&s /<SM1 and optical proximity correction /O<C1 mas&s#
and the use of different exposure tools and=or techni%ues for different process layers will compound the difficulty.
,uture overlay metrology re%uirements# along with problems caused by low contrast levels# will drive the
development of new optical or S3M methods along with scanning probe microscopy /S<M1. The need for new
target structures has been suggested as a means of overcoming the issues associated with phase shift mas& and
optical proximity mas& alignment errors not detectable with traditional targets. Overlay for on!chip interconnect will
continue to be challenging. The use of chemical mechanical polishing for planari$ation degrades target structures.
Thus as re%uirements for tighter overlay control are introduced# the line edge of overlay targets in interconnect are
roughened. The low!2 materials used as insulators will continue to ma&e overlay more difficult especially as porous
low 2 move into manufacturing.
The dramatic tightening of the overlay budget up to +-F Tor +CFU of the device half!pitch# re%uired for advanced
applications in )R"M and '0M# calls for a faster introduction of alternative measuring solutions# li&e high!voltage
S3M and scatterometry techni%ues# which are still far from being mature enough today# and may re%uire
brea&throughs also in metrology integration.
The introduction of 340 lithography re%uires further development in the area of 340 mas& metrology and 340
"erial Image Measurements Systems /340 "IMS1.
Page 10 o6 #
The 5ithography Metrology Re%uirements Tables are divided into wafer and mas& re%uirements Tables M3T(# and
M3TVa and M3TVb# respectively. The mas& metrology re%uirements in Tables M3TVa and M3TVb are further
divided into the needs for each type of exposure technology; optical# 340# and electron pro9ection.
.3 %&planation 'f $ncertainty In (a)les Met3 *nd Met
The preceding concepts are summari$ed by the following consideration for the precision of patterning metrology;
the definition for precision critically depends on the application. Liven the application and the metrology
instrument# a sampling plan needs to be defined. The precision specification needs to be interpreted in light of
application# instrument# and sampling plan. The application defines the accuracy# single tool precision# and matching
re%uirements. In some applications# the relative accuracy and single tool precision are paramount. In some
applications# tool matching and single tool precision are paramount. In some applications# a single measurement
event is not sufficient to provide the needed measurement: rather the average of multiple measurement events
constitute the critical measurement episode: in this case the precision should be interpreted as the uncertainty
re%uirement of the average. The precision numbers in the tables are changed to uncertainty numbers. The relation to
precision and uncertainty /G1 is given in formula /.1.
G
+ I
G<
+
QGM
+
QGS
+
QGother
+
/.1
4ncertainty /G1 contains the following components; G< /<recision1# GM /Matching1# GS /Sample variation1 and Gother
/inaccuracy and other effects1. 8e assume normal distributions where each factor is independent and only random
variations occur. (+)
Table MET* )ithography Metrology %+afer) Technology ,e-uirements
Table MET.a )ithography Metrology %Mas!) Technology ,e-uirements/ (ptical
Table MET.b )ithography Metrology %Mas!) Technology ,e-uirements/ EU0
Figure MET1a )ithography Metrology Potential $olutions/ 23
Figure MET1b )ithography Metrology Potential $olutions/ (verlay
+ ,ront %nd -rocesses Metrology
The industry continues to find means of extending CMOS. The recent announcement that ,in,3T transistors will be
introduced into manufacturing for the (( nm W pitch indicates that future CMOS will be both planar and non!planar.
4ltra!thin body SOI is expected to extend planar CMOS# and the scaling of SOI thic&ness may slow over the next
ten years. Since first generation high and metal gate is in manufacturing# research and development efforts are
aimed at increasing . Mobility enhancement through local stress remains a &ey means of scaling transistors. 'ew
channel materials will further enhance mobility. ,in,3T transistors are expected to use high and metal gate while
increase in mobility will be achieved using different technology than that used for planar CMOS. The metrology
community continues research and development to fill these measurement needs. It is important to note that
characteri$ation and metrology must be tailored to the specific process used to fabricate the transistor. IC
manufacturers continue to use a variety of different designs# and transistor design is a differentiator for IC
manufacturers. 3xamples of these differences can be highlighted by <MOS process and design for previous
technology generations. "lthough the dual stress liner approach is predominant# but the use of SiLe in the source
and drain is also used in manufactured ICEs. Transistor cross!sections also show a variety of spacer oxide dimensions
and processes. In this section the specific metrology needs for starting materials# surface preparation# thermal=thin
films# doping technology# and front!end plasma etch technologies are covered. <rocess integration issues such as
variability# the need to control lea&age current# and the reduction in threshold voltage and gate delay and their
tolerances will interact with the reality of process control ranges for gate dielectric thic&ness# doping profiles#
9unctions# and doses to drive metrology needs. Modeling studies of manufacturing tolerances continue to be a
critical tool for transistor metrology strategy. Metrology re%uirements for ,ront 3nd <rocesses are shown in Table
M3TC# and the potential solutions are shown in ,igure M3TC.
Table MET4 Front End Processes Metrology Technology ,e-uirements
Page 11 o6 #
The impact of shrin&ing dimension on ,3< metrology is already at the point where research devices and materials
exhibit materials properties associated with nano!science. ,or example the properties of nanowire li&e shapes such
as a ,I' in a ,I',3T are %uantum confined in two dimensions.
+.1 Starting Materials
Many of the metrology challenges related to starting materials involve the emerging class of layered materials such
as SOI and strained silicon on SOI. The trend toward thinner layers# along with multiple layer interfaces# poses a
challenge to most material metrology techni%ues.
"reas of concern include the following;
. ul& 'i and Cu measurement on pQ# silicon on insulator /SOI1# strained silicon /SSi1# and strained silicon
on insulator /SSOI1 wafers
+ Measurement of .-DN.-.- cm!( ,e /and other bul& metals1 in the top Si of thin SOI wafers
( Thic&ness and uniformity of very thin SOI layers /B+- nm1
V )efectivity of thin layers /e.g.# threading dislocations# ?*, defects@1
C <article detection /B.-- nm1 on layered surfaces
Small particle detection continues to be of concern for the future. 'ote that due to metrology capability issues the
silicon starting materials particle re%uirements below 6C nm si$e will not re%uire sub!6C nm metrology but will
model the critical number of sub!6C nm particles based upon the number of particles detected at 6C nm si$e. More
information can be found in the Starting Materials section of the Front End Processes chapter.
$ilicon(n'nsulator %$(') is entering the mainstream of IC device applications# and this is expected to grow further
along the Roadmap. Recent device wor& has motivated a prediction of an increase in SOI thic&ness at ++ nm W pitch
from J nm of Si to H .- nm. This is predicted to follow another decrease in thic&ness for several W pitch nodes.
This prediction may not follow the ,3< roadmap SOI timing. One unmet challenge is the measurement of SOI
uniformity inside die!si$ed areas. "cross!wafer uniformity must also be characteri$ed. "n expectation has been that
the materials specifications for polished silicon substrates would be transferred to SOI specifications. *owever# the
underlying insulator structure in SOI negatively affects many of the metrology capabilities used for polished silicon
substrates. Thus# there is some difficulty to measure and control SOI material properties at the level desired. The
metrology community has addressed this but some issues remain. ,or more details on these metrology challenges
see the ,3< chapter on Starting Materials.
+.2 Surface preparation
'n situ sensors for particles# chemical composition# and possibly for trace metallics are being introduced to some wet
chemical cleaning tools. <article detection is covered in the Yield Enhancement chapter" <article=defect and
metallic=organic contamination analyses are covered in the Materials Characteri$ation Section of the Metrology
chapter. The role of impurities in high!2 gate dielectrics# and therefore their measurement re%uirements# is a future
research topic. ,or the present the re%uired impurity levels are pro9ected to be the same as for silicon oxynitride gate
dielectrics# but the measurement of those impurities is not clear.
+.3 (her#al.thin fil#s
'ext generation high = metal gate technology may use nano!crystalline *f based oxides. "s these alternative
oxides are being developed# new metrology challenges are emerging. The high 2 gate stac& contains several
significant challenges that re%uire further research and development. The Metrology roadmap previously discussed
the challenges associated with measurement of nitrogen concentration in high!2 dielectrics. If nano!crystalline
films are used# film crystal structure must be characteri$ed to determine phase and texture. The composition of wor&
function ad9usting films must also be characteri$ed. The films used to ad9ust the gate wor& function are very thin
and nanoscale roughness may prove to be of the same dimensions as film thic&ness ma&ing it impossible to use
some traditional measurement methods. Materials characteri$ation of annealed gate stac&s challenges all methods
including ultra!high resolution T3M. In addition# new )R"M structures that use mixed high!2 dielectrics# and even
ultra!thin layers of stac&ed high!2 dielectrics# will challenge metrology development.
Metrology research and development is re%uired for advancement of new channel materials including germanium
and III!0s. Measurement needs are driven by the challenges associated with producing defect free crystal structures
due to lattice mismatch with the silicon substrate. Measurement needs include observation and %uantification of
Page 12 o6 #
defect states in the band gap and dislocation densities. Many measurements re%uire blan&et films. "t this time#
correlation of measurements of blan&et films with channel layers in transistors will re%uire use of cross!sections
which may not be representative of the total transistor structure.
+. Strained Si processes
Carrier mobility enhancement through process or structure induced local stress continues to beis a critical means of
improving drive current and thus transistor performance. Typically# 'MOS transistors are given tensile stress by
applying Si('V stress liner film over the gate electrode. One of several different processes is used for <MOS
transistors. In the replacement source!drain process# <MOS transistor channels are given compressive stress by the
replacement of the silicon in the source and drain with selectively grown SiLe. The second means is through a
compressive Si('V stress liner. Shallow trench isolation /STI1 is another source of compressive stress in the channel.
*ere# the pattern layout of active area# gate electrode# and contact hole must be carefully designed and the processes
should be tightly controlled. " combination of techni%ues and selection of Si crystal orientation in the channel have
also been proposed. 'ew processes in the development phase re%uire stress characteri$ation and metrology. These
include a Si;C /heavily carbon!doped silicon1 replacement source!drain process which is under consideration for
'MOS. SiC would induce tensile stress in the 'MOS channel region. "s changing the materials of gate electrodes
and by introducing so!called Late 5ast process# sources of stress has been increasing. Thus necessity of local stress
metrology techni%ue is highlighted. It is &nown that Through Silicon 0ia /TS01 is another source of stress. In order
to eliminate negative effect on transistors near TS0s# a metric of Seep Out Xone /SOX1 is introduced. "nother
explanation of stress measurement is shown in the sub!chapter of () interconnect metrology.
In order to accelerate design of the pattern layout and process conditions# a non!destructive direct measurement of
the stress in the nano!si$ed area is desired. The importance of ,inite 3lement Simulations of stress and resulting
electrical properties has already been shown to be a &ey aspect of process development and metrology. "ccurate
stress metrology can help calibrate these simulations. "s new processes are introduced with new technology
generations# the challenge renews itself. ,urther complicating the challenge is the timing of the potential transition
to alternate channels and the introduction of ,I',3TS or wrap around gatesTrigate structure. This year l5ine items
for local stress=strain measurements for both of off!line and in!line metrology have beenwere introduced to the
metrology technology re%uirements Table M3TC. It is expected that test pad would be used for in!line stress=strain
measurement and its si$e is estimated asat around .-- Pm Y .-- Pm. This test pad si$e should be reduced as same as
another metrology test pad such for film thic&ness measurement or OC) measurement.
Review of Stress Measurement Methods is shown in ,igure M3T(. This review shows a clear contrast in spatial
locali$ation capability between off!line methods such as 'anoconvergent beam electron diffraction )iffraction
/C3)')1 and potential in!line methods from the stand points of off!line destructive metrology and in!line non!
destructive metrology. In the case of Raman spectroscopy# area of measurement depends not only on microscopic
spatial resolution but also wavelength of illumination light. This is due to the penetration depth of the light.
Figure MET* ,eview of $tress5$train Measurement Methods
+.+ ,%"*M
"lthough the thic&ness of the dielectric films are .-- to +-- nm# optical models for inline film thic&ness
measurement of the metal oxides must be developed when a new materials set is used. The main metrology need is
for fatigue testing of the capacitor structures at .-.6 read write cycles and above.
Cross!sections of memory devices illustrate the challenges associated with fabrication and process control for
complex () memory structures created in a se%uence of at least two patterning levels /pattern over pattern1. Many
measurement needs are not covered by simplified test structures. The impact of overlay errors is illustrated in ,igure
M3TV. Cross!sectional metrology needs such as improved dimensional precision are a &ey re%uirement for memory
and other () structures.
Figure MET. *3 Metrology ,e-uirements
+./ Doping technology
Improved inline process measurements to control active dopant implants is re%uired beyond (+ nm. <resently# V!
point probe measurement is used for high dose implant and p7otomodulated opt89al re:e9ta;9e <PMOR1 is
used for low!dose implant process control. <MOR has been shown capable of measuring active dopant profiles.
Page 1 o6 #
"dvances in <MOR are needed to extend it to thin SOI. " new techni%ue that provides direct in situ measurement of
dose# dopant profile# and dose uniformity would allow real!time control. 'ew methods for control of # <# and "s
implants are also needed# and several inline systems based on x!ray=electron interactions optimi$ed for # <# and "s
dose measurement have recently been introduced. Offline secondary ion mass spectrometry has been shown to
provide the needed precision for current technology generations including ultra!shallow 9unctions. The range of
applicability and capability of new# non!destructive measurement methods such as carrier illumination /an optical
technology1 are under evaluation. Two! and preferably three!dimensional profiling of active dopant concentrations is
essential for achieving future technology generations. "ctivated dopant profiles and related TC") modeling and
defect profiles are necessary for developing new doping technology. 'anoscale scanning spreading resistance
/SSRM1 measurements done in high vacuum have proven capable of achieving the necessary spatial resolution for
dopant concentration gradients. Recent results indicate that *0!SSRM is capable of measuring between . and ..C
nm=decade in carrier concentration with a precision of between ( to CF.
The measurement of dopant profiles in +)=() structures# such as ,I',3Ts# is a challenge. Indirect methods such as
fin resistivity in test structures may detect process changes# but the direct determination of the dopant profile and its
conformality is difficult.
Figure MET4 FEP Metrology Potential $olutions
/ 3D IN(%"C'NN%C( M%("'!'01
() Interconnect process technology is covered in both the "ssembly and <ac&aging as well as
the Interconnect Roadmaps. The main challenges for () metrology involve measuring high
aspect ratio through!silicon vias /TS01# and the opa%ue nature of materials /silicon# copper1 that
limit optical microscopy techni%ues. These challenges are characteri$ed by two different tool
sets: in!line metrology and off!line metrology using destructive analysis.
)evelopment of manufacturable () processes is also dependent upon a broad range of existing
semiconductor metrologies including but not limited to: thin film metrology# wafer topography#
surface roughness# pac&aging metrologies and electrical test. These metrologies are not
addressed in this section of the ITRS.
Page 1# o6 #
(a)le 1 I("S 3D Interconnect (S2 "oad#ap
/.1 3onding o4erlay
0alidation of the performance of process e%uipment for bonding wafers for () interconnects will
re%uire the use of infrared /IR1 microscopy to measure alignment fiducials at the interface of the
bonded wafer pairs /8<1# comparing overlay error to overlay tolerance# then determining if
overlay accuracy is sufficient for electrically yielding interconnects. Silicon is transparent to IR
radiation# which is able to penetrate through full thic&ness /JJC microns thic& for (--mm
diameter wafers1 silicon wafers# enabling the measurement of overlay.

Currently# there are a number of IR microscope tools capable of supporting in!line overlay
metrology re%uirements for bonded wafer pairs in high volume manufacturing /*0M1. They use
either broadband IR /typically from a halogen lamp1# or a specific IR laser generated wavelength
/typically .(.- nm1. "n IR metrology tool for this purpose and has demonstrated repeatability of
overlay measurements on bonded wafer pairs with . sigma repeatability of less than -.. Zm. The
spatial resolution of this system based upon the Rayleigh criterion is H -.C Zm. In the case where
the carrier substrate is transparent to visible light# the use of metrology e%uipment with a Top and
ottom microscope configuration can also be an alternative solution. This configuration can also
demonstrate repeatability . sigma of less than -..microns.
4sing in!line overlay metrology is necessary to identify poorly aligned wafer pairs that are
unli&ely to provide electrically yielding interconnects. "s a result# those costs and time
associated with subse%uent wafer processing are avoided# and the feed!bac& loop for bonding
process control is closed. IR microscope resolution at -.C micron matches the interconnect
roadmap for overlay accuracy +--D N +-.+. Improved overlay accuracy as specified in the
roadmap re%uires an improvement in overlay resolution for +-.+ and beyond.
Page 1, o6 #
Overlay performance is an inherently +) parameter. Circular via features are bonded to circular
bond pads# in patterns that span the full si$e of the wafer pair. Most statements of overlay
performance focus on performance in a single axis. )efinitions of overlay that are consistent
with the multi!dimensional nature of the actual re%uirement and test methods that account for
overlay performance throughout the entire wafer area should be defined in ITRS +-...
/.2 3onded interface 4oid detection
Lood bonding at the interface of a bonded wafer pair is critical to ensure that the wafer pair does
not separate during subse%uent operations li&e wafer thinning and wafer bevel edge trim.
Scanning acoustic microscopy /S"M1 has proven useful to detect and characteri$e bond voids at
the interface of a 8<. 4sing transducers /typically ..- M*$1 to create ultrasound# and a
couplant li%uid to transmit ultrasound to the 8< surface /typically )I water1# S"M can survey
the interface of a bonded wafer pair and detect voids as reflections of ultrasonic energy. S"M
resolution is improved by using higher fre%uency ultrasound and thinning wafers to decrease
ultrasound attenuation# but thinning wafers to achieve improved S"M resolution is not a
manufacturable solution for metrology in *0M. The throughput of this method must also be
improved for volume production.
Currently# there are a number of S"M tools capable of supporting in!line void metrology
re%uirements for bonded wafer pairs in high volume manufacturing. )ry!in# dry!out S"M
systems that use a 'itrogen stream to remove couplant li%uid from the external surfaces of a
bonded wafer pair are available. There is some concern for added defectivity as a result of the
couplant li%uid used /particles# metallics1# but subse%uent thinning operations and the cleaning
steps that follow are expected to be sufficient for reducing S"M!induced defects. "nother
concern is lac& of heremeticity at the interface of the bonded wafer pair that can allow couplant
li%uid incursion into the interface via capillary action. The use of a li%uid spray instead of
complete immersion could be an attractive alternative.
4sing in!line void metrology is necessary to identify wafer pairs that have the potential to
separate during subse%uent wafer thinning and edge bevel trimming operations. S"M resolution
for 8< voids approaches 6- microns /using a ..-M*$ transducer1. "lthough there is no bond
void re%uirement specified in the ITRS# it is recommended to be included in the +-.. revision.
/.3 3onded interface defect identification
Currently# there are no metrology tools capable of supporting in!line bonded wafer pair defect
identification with defect mapping in a Cartesian coordinate system for subse%uent defect
review. "lthough there is no 8< defect identification re%uirement specified in the ITRS# it is
recommended that it be included in the +-.. revision.
/. 3onded interface defect re4ie5
onding wafers for () interconnects will re%uire the use of infrared /IR1 microscopy to locate
and review defects at the interface of a bonded wafer pair. These defects are present on
individual wafers prior to bonding /particles# CM< damage1 or generated during the bonding
process /voids# adhesive anomalies# dendritic structures1 . 8< defect review tools will need to
Page 1. o6 #
be able to merge individual wafer defect maps into a combined 8< map# and will re%uire the
ability to add any new defects randomly observed during defect review.
Currently# there are defect review tools using an IR microscope capable of supporting defect
review re%uirements for bonded wafer pairs in high volume manufacturing. "n IR microscope
is not useful as a defect identification tool as outlined in section +.(. The field of view of the
microscope is relatively small# and .--F inspection of the entire wafer is not feasible. *owever#
defects can be manually identified at the interface of the 8< and added to its defect map.
"lthough there is no 8< defect review re%uirement specified in the ITRS# it is recommended
that it be included in the +-.. revision.
/.+ %dge )e4el defects
3dge bevel inspection is re%uired to identify defects in a bonded wafer pair that can lead to
subse%uent wafer brea&age. 3dge bevel defects can be problematic at bonding. 3dge bevel
chips can initiate cleave lines for silicon wafer brea&age when the forces associated with bonding
or thinning wafer pairs are applied. The control of the notch alignment of bonded wafer pairs
with an accuracy of less than C- microns is also needed. 8afer edge bevel trim operations that
precede bonded wafer pair thinning can be another source of edge bevel defects.
Currently# there are a number of edge bevel inspection tools capable of supporting in!line
metrology re%uirements for bonded wafer pairs in high volume manufacturing. "lthough there is
no edge bevel defect re%uirement specified in the ITRS# it is recommended that it be included in
the +-.. revision.
/./ 3ond strength unifor#ity
Currently# there are no in!line tools to assess bonded wafer pair strength uniformity. Micro!
chevron testing for 8< strength uniformity uses a wafer with an etched pattern /micro!
chevron1# bonded to a blan&et film wafer that is subse%uently speciated into individual die and
tested for adhesion strength using a pull!tester. Mapping bonding strength results for multiple
die on a 8< allows calculations for within!wafer pair non!uniformity# and indicates
ad9ustments to the wafer bonding hardware are re%uired when strength uniformity results drift
outside of established control limits. Micro!chevron testing is more sensitive and repeatable than
other bond strength tests li&e V!point bend.
"lthough there is no 8< strength uniformity re%uirement specified in the ITRS# it is
recommended that it be included in the +-.. revision by specifying micro!chevron testing as
described in S3MI[ standard MS!C.
/.6 3onded 7afer -air thic8ness
Total thic&ness and intra!wafer total thic&ness variation /TT01 of the 8< is crucial for the
bonding and grinding operation. Currently# there are a number of metrology tools capable to
support in!line measurement. Traditional capacity method techni%ue has limitation in the case of
non!conductive substrate. The white light or IR chromatic as well as interferometry techni%ue
can provide very good alternative for total thic&ness measurement when implemented in a top
and bottom dual mode configuration.
Page 17 o6 #
The measurement of individual layers consisted of the 8< will generally re%uire the use an IR
light source to pass through the Silicon layers. The drawbac& of the IR interfometer techni%ue is
lac& of resolution for thin layers. 8ith improvement in detection treatment algorithm# thin layers
such as the adhesive layer itself could be measured.
/.9 (S2 etch depth
Through!silicon vias are etched at a very high aspect ratio /*"R1 of via diameter to etch depth#
approaching .-;. ! +-;.. These *"R features challenge and limit the use of optical metrology
techni%ues for measuring smaller diameter TS0s.
Currently# there are a number of TS0 etch depth metrology tools capable of supporting in!line
metrology re%uirements in high volume manufacturing. )epending on the principle of the
techni%ues involved and its spot si$e# the measurement can be done on individual TS0# on an
average number of TS0s or will re%uire a specific periodic array of TS0s.
8hite light interferometry and bac&side infrared interferometry can be used for measuring etch
depth of individual TS0s for C micron and larger diameter TS0s with less than .-;. aspect ratio.
,or white light interferometer and smaller diameter# improvement in sensor configuration is
needed to get paralleled collimated light to able to be reflected down to the bottom TS0.
ac&side infrared interferometry has been demonstrated as capable for TS0 etch depth
metrology for sub!micron features# and is not limited by aspect ratio.
The model based infrared reflectometry on an array of TS0s could be another alternative for
depth measurement of diameter below Cmicrons at the condition the density of via is high
enough to get diffracted signal. This techni%ue is not a direct techni%ue and will re%uire cross!
section analysis for calibration.
"lthough there is no TS0 etch depth metrology re%uirement specified in the ITRS# it is
recommended that it be included in the +-.. revision.
/.: (S2 etch profile
Currently there are no in!line TS0 etch profile metrology tools suitable for use in high volume
manufacturing. Cross!section S3M analysis can be utili$ed for process development# but it is a
destructive techni%ue. "lthough there is no TS0 etch profile metrology re%uirement specified in
the ITRS# it is recommended that it be included in the +-.. revision.
/.1;(S2 liner, )arrier, seed thic8ness
)eposition of liner# barrier and seed films is challenged by the high aspect ratio of the TS0 and
directional film deposition processes. Continuous# pin!hole free films in the TS0 are re%uired to
electrically isolate# prevent copper migration and encourage good copper fill in the subse%uent
copper plating process.
Currently there are no in!line tools suitable for TS0 liner# barrier and seed thic&ness metrology
for use in high volume manufacturing. Cross!section S3M and T3M analysis can be utili$ed for
process development# but are destructive techni%ues. 3lectrical test structures can be utili$ed for
measuring lea&age and electro!migration# but the information they provide is obtained after
many subse%uent operations following liner# barrier and seed deposition.
"lthough there are no TS0 liner# barrier and seed thic&ness metrology re%uirements specified in
the ITRS# it is recommended that they be included in the +-.. revision. ..1.12 TS/ =o8d>
Page 1' o6 #
Micro!voiding in the TS0 or in the interconnect bond region could lead to electrical or reliability
failures. 4sing standard cross!sectioning or ,I=S3M techni%ues it is possible to destructively
evaluate the condition of a selected bonded vias. 'on!destructive methods to identify these
defects would provide significant benefits for both process development and failure analysis.
TS0 void metrology is challenged by the opa%ue nature of copper: optical metrology techni%ues
for void detection are not available. "coustic wave techni%ues are also investigated through the
change in total volume of the copper lines. The capability to scan the whole TS0 depth as well as
the sensitivity to micro!void has to be demonstrated. Copper plating is challenged by the high
aspect ratio of the TS0: any tendency towards conformal plating must be carefully controlled by
plating bath additives to ensure bottom!up filling.
M!ray and x!ray tomography techni%ues have proven useful to reveal voids within copper!filled
TS0s# but are slow and re%uire destructive sample preparation. M!ray tools cannot be
considered as in!line TS0 void metrology for high volume manufacturing# but are useful for
feedbac& on TS0 plating process development.
"lthough there is no TS0 void metrology re%uirement specified in the ITRS# it is recommended
that it be included in the +-.. revision.
/.11 Shape and stress
The shape of the 8< is usually controlled through ow and warp measurements over the
process flow. This is critical for process monitoring but also for all aspects related to handling of
thin wafers in a manufacturing context. Currently there are a large number of metrology tools
capable to support these in!line measurements. 0arious techni%ues such as laser deflection#
capacity# chromatic and interferometer techni%ues# coherent gradient sensing /CLS1 are able to
give the shape of the 8<. "s it stands# the results strongly depend on the way the wafer is hold
and at some point can be impacted by gravity effect. Coherence between metrology
semiconductors suppliers need to be improved through S3MI standard recommendation. This
will allow comparable results between techni%ues.
The introduction of large scale TS0 in CMOS environment is also raising the %uestion of stress
induced by the TS0 themselves. Raman spectroscopy can measure stress distribution in the
Silicon around the TS0s using small spot but the techni%ue needs to move to longer wavelength
to get information from deep silicon. Off!line analysis such as MR) and 3S) techni%ues are
also implemented alternatives to get the strain measurement.
/.123D Metrology for Copper nail and -illars
,or future () interconnect technologies# such as stac&ing circuit bloc&s and () integrated
circuit# there is a need to control the height# diameter and coplanarity of the Copper pillars that
will connect the top and bottom of the stac&ed dices. This re%uest pretty much e%uivalent to
umps measurements in bac&end manufacturing plants becomes now also critical at the wafer
level for IC manufacturing.
There are a number of metrology tools capable to measure those parameters at a production
scale. Techni%ues such as laser triangulation or confocal interferometry are very well adapted.
Page 1) o6 #
'evertheless there is clearly a lac& of reference standard available to address deficiencies for ()
metrology.
6 Interconnect Metrology
'ew processes and structures continue to drive metrology research and development. <orous low 2 is moving into
manufacturing# and () Interconnect is being used in a great variety of implementations. Copper contact structures
were announced at &ey technical symposia. "ll areas of metrology including materials characteri$ation# in!line
measurements# and advanced e%uipment and process control are used for interconnect research# development# and
manufacturing. Reliability of new processes such as copper contacts is largely un&nown. "s it has been in the past#
reliability testing is a critical part of evaluating new processes.
Interconnects# including all of the IC structures necessary to connect from silicon to the boards and boxes of the
outside world# have become a potential performance roadbloc& for the continuation of the semiconductor industry
on the MooreEs 5aw curve. This roadbloc& has components in both technology and cost. The technology
components span the necessary transition from aluminum=SiO+ to Cu=low 2# as well as transitions to more radical
interconnect approaches beyond the metal=dielectric system. The anticipated high cost to fabricate alternatives to the
existing metal=dielectric interconnect system for global interconnects is a large roadbloc&. "mong the potential
technology and cost issues inherent in the switch from aluminum=SiO+ to Cu!low 2 are the significant challenges for
new metrology for process development# manufacturing validation# and process control. ,or example# in Cu!low 2 it
is desired to produce minimal thic&ness barriers between Cu and dielectrics. This has resulted in a need for
metrology for detailed characteri$ation of extremely thin layers and ?$ero thic&ness@ interfaces without the
undesirable effects occurring during destructive sample preparation. The anticipation of radical interconnect options#
such as optical interconnects# has led to new metrology issues such as the need to profile optical properties of very
narrow waveguides# and to be able to identify extremely small optical defects in such waveguide materials. Some of
the needed metrology problems have been solved with creative applications and advances of existing techni%ues and
some new techni%ues have been developed. *owever# some problems have been identified as particularly difficult#
and possibly not having solutions within the confines of currently envisioned metrology techni%ues.
Interconnect needs for metrology# as noted above# include continuing evolutionary advances in existing metrology
techni%ues# as well as the increasing need for novel metrology approaches for more radical interconnect structures.
The following sections will describe some of the needs and status of existing metrology techni%ues for copper and
low!& Interconnects. The preceding section focused on the needed advances for future directions in ()
interconnect. Refer to the 'nterconnect chapter.
6.1 C$<!'7 = M%(*!!I>*(I'N ISS$%S *ND M%("'!'01 N%%DS
6.1.1 Cu Metalli?ation Issues
Copper metalli$ation has been used for several generations. The latest advance in copper metalli$ation is the use of
copper contacts to the transistor replacing tungsten. 8ith each shrin&# the challenges of filling trenches and vias
must be faced again. "mong the most important of these is the need for precise control of electrochemical deposition
baths# and identification of very low!level impurities that may cause resistivity increases in electrochemically
deposited copper. 8e now &now that the reliability of copper metal interconnects is degraded by the effects of
electro and stress migration# and that the primary degradation modes are associated with surface diffusion of Cu
along the interfaces between the Cu and dielectrics and barriers. 0oids in metal lines and vias that occur during
processing have also been identified as significant yield loss initiators. 0oiding problems can show up after
deposition=CM<=anneal# or from agglomeration of micro!voids due to electro or stress migration. "nother significant
problem relating to voids is a need to be able to identify relatively small# isolated voids in large fields of patterned
Cu conductors. These isolated voids often do not show up as yield loss# but can be an incipient cause of later
reliability failures. These voids may be on the surface of the conductors# but are often buried within the conductor
pattern or in vias. "dditional issues with Cu metalli$ation arise from the use of thin barriers to isolate the Cu from
Page 20 o6 #
underlying dielectrics. These thin barriers raise significant needs for measurement capabilities of ultra!thin layers#
interface properties# and defects and materials structure on sidewalls in very narrow channels. The problems noted
above have all been found to be important for Cu metalli$ation at D- nm and above. "s the industry moves below D-
nm# it is expected that these issues will still be present# but that additional issues will arise. 8hile we do not &now
all of the new issues that will arise# several problems associated with our inability to extrapolate current techni%ues
to the very small geometries and the increasing importance of currently acceptable limitations of metrology for
future technology generations are already clear. "mong these future needs for Cu metalli$ation metrology is the
increasing importance of metrology for ultra!thin layersAespecially barriers on sidewalls. This need re%uires not
only the ability to establish physical properties and structure of these layers with thic&nesses B+ nm# but also to
identify and characteri$e defects in the films. "n additional problem area that is currently not extensively studied#
but that is expected to become increasingly important at smaller geometries is the interface between the Cu and the
barrier or dielectric. "s the Cu conductors become smaller# it is expected that interface scattering will cause
significant increases in resistivity of very narrow lines.
6.1.2 Cu Metalli?ation Metrology
Copper electroplating systems need %uantitative determination of the additives# byproducts# and inorganic contents
in the bath to maintain the desired properties in the electroplated copper film. <rocess monitoring re%uires in situ
measurements of additives# byproducts# and inorganic content that result from bath aging. " mass spectrometry
based method to real!time sample bath contents provides a new potential solution. Cyclic voltammetric stripping
/C0S1 is widely used to measure the combined effect of the additives and byproducts on the plating %uality. 5i%uid
Chromatography can be used to %uantitatively measure individual components or compounds that are
electrochemically inactive and volumetric analysis using titration methods can be used for the monitoring of
inorganics.
arrier layer metrology needs include measurement of thic&ness# spatial uniformity# defects# and adhesion. Inline
measurement for () structures continues to be a ma9or gap. Measurement of materials on sidewall of low 2 trenches
is made even more difficult by the roughness along the sidewall. There is some concern about the application of
statistical process control to very thin barrier layers. Interconnect technical re%uirements indicate that barrier layers
for future technology will be B+ nm thic&. <resently# a number of measurement methods are capable of measuring a
barrier layer under seed copper when the films are hori$ontal. These methods include acoustic methods# M!ray
reflectivity# and M!ray fluorescence. Some of these methods can be used on patterned wafers. Inline measurement of
crystallographic phase and crystallographic texture /grain orientation1 of copper=barrier films is now possible using
M!ray diffraction based methods. This technology is under evaluation for process monitoring# and the connection to
electrical properties and process yield is being investigated.
)etection of voids in copper lines is most useful after CM< and anneal processes. " metric for copper void content
has been proposed in the Interconnect Roadmap and in line metrology for copper voids is the sub9ect of much
development. *owever# these efforts are focusing on the detection of voids only and not on the statistical sampling
needed for process control. Many of the methods are based on detection of changes in the total volume of the copper
lines. The typical across!chip variation in the thic&ness of copper lines will mas& the amount of voiding that these
methods can observe. Interconnect structures# which involve many layers of widely varying thic&ness made from a
variety of material types# pose the most severe challenge to rapid# and spatially resolved multi!layer thic&ness
measurements.
Some measurements remain elusive. ,or example# measurement of barrier and seed copper film thic&ness on
sidewalls is not yet possible. Recently crystallographic texture measurements on sidewalls have been reported.
"dhesion strength measurements are still done using destructive methods. 3nd point detection for etch must be
developed for new etch stop materials for porous low 2. Other areas of metrological concern with the new materials
and architectures include in!film moisture content# film stoichiometry# mechanical strength=rigidity# local stress
/versus wafer stress1# and line resistivity /versus bul& resistivity1. In addition# calibration techni%ues and standards
need to be developed in parallel with metrology.
)evelopment of interconnect tools# processes# and pilot line fabrication all re%uire detailed characteri$ation of
patterned and unpatterned films. Currently# many of the inline measurements for interconnect structures are made on
simplified structures or monitor wafers and are often destructive. Small feature si$es including ultra!thin barrier
layers will continue to stretch current capabilities. Interconnect metrology development will continue to be
challenged by the need to provide physical measurements that correlate to electrical performance# yield# and
reliability. More efficient and cost!effective manufacturing metrology re%uires measurement on patterned wafers.
Page 21 o6 #
Metrology re%uirements for Interconnect are shown in Table M3T6 and the potential solutions are shown in ,igure
M3T6 below. The new measurement re%uirements for void detection in copper lines and &iller pores in low 2 appear
to be difficult or impossible to meet. The need is to have a rapid# inline observation of very small number of
voids=larger pores. The main challenge is the re%uirement that the information be a statistically significant
determination at the percentage specified in Table M3T6.
Table MET6 'nterconnect Metrology Technology ,e-uirements
6.2 !o5 = Dielectrics Issues *nd Metrology Needs
6.2.1 !o5 = Dielectric Issues
The move from SiO+ to other dielectrics to provide lower dielectric constants in interconnect structures is proving as
much# if not more# of a challenge to the semiconductor industry than the move from "l metalli$ation to Cu. "
significant part of the difficulties has come from the fact that low 2 materials available thus far have significantly
different physical and mechanical properties than the prior SiO+. "mong the primary differences are significantly
different mechanical properties# and the presence of pores in the material. The lower mechanical strength has
resulted in a new set of issues stemming from problems resulting from materials and processes used in bac& end
manufacturing showing up as problems at assembly and pac&aging. " significant part of the problem is that there is
no convenient and competent metrology tools and methodology to %ualify materials at the bac& end process stage for
assembly and pac&aging viability. " second ma9or issue has been identified with characteri$ation of porous
materials. "t the present time there are no metrology techni%ues and methodologies to identify anomalously large or
significantly connected pores /so called ?&iller pores@1 in otherwise smaller pored materials. There are also no
available metrology techni%ues to characteri$e the materials on the sidewalls of low 2 patterns for physical
properties# chemical structure# and electrical performance. This capability needs to be able to identify and %uantify
very thin layers on these sidewalls related to physical layers and damage due to processes such as pore sealing and
plasma etch. These features need to be %uantifiable both on continuous sidewall surfaces and into pores on porous
materials. The two issues noted above# along with the standard measurements associated with dielectrics: need to be
addressed for not only todayEs dielectrics# but also for those that will be used in the few nanometer generations of the
not too distant future.
6.2.2 !o5<= Metrology
Inline metrology for non!porous low!2 processes is accomplished using measurements of film thic&ness and post
CM< flatness. 'n situ sensors are widely used to control CM<. Metrology continues to be a critical part of research
and development of porous low!2 materials. The need for transition of some of the measurements used during
process development into volume manufacturing is a topic of debate. 3xamples include pore si$e distribution
measurement. <ore si$e distribution has been characteri$ed off!line by small angle neutron scattering# positron
annihilation# a combination of gas absorption and ellipsometry /ellipsometric poresimetry1# and small angle M!ray
scattering /S"MS1. S"MS and ellipsometric poresimetry can be used next to /at!line1 a manufacturing line. The need
for moving these methods into the fab is under evaluation. )etection of large# ?&iller#@ pores in patterned low 2 \has
been highlighted as a critical need for manufacturing metrology by the Interconnect Roadmap.
*igh!fre%uency measurement of low!2 materials and test structures has been developed up to V- L*$. This needs to
be extended to H.-- L*$ because +- L*$ cloc&s have rising and falling edges much above V- L*$. "s a result of
extensive evaluation# the interconnect community no longer considers this measurement a critical need in the near
term. 5ow!2 materials seem to have constant dielectric functions over the fre%uency range of interest /from . L*$
to .- L*$1.
Thinning of porous low 2 during chemical mechanical polishing technology must be controlled# and available
flatness metrology further developed for patterned porous low!2 wafers. Stylus profilers and scanned probe /atomic
force1 microscopes can provide local and global flatness information# but the throughput of these methods must be
improved. Standards organi$ations have developed /and continue to develop1 flatness tests that provide the
information re%uired for statistical process control that is useful for lithographic processing.
Interconnect specific C) measurement procedures must be further developed for control of etch processes. Sey gaps
include the ability to validate post etch clean effectiveness# sidewall damage layer and properties. Rapid () imaging
of trench and contact=via structures must provide profile shape including sidewall angle and bottom C). This is
Page 22 o6 #
beyond the capabilities of current inline C)!S3Ms. 3tch bias determination is difficult due to the lac& of ade%uate
precision for resist C) measurements. One potential solution is scatterometry# which provides information that is
averaged over many lines with good precision for M. levels# but this precision may degrade for higher metal levels.
,urthermore# scatterometry must be extended to contact and via structures. 3lectrical test structures continue to be
an important means of evaluating the R!C properties of patterned low!2 films.
Figure MET6 'nterconnect Metrology Potential $olutions DRAM 1"2 P#$%&De=elopme;t U;der?ay@ual8A9at8o;-Pre3
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;odeIn-situ >e;>or> 6or CMP a;dplatt8;g Cat7Stre>> metrologyOpt89al2 E3ray2 a;d a9ou>t89Alm t789D;e>>2 ;m
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9 M*(%"I*!S *ND C'N(*MIN*(I'N C@*"*C(%"I>*(I'N
The rapid introduction of new materials# reduced feature si$e# new device structures# and low!temperature
processing continues to challenge materials characteri$ation and contamination analysis re%uired for process
development and %uality control. Correlation of appropriate offline characteri$ation methods# with each other# and
with inline physical and electrical methods# is often necessary to allow accurate measurement of metrics critical to
manufactured device performance and reliability. Characteri$ation accuracy re%uirements continue towards tighter
error tolerances for information such as layer thic&ness or elemental concentration. Characteri$ation methods must
continue to be developed toward whole wafer measurement capability and clean room compatibility.
The declining thic&ness of films# moving into the sub!nanometer range# creates additional difficulties to currently
available optical and opto!acoustic technologies. Shorter wavelengths of light even into the M!ray range are
currently investigated to overcome the challenge of inline film thic&ness and composition detection. Complimentary
techni%ues are often re%uired for a complete understanding of process control# for example M!ray reflectometry can
be used to determine film thic&ness and density while 40 ellipsometry can determine thic&ness# optical index# and
band!gap.
Often# offline methods provide information that inline methods cannot. ,or example# transmission electron
microscopy /T3M1 and scanning T3M /ST3M1 can provide the highest spatial resolution or cross!sectional
characteri$ation of ultra!thin films and interfacial layers. ST3M systems e%uipped with M!ray detection and electron
energy loss spectroscopy /335S1 have provided new information about interface chemical bonding. *igh!
performance secondary ion mass spectroscopy /SIMS1# and its variant time!of!flight /TO,1 SIMS# provide
contamination analysis of surfaces and thin film stac&s. Lra$ing incidence M!ray reflectivity /MRR1 provides
measurement of film thic&ness and density# while gra$ing incidence M!ray diffraction provides information about the
crystalline texture of thin films. The importance of using diffuse scattering in addition to specular scattering during
MRR seems to be critical to building interfacial models from MRR that can be compared to interfacial models from
other methods such as T3M=ST3M# SIMS# and ion bac&scattering. ,ield emission "uger electron spectroscopy /,3!
"3S1 provides composition analysis of particulate contamination down to less than +- nm in si$e. Offline
characteri$ation of physical properties such as void content and si$e in porous low!2 insulators# film adhesion# and
mechanical properties# for example# is re%uired for evaluation of new materials. Many of these tools are now
available for full wafers up to (-- mm in diameter.
Continued development of T3M and ST3M imaging capability is re%uired. T3M=ST3M methods re%uire sample
preparation methods that can result in metrology artifacts if care is not ta&en. Choice of detection angle for annular
detectors employed in ST3M instruments allows imaging contrast to vary from incoherent imaging sensitive to
mass!thic&ness variations to coherent imaging sensitive to crystal orientation and strain. Several technologies are
being applied to materials and process development for critical areas such as high and low 2. 3lectron energy loss
spectroscopy /335S1 can achieve spatial resolution of atomic columns for oriented crystalline samples. 8ith this
greatly improved spatial resolution# 335S can be used to characteri$e interfacial regions such as that between high 2
dielectrics and the silicon substrate. ST3M with "nnular )ar& ,ield imaging and 335S are becoming routine in
manufacturing support labs# however spatial resolution in regular practice is often limited by real device samples
where amorphous and disordered interfaces increase probe interaction volumes beyond those afforded by channeling
along atomic columns in perfect crystals. ,urther routine site!specific sample preparation conducted by focused ion
Page 2 o6 #
beam generally produces samples in the .-- nm thic&ness range. ,or certain applications such as lithographic cross
section metrology of photoresist and gate side wall angle measurements# this is sufficient
+.
. More challenging
applications re%uire a thic&ness of below C- nm for optimal spatial resolution in imaging and analysis. Lreat
advances have been made using in situ argon beam thinning of samples
++
. "dvances in image reconstruction software
have also improved image resolution and thus interfacial imaging. Several improvements in T3M=ST3M technology
are now commercially available including lens aberration correction and monochromators for the electron beam.
Recent brea&throughs in aberration corrected scanning T3M loo& very promising and reveal details such as single
misplaced atoms in a 9unction. ,urther# via combined application with high!brightness electron sources# improved
resolution may be achieved at reduced incident beam acceleration potentials allowing T3M measurements below the
damage threshold energies that have plagued high resolution characteri$ation of fragile materials including carbon
nanotubes and graphene. "ll of these T3M=ST3M tool improvements put added constraints on improved sample
preparation: thinner samples and reduced surface!damage layers are re%uired.
Though at present itEs generally considered time!prohibitive# electron tomography# producing () models of device
structures# may play an increasingly important role in metrology. Tomography has less stringent sample preparation
conditions as surface damage regions may be removed from reconstructions and thic&er samples are generally
desired.
"dvances over traditional energy dispersive spectrometers /3)S1 and some wavelength dispersive spectrometers
can enable particle and defect analysis on S3Ms located in the clean room. 'ew M!ray detectors will allow
resolution of slight chemical shifts in M!ray pea&s providing chemical information such as local bonding
environments. <rototype microcalorimeter energy dispersive spectrometers /3)S1 and superconducting tunnel
9unction techni%ues have M!ray energy resolution capable of separating overlapping pea&s that cannot be resolved
with current generation lithium!drifted!silicon 3)S detectors. "lthough beta site systems have been tested#
unfortunately# these have not become widely available. These detectors can also be implemented in micro MR, /M!
ray fluorescence1 systems# using either an electron beam or a micro focus M!ray beam as excitation source. M<S /M!
ray photoelectron spectroscopy1 is now widely used as a means to determine thic&ness and composition of thin /up
to C- nm1 films.
8hile these and other offline characteri$ation tools provide critical information for implementing the Roadmap#
there are still many challenges. Characteri$ation of high!2 gate stac&s is difficult due to the length!scales for which
electrical properties are determined. ,or example chemical intermixing by reactions forming intermetallics or alloys
may be easily confused with physical roughness at an interface. Characteri$ation techni%ues which probe the local
atom!atom interactions including electron energy loss spectroscopy# M!ray absorption near edge structure
spectroscopies are often re%uired. In addition# as device features continue to shrin& and new non!planar MOS
devices are developed# the applicability of characteri$ing planar structures as representative of device features
becomes more %uestionable. ,urthermore# ongoing scaling ma&es the analysis of contamination in high aspect ratio
structures even more difficult.
The introduction of new materials will raise new challenges in contamination analysis# such as happened with
copper metalli$ation where the very real possibility of cross contamination has led to the need to measure bul&
copper contamination down to the order of .-
.-
atoms=cm
(
and surface copper contamination even in the edge
exclusion and bevel regions# all because of the high diffusivity properties of this deleterious metal. )evice shrin&ing
is also tending to lower the thermal budgets allowed for processing so that the behavior of metal contamination and
how to reduce its negative effects are changing the characteri$ation needs. ,or example# low!temperature processing
is changing which surface contamination elements# and at what levels# need to be controlled and therefore measured.
" &ey example is the role of surface calcium on very thin gate oxide integrity# and the difficult challenge of
measuring this surface element at the .-
K
atoms=cm
+
level. Traditional methods such as vapor phase decomposition
followed by IC<!MS can have day!to!day limitations at this level /71. In addition# low!temperature processing is
changing how metal contamination gettering is achieved# challenging the way to characteri$e material properties to
ensure proper gettering.
Metallic contamination has long been &nown to be a &ey detrimental factor to device yield# causing degradation of
electrical parameters li&e gate oxide brea&down voltage and bac&ground noise in Charge Coupled )evices /CC)1
for instance. *istorically# monitoring has been achieved in!line through the use of monitor wafers and a combination
of Total Reflectance M!Ray ,luorescence /TMR,1 and post anneal Surface <hoto 0oltage /S<01. 4nfortunately# with
the ever increasing sensitivity of new technologies to trace metal contaminants and the more stringent %uality
criteria imposed by certain applications# this type of control scheme often has limitations both in terms of sensitivity
Page 2# o6 #
and detection capabilities. " techni%ue li&e "utomated 0apor <hase )ecomposition = Ion Coupled <lasma Mass
Spectrometry /0<) =IC<!MS1 can be powerful in this context as ultimate detection limits can be reached /down to a
few .-6 at=cm+ for some species1. ,ull or semi!local wafer measurement can be performed and tool automation
enable insertion as a true monitoring tool in a production line. In addition bul& analysis can also be achieved through
the use of ade%uate chemistries which in combination with )5TS/)eep level trap states71 can offer a full range
analytical capability both in terms of identification and %uantification.
9.1 Materials and conta#ination in strain<)ased de4ices
The accelerated use of strained silicon without SOI has resulted in new metrology and characteri$ation re%uirements
earlier than predicted. Late oxide metrology becomes even more complex when strained Si channel structures are
used as the starting material instead of bul& Si or SOI wafers. Strained Si is either grown on thic& relaxed SiLe
buffer layers on bul& Si or on compliant substrates consisting of thin SiLe layers on SOI. In both cases# the
metrology of the starting material is crucial with a large number of parameters to be controlled; .1 thic&ness and Le
profile of the SiLe buffer# +1 thic&ness of the strained Si channel# (1 roughness of the Si=SiLe interface and the Si
surface# V1 magnitude and local variation of stress in the Si channel# C1 threading dislocation density in the Si
channel /high sensitivity of the measurement is needed# since the desirable dislocation density is very low /at B.-(!
.-Vcm!+11# 61 density of other defects# such as twins# dislocation pile!ups# or misfit dislocations# particularly at the
SiLe=Si channel interface# and J1 distribution of dopants in channel and buffer /particularly after thermal annealing1.
Several methods employing T3M=ST3M have been developed to measure and map strain distributions in strained!
channel devices. It has been noted that thinning of a T3M sample may allow relaxation of some of the strain# and
finite element modeling has been useful in understanding how strain may be relaxed during sample thinning#
however strain measurement by T3M=ST3M has had many successes. oth threading and misfit dislocations can be
measured by T3M# but the limited sample si$e area if often a problem for re%uired statistical analysis of dislocation
densities. "tomic force microscopy determines the surface roughness of the Si channel. Optical microscopy has been
successful for etch pit density /3<)1 measurements to determine the density of threading dislocations intercepting
the wafer surface. Clear prescriptions for 3<) are needed to select the etch depth. The meaning of lines and points
in the 3<) optical images need to be explained. M!ray topography is another techni%ue offering promise for defect
detection. The Le and dopant profiles can easily be measured with SIMS. " high sputtering rate is needed for thic&
SiLe buffers# while high depth resolution /possibly with a low!energy floating ion gun1 enables the analysis of the
thin Si channel and of the channel=buffer interface. Optical carrier excitation using a red photodiode directed at the
sputtering crater has been used to avoid SIMS charging artifacts: this is particularly important for strained Si over
SOI and for undoped layers.
4ni%ue properties associated with strained silicon are being addressed with a variety of metrology methods. Stress is
the force re%uired to create lattice strain which affects the electronic band structure to provide mobility enhancement
of electrons or holes. Raman spectroscopy can measure stress# while T3M and MR) measure strain. Raman
spectrometry measures the energy of the Si!Si vibration in the Si channel which depends on changes in stress.
*owever# the phonon deformation potential /describing the variation of the Si!Si phonon energy with stress1 is not
firmly established for thin Si channels. Such Raman measurements need to be performed using a 40 laser to avoid
penetration of the laser into the Si substrate. "t (+C nm wavelength# the entire Raman signal stems from the thin Si
channel# simplifying data analysis. ,or longer wavelengths# the Si!Si vibration in the SiLe buffer complicates the
signal. The energy of the Si!Si vibration in SiLe depends on alloy composition and stress# which complicates the
problem. Raman mapping yields the stress distribution across the wafer with a maximum resolution of about -.C Pm#
thus allowing prediction of transistor!to!transistor variations in mobility enhancement. It would be desirable to
improve this resolution# possibly using solid or li%uid immersion techni%ues. Micro!MR) is also applied to measure
the stress in small structures# but currently the analysis spot is in the CN.- micron range# ma&ing device analysis not
yet feasible. "nalysis of ellipsometry data for strained Si channels is complicated# since the dielectric function of Si
depends on the stress. This relationship /described by the pie$o!optical or elasto!optical tensors1 is %ualitatively
understood# but sufficiently accurate %uantitative data for fitting ellipsometry data of strained Si channels is lac&ing.
8hen only considering the 40 portion of the ellipsometry spectra# there is some hope in the capability to determine
the gate oxide thic&ness# at least for sufficiently smooth surfaces. ,or rougher surfaces# there is an additional source
of error# since surface roughness enters the ellipsometry analysis in a similar fashion as the native or gate oxide. ,or
accurate gate oxide metrology# the Si surface roughness should be an order of magnitude less than the gate oxide
thic&ness. This is satisfied for bul& Si starting materials# but may cause concerns for measurements on strained Si
Page 2, o6 #
channels. Confinement effects in the thin Si channel are not yet an issue in the visible and 40 portions of the
ellipsometry spectra. In principle# ellipsometry should not only be able to determine the Si channel thic&ness# but
also the Le content of the SiLe buffer underneath. In practice# however# the Le content determined from
ellipsometry data is much too low# possibly due to ignoring the strain effects on the Si dielectric function. On
pseudomorphic Si=SiLe heterostructures# ellipsometry is much more successful.
M!ray reflectivity is an attractive alternative to spectroscopic ellipsometry to determine strained Si channel thic&ness
since the refractive index for M!rays is very close to . and does not depend on the stress. ,or Si channel thic&nesses
of the order of .-N+- nm# a clear series of interference fringes /sometimes accompanied by an additional large!angle
pea& of un&nown origin1 is obtained. *owever# determining the Si channel thic&ness using commercial software
fitting pac&ages does not always yield the correct value /in comparison to T3M1. <ossibly# this is related to surface
roughness that is more difficult to handle for M!ray reflectivity than for spectroscopic ellipsometry because of the
smaller wavelength. 3xperimental concerns about M!ray instrument reliability and alignment are similar to that
described for measurements on high!2 gate dielectrics. *igh!resolution triple!axis M!ray diffraction has been used
successfully /using lab and synchrotron M!ray sources1 to determine the vertical Si lattice constant in the channel#
another measure for the stress in the structures.
" number of microscopy methods are in the research and development phase. These include the point pro9ection
microscope /electron holography1 and low!energy electron microscopy. 5ow!energy electron microscopy has been
used to study surface science for several years. The application of this method to materials characteri$ation and
possibly to inline metrology needs to be studied. " discussion of these methods is provided in the Microscopy
Section of the Metrology Roadmap.
One of the fi4e long<ter# difficult challenges for metrology is structural and elemental analysis at device
dimensions. ,ulfilling this need will re%uire developing materials characteri$ation methods that provide maps of
elemental or chemical distributions at an atomic scale in three dimensions. () "tom <robes and similar methods
hold promise of providing atom!by!atom maps for small /C-!.C- nm diameter1 needle shaped samples that may be
prepared by ,I lift!out techni%ues. 53"< technology needs further method and data analysis development# and
currently has difficulties in measuring non!conductive and heterogeneously!conductive structures with both
conducting and non!conducting features. One challenge will be obtaining near .--F detection of each element
during data ac%uisition. 3lectron tomography is a growing region of interest and is being pursued by both tilt!series
and focal series methods in both ST3M and T3M. "berration corrected T3M currently shows promise in this area as
smaller and more intense probes may allow increased resolution and signal to noise re%uired for tomographic
analysis.
Figure MET7 Materials an Conta!ination "otential #olutions DRAM 1"2 P#$%&De=elopme;t
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: Metrology for %#erging "esearch Materials and De4ices
This section covers the materials and device characteri$ation as well as inline measurement needs for emerging
materials and devices. /Refer to the 3merging Research )evices chapter1 Considerable progress has been made
since the last update to the ITRS. )ue to the great interest of the ITRS community in graphene# great advances have
proven that the atomic structure can be imaged and electrical properties tested for a variety of new devices. 8e
summari$e this below.
The 3merging Research Materials and )evices Roadmap lists the cross!cutting metrology needs as
follows;
Page 2. o6 #
Characteri$ation and Imaging of 'ano!Scale Structures and Composition
Metrology 'eeds for Interfaces and 3mbedded 'ano!Structures
Characteri$ation of 0acancies and )efects in 'ano!Scale Structures
8afer 5evel Mapping of <roperties of 'anoscale 3RM
Metrology 'eeds for Simultaneous Spin and 3lectrical Measurements
Metrology 'eeds for Complex Metal Oxide Systems
Metrology for Molecular )evices
Metrology 'eeds for Macromolecular Materials
Metrology 'eeds for )irected Self!"ssembly
Modeling and "nalysis of <robe!Sample Interactions
Metrology 'eeds for 4ltra!Scaled )evices
Metrology for 3RM 3nvironmental Safety and *ealth
This section of the Metrology Roadmap complements the Cross!cutting Metrology needs described in the 3RM
roadmap by describing the status and research needs for a number of &ey measurement methods. This section is
divided into sub!sections on () "tomic Imaging and Spectroscopy# Other Microscopy 'eeds including Scanned
<robe Microscopies# Optical <roperties of nanomaterials# and 3lectrical Characteri$ation for 3merging Materials
and )evices.
Update on 7dvances in 8raphene Metrology
" great number of researchers are wor&ing in the area of graphene materials# device# and metrology
development. Metrology has been a &ey enabler for determination of graphene properties. )evices based
on R, transistors and other eyond CMOS devices are being fabricated using cleanroom processing
methods. C0) processing provides a facile route to large area graphene. " number of &ey properties can
be routinely measured including layer number# the presence of voids /possibly missing grains1# and carrier
mobility. Research efforts have shown the effect of graphene proximity to substrates observing boron
nitride substrates increase the carrier mobility in graphene compared to that observed using SiO+=Si
substrates.(/) It is now widely recogni$ed that the properties of single layer graphene /S5L1 and few
layer graphene /,5L1 depend on sample cleanliness# the substrate that the graphene sits on# and the
stac&ing configuration of ,5L. The properties of bi!layer graphene depend on the stac&ing pattern and
the rotational orientation of the two layers. One of the &ey needs for graphene is determining the number
of layers across the sample. 5ow energy electron microscopy# Raman spectroscopy# and optical
microscopy /when low spatial resolution is re%uired1 have all been used to successfully determine the
number of layers. The rotational misorientation of bi!layer graphene can be determined using *R!T3M
and STM. 3lectron!hole puddles in single layer graphene /S5L1 have been observed using a single
electron microscope and attributed to charge inhomogeneities in the SiO+ layer below.(6) C0) graphene
grain si$e can routinely be measured using dar& field T3M.(9) This wor& illustrates the importance of the
properties of the substrate in the overall device properties.
Update on 7dvances in Memristor Metrology
Redox memory devices# such as memristors# provide a number of measurement challenges. ,or example#
the physical mechanisms involved in device operation are not well understood. Operation of the TiO+
based devices seems to involve formation of conducting nanofilaments within the TiO+ between metal
electrodes. Recently# transmission electron microscopy/D# .-1# synchrotron based scanning transmission
M!Ray microscopy /STMM1 /..1 with chemical analysis using near edge M!Ray absorption fine structure
/'3M",S1/.+1# and photoemission electron microscope /<33M1/.+1 have observed the formation of a
stable ?Magneli TiVOJ phase@ in the TiO+ dielectric. This characteri$ation is challenging and far from
Page 27 o6 #
routine. ,ilament characteri$ation also illustrates the difficulties involved in understanding new
materials.

Co##ent on the I#pact of Nanoscale Di#ensions on Metrology
One of most overloo&ed challenges in metrology is the need for nanoscale materials properties. The
materials properties used to measure process variation not only change at the nanoscale# but are
themselves altered by surrounding materials. These changes include optical properties /complex refractive
index1# carrier mobility# and numerous others. ,or example# the optical properties of the top layer of SOI
are thic&ness dependent below .- nm. ,urthermore# recent data have shown the optical properties depend
on layers deposited above the top SOI film. This dimensional and materials stac& dependence points to
the need for developing databases of these properties with entries for critical materials stac&s. In some
instances# it seems that both carrier and phonon confinement impacts numerous properties including
dielectric function /complex refractive index1# carrier mobility# and thermal transport.
:.1 3D *to#ic I#aging and Spectroscopy
7berration 2orrected TEM and $TEM w5E)$
"berration corrected lens technology has revolutioni$ed transmission and scanning transmission electron
microscopy. Commercially available T3M and ST3M systems have demonstrated sub -.. nm resolution
and electron energy loss spectra have located atoms in an atomic column. "berration corrected ST3M
systems are approaching () atomic resolution as increased convergence angles reduce the depth of focus.
This technology has already been applied to nanotechnology. Recently# single layer graphene has been
imaged along with defects in the stac&ing configuration of multilayer graphene.(13, 1) Some of the
achievements of aberration corrected electron microscopy of nanotechnology include;
Imaging of single layer graphene# layer corrugation# and defects.
35S spectra of a single Sr atom in an atomic column of CaTiO(
Imaging both S and I atoms of a SI crystal inside a carbon nanotube
Observation of the movement of atoms in nanodots
Observation of the relationship between the gold atoms in the nanodot gold catalyst and a silicon
nanowire.
"dvances in image and spectral modeling will enable the full potential of aberration correction and
associated advances such as energy filters for the electron source and higher energy resolution=electron
energy loss. Multi!slice simulations are already being modified for nano!dimensional materials and other
applications. These first simulations indicate that the observation of twinning defects in nanowires
re%uires the use of multiple angles of observation. The impact of nano!dimensions on electron diffraction
patterns is also interesting. Microscopy of carbon containing samples has moved beyond carbon
nanotubes into single layer graphene. )espite all of the above!mentioned advances# microscopy of soft
matter remains exceedingly difficult as bonds are more readily bro&en in molecular samples. *igher
energy resolution for 35S is critical to understanding molecular samples.
*3 7tom Probe
The () "tom <robe is an advanced version of a field ioni$ation microscope combined with a mass
spectrometer capable of atom!by!atom three dimensional reconstruction of a small needle!shaped sample.
The sample may be prepared from a device specific site by chemical or plasma etching# or focused ion
beam lift!out techni%ues similar to those commonly used for T3M sample preparation. In the () "tom
<robe experiment# a needle!shaped sample is placed in close proximity to an electrode and a strong
applied field ioni$es atoms from the sample tip# e9ecting atoms from the sample# and accelerating them
through a position sensitive mass spectrometer. The original position of atoms in the sample is determined
Page 2' o6 #
from geometric considerations and the atomic mass is determined from time of flight. () "tom <robe
provides a means of measuring the atomic arrangement of free standing wires allowing a method to
characteri$e doping density in nanowires. 'on!metallic samples have had difficulties but progress has
been made with the addition of laser pulsing. The () "tom <robe brings us closer to the dream of atomic
mapping in three dimensions. Current detection efficiency is approximately 6-F of the atoms ioni$ed and
there has been much progress in developing an understanding of local field effects that affect resultant ()
models.
*3 Tomography
"s the geometrical complexity of devices continues to increase# there is a growing need to extend the ()
capabilities of tomography techni%ues to sub!.nm resolutions. oth electron and x!ray tomography can
potentially be extended to sub!nm resolution. "s with any tomography techni%ue# such imaging re%uires
multiple images at many different angles. 3lectron tomography has already demonstrated atomic
resolution through the use of aberration corrected ST3Ms (1+). The potential for sub!nm x!ray
tomography with its simplified sample preparation re%uirements has also shown promise with the
advances in x!ray optics using Multilayer 5aue 5enses. (1/)
:.2 'ther Microscopy Needs including Scanning -ro)e Microscopy
7ssumptionAthere is a need for characteri$ing the structure and local properties of current CMOS
devices as they scale down in si$e# as well as for anticipating the metrology re%uirements of post CMOS
device technologies.
Probes of )ocal Properties with &igh $patial ,esolution/ (pportunities
Scanning <robe Microscopy /S<M1 is a platform upon which a variety of local structure=property tools
have been developed with spatial resolution spanning C- nm to -.. nm. Scanning Capacitance
Microscopy# Spreading Resistance Microscopy and Conductive Tip "tomic ,orce Microscopy have been
optimi$ed for dopant concentration profile measurement with spatial resolution dependent on dopant
concentration. Recent developments in S<M involving fre%uency dependent signals on the sample and
tip# and simultaneous perturbation with more than one fre%uency and=or probe expand the range and
resolution of measurements.
)ocal Measurements ,elated to 2harge and Transport# it is increasingly important to characteri$e
devices in situ and during operation# particularly as a function of fre%uency. Scanning Impedance
Microscopy and 'ano Impedance Spectroscopy span K orders of magnitude in fre%uency to %uantify
interface and defect properties# including charge trapping. Individual defects in molecular nanowires can
be detected with these tools# as well as# local contact potential. Scanning Surface <otential Microscopy
/also called Selvin ,orce Microscopy1 can easily map wor& function variations at the tens of nm scale
and can be exploited to characteri$e ,3T and interconnect structures. There is recent evidence that the
spatial resolution of this techni%ue can be extended to atomic scales. Surface potential variations on high!
& dielectric films can be characteri$ed providing insight on interface properties both before and after
metalli$ation with a high energy and spatial resolution. Recent S<M observations of %uantum dots
demonstrated single electron detection indicated the potential for increased energy resolution in highly
speciali$ed environments.
)ocal Measurements ,elated to $pin# " scanning probe tool# Magnetic Resonance ,orce Microscopy#
has recently demonstrated the detection of single spins with magnetic probes. ,urther development will
determine limitations on spatial resolution and the potential to study spin polari$ation and characteri$e
spin based devices. "t lower sensitivity# Magnetic ,orce Microscopy can be used to map current flow
Page 2) o6 #
through devices. To be generally useful the limits of field detection and development of standardi$ed
commercially available magnetic tips are re%uired.
2omple9 Properties#,uture generation devices will li&ely involve a wider materials set# perhaps
including organic and biomolecular constituents# and re%uire additional property measurements. 4tili$ing
high fre%uencies in various detection configurations yields local dielectric constant# electrostriction#
pie$o!electric coefficient# switching dynamics# etc. These measurements are critical in the development
of capacitor based memory and for hybrid device structures# as well as dielectric characteri$ation.
Multiple Modulation and 2ombined Probes#The combination of multiple measurements is sometimes
necessary to isolate properties and is sometimes useful to maximi$e information. ,or example
electrostatic interactions that occur during magnetic force measurements can be incapacitating. y
measuring surface potential at high fre%uency# nulling it# and measuring magnetic forces at low fre%uency#
the interactions are separated and %uantified. This approach can be applied to produce generali$ed
metrology tools.
Probes of )ocal Properties with &igh $patial ,esolution/ 2hallenges
The challenges are implementing these tools on increasingly miniaturi$ed active devices and complex
materials systems in an industrial environment and time scale.
8eneral 7ccessibility# The time it ta&es to bring a metrology capability from the lab development to
commerciali$ation results in a large gap between capability and accessibility. ,or some companies the
design timeline is on the order of 6 years. This is particularly critical now since device research is
encompassing new materials for high!& dielectrics# exploring alternative geometries# and loo&ing toward
post CMOS technologies. Other mechanisms of accessibility are necessary to meet roadmap
re%uirements.
'ncreased resolution# In the era of shrin&ing electronics# a trend toward higher spatial resolution is
desirable. ,or some S<M tools# fundamental principles will limit ultimate resolution. Other tools are so
new that limits have not been examined. Recent results in Scanning Selvin <robe Microscopy suggest
that atomic scale resolution is possible for some of the complex property probes./]aw wants a reference
here1 If so# new physics will emerge and theory will be re%uired to interpret the output. There is a
potential to increase the energy resolution of most of the measurements# as demonstrated by inelastic
tunneling and single electron detection. The maximum energy resolution will be achieved at low
temperature# which is a trade off with throughput and convenience.
Tip and 2antilever Technology#Commercial vendors have developed a large toolbox of speciali$ed S<M
cantilevers and tips. Reproducibility is often an issue: in some cases yields of good tips are on the order
of (-F. More important is the gap between commercially available cantilevers=tips and those re%uired
for tool development. This becomes more difficult as the tips envisioned for tool development involve
embedded circuitry and complex tip geometries.
2alibration $tandards#The lac& of calibration standards for nm si$ed physical structures is a significant
problem. "t high spatial resolution and under speciali$ed circumstances# atomic structure can be used.
Carbon nanotubes have been suggested as a general alternative and can be used for electrostatic property
calibration as well. Standard calibration processes should continue to be developed at the nanometer
length scale.
Page 0 o6 #
:.3 'ptical -roperties of Nano#aterials
The optical properties of nano!scale crystalline materials# especially semiconductors# are modified by
%uantum confinement and surface states. The fundamental expression of the optical response of a
material is its dielectric function. The imaginary part of the dielectric function is directly related to the
absorption of light. ,or both direct and indirect band gap materials# the optical response is characteri$ed
by critical points where electrons are excited from the top of a valence band to the conduction band.
Certain transitions have a strong excitonic nature. These transitions change as one moves from bul& to
thin film to nanowires and then nano!dots.
The symmetry of a bul& sample strongly influences both the band structure and the 9oint density of states.
^uantum confinement in one# two# or three dimensions changes the energy of the critical points and the
9oint density of states. Thus# the shape of imaginary part of the dielectric function of nano!si$ed materials
is altered by the change in the 9oint density of states and the appearance of new critical points due to the
confinement. One interesting example is the emergence of strong anisotropy in silicon nanowires less
than +.+ nm in diameter and the theoretical prediction of new absorption pea&s for light polari$ations
along the wire axis.(16) The nature of optical transitions with a strong excitonic nature are not well
understood# and further theoretical and experimental wor& is re%uired to understand the role of excitons in
nanoscale materials.
:. %lectrical Characteri?ation for %#erging Materials and De4ices
Many emerging nanoelectronic devices exhibit non!conventional behavior such as negative differential
resistance and hysteretic switching (19, 1:, 2;) 'ew electrical measurement methodologies and analyses
will be re%uired to characteri$e the behavior of these new emerging materials and devices. Certain
traditional parameters# such as mobility# are much more challenging to extract at the nanoscale.(21) It is
important to determine what parameters are determining final device performance for a given emerging
device technology. In addition# the behavior of some categories of emerging devices is based upon
completely different mechanisms than those in traditional CMOS. ,or example certain devices have
intrinsically %uantum mechanical behavior# while others do not utili$e charge transport to change the
computational state# but rely upon other mechanisms such as magnetic flux changes. Salient device
parameters and their extraction methods will need to be defined for such new devices that switch by
different physical principles than standard MOS,3T structures. Methodologies will need to be established
for characteri$ing the stability and reliability of new device structures and circuit architectures.
In addition to advances in electrical test methodologies# viable test structures are critically needed to
reliably and reproducibly measure nm!si$ed interfacial elements /such as individual molecules and nm!
si$ed semiconductor %uantum dots1 incorporating larger electrodes and leads that can be electrically
contacted by probes or wire bonds. Methods to contact sub!lithographic components of emerging
nanoelectronic devices are perhaps the greatest challenge for the electrical characteri$ation of emerging
materials and devices. ,urthermore# parametric test structures need to be developed that interrogate the
interface between metal interconnect and the active region of nano!scale devices# especially those
fabricated with organic materials. <arameters such as wor& function# barrier height# and transport
processes need to be investigated and defined for devices fabricated with unconventional materials.
1; "eference Materials
Reference materials are physical ob9ects with one or more well established properties typically used to
calibrate metrology instruments. Reference materials are a critical part of metrology since they establish a
?yard stic&@ for comparison of data ta&en by different methods# by similar instruments at different
locations /internally or externally1# or between the model and experiment. Reference materials are also
extremely useful in testing and benchmar&ing instrumentation.
Page 1 o6 #
There are two basic &inds of reference materials;
.1 " reference material can be a well!calibrated artifact that gives a reference point for the metrology
under test.
+1 "nother e%ually important reference material tests how accurately the tool under test measures a &ey
process control parameter. The most relevant reference materials are products that come from the
manufacturing process. The measurement tools under test /TuT1 are designed to measure a feature of a
given product such as linewidth accurately# for example. This product contains subtle# but important#
process changes that may affect measurement accuracy. It is the responsibility of the metrologist to
understand the important process variations that can be difficult to measure by the TuT and to incorporate
them into a meaningful set of test artifacts. These test artifacts must then be accurately measured with an
appropriately %ualified and documented reference measurement system.
Reference materials of the first &ind can be obtained from a variety of sources and come in a variety of
forms and grades. These types of standards are important and useful# but they tend to be limited in their
usefulness because of a limited li&eness to the customersE manufacturing process and the lac& of relevant
induced process variations. )epending on the source# they may be called Certified Reference Materials
/CRM1# Consensus Reference Materials# 'IST Traceable Reference Materials /'TRM[1 or Standard
Reference Materials /SRM[1.
.
The 4S 'ational Institute of Standards and Technology /'IST1 is one of
the internationally accepted national authorities of measurement science in the semiconductor industry.
Commercial suppliers can also create and submit calibration artifacts to a rigorous measurement program
at 'IST for the purpose of developing an 'TRM: reference material producers adhering to these
re%uirements are allowed to use the 'TRM trademar& for the series of artifacts chec&ed by 'IST.
+

"nother approach is the measurement certification of reference materials through interlaboratory testing
under the supervision of recogni$ed standards developing bodies# such as "STM International. The
'ational Metrology Institutions /'MI1 in different countries develop and maintain standards that might
be suitable and should be consulted. There is an effort among many of the leading 'MIs# including 'IST#
to coordinate cross comparisons of their measurements and standards to arrive at a mutual recognition
sometime in the near future to avoid duplication of efforts.
(

There are several technical re%uirements related to reference materials of the first &ind and their
measurement certification# as follows;
Reference materials must have properties that remain stable during use: both spatial and temporal variations in
the certified material properties must be much smaller than the desired calibration uncertainty.
Measurement and certification of reference materials must be carried out using standardi$ed or well!
documented test procedures. In some areas of metrology no current method of measurement is ade%uate for the
purpose. 8hen the basic measurement process has not been proven# reference materials cannot be produced.
The final measurement uncertainty in an industry measurement employing a reference material is a
combination of uncertainty in the certified value of the reference material and additional uncertainties
associated with comparing the reference material to the un&nown. ,or this reason# the uncertainty in the
reference material must be smaller than the desired uncertainty of the final measurement. "n industry rule of
thumb is that uncertainties in the certified value of the reference material be less than _ of the variability of the
manufacturing process to be evaluated or controlled by the instrument calibrated using the reference material.
,or applications where accurate measurements are re%uired /such as dopant profiling to provide inputs for
modeling1# the reference material attribute must be determined with an accuracy /including both bias and
variability1 better than _ of the re%uired final accuracy of the measurement for which it will be used.
.
:T,M; and $,M; acronyms are registered trademar!s of :'$T"
+
Use of the :T,M mar! on a subse-uent series of artifacts, even of the same type, re-uires additional verification testing by
:'$T"
(
,efer to The 'nternational <ureau of +eights and Measures= website http/55www"bipm"org5en5convention5mra5"
Page 2 o6 #
"dd8t8o;al tra8;8;g o6 pro9e>> e;g8;eer> 8; t7e Aeld o6 mea>ureme;t >98e;9e 8>
e>>e;t8al to a=o8d m8>u>e o6 re6ere;9e mater8al> a;d m8>8;terpretat8o; o6 t7e re>ult>
oCta8;ed ?8t7 t7e8r u>e.
11 "eference Measure#ent Syste#
" Reference Measurement System /RMS1 is an instrument# or a set of several instruments# that
complement each other in their ability to excel in various aspects of dimensional metrology. "n
RMS /this is a rather limited definition for RMS!dimensional metrology1 is well characteri$ed
using the best the science and technology of dimensional metrology can offer; applied physics#
sound statistics# related standards# and proper handling of all measurement error contributions
based on the best protocols available. ecause an RMS has been well characteri$ed# it is more
accurate# perhaps by an order of magnitude# and more precise than any instrument in a
production fab.
i
"n RMS must be sufficiently stable that other measurement systems can be
related to it. "n RMS can be used to trac& measurement discrepancies among the metrology
instruments of a fab# and to control the performance and matching of production metrology
instruments over time.
)ue to the performance and reliability expected from this instrument# the RMS re%uires a
significantly higher degree of care# scrutiny# and testing than other fab instruments. Through its
measurements this ?golden@ instrument can help production and reduce costs. *owever# this is
an instrument that# by the nature of the semiconductor process# must reside within the clean
environment of the fab so that wafers measured within this instrument can be allowed bac& into
the process stream. 8afers from any other fab can come for measurements and be returned to
serve as in!house references across the company or companies.
Page o6 #
i
.. unday# .# Cordes# ".# "llgair# `.# "guilar# ).# Tileli# 0.# Thiel# .# "vitan# ].# <eltinov# R.# ar!Xvi# M.# "dan# O.# >
Chir&o# S. ?3lectron!beam induced photoresist shrin&age influence on +) profiles@. Metrology# Inspection# and <rocess
Control for Microlithography MMI0. `. <roceedings of the S<I3# 0olume J6(K# pp. J6(K.5!J6(K.5!+. /+-.-1.
+. R. "ttota# R. L. )ixson# `. ". Sramar# `. 3. <ot$ic&# ". 3. 0ladar# . unday# 3. 'ova&# and ". Rudac&# TSOM Method
for Semiconductor Metrology# <roc. of S<I3 0ol. JDJ. JDJ.-T!..
(. 'andatech /this is not a complete reference1
V. ". 0aid# . ]an# ]. `iang# M. Selling# C. *artig# `. "llgair# <. 3bersbach# M. Sendelbach# '. Rana# ".
Satnani#3. Mclellan# C. "rchie# C. o$dog# *. Sim# M. Sendler# S. 'g# . Sherman# . rill# I. Turovets# R.
4rens&y# " holistic metrology approach; hybrid metrology utili$ing scatterometry# C)!",M# and C)!S3M#
<roc. of S<I3 0ol. JDJ.# JDJ.-(.
C. unday# .# Ri9pers# .# an&e# 8.# "rchie# C.# <eterson# I.# 4&raintsev# 0.# *ingst# T.# and "sano# M. ?Impact of
Sampling on 4ncertainty; Semiconductor )imensional Metrology "pplications#@ <roc. S<I3 6D++# 6D++!-M# pp -M!.
to -M!++# March# +--K.
6. C.R. )ean# ".,. ]oung# I. Meric# C. 5ee# 5. 8ang# S. Sorgenfrei# S. 8atanabe# T. Taniguchi# <. Sim# S.5. Shepard# `.
*one# oron nitride substrates for high %uality graphene electronics# :ature :anotechnology
J. +#
K. J++NJ+6#
D. /+-.-1.
J. `. Martin# '. "&erman# L. 4lbricht# T. 5ohmann# `. *. Smet# S. von Slit$ing > ". ]acoby# :ature Physics # .VV ! .VK
/+--K1.
K. <. ]. *uang# C. S. Rui$!0argas.# ". M. van der Xande# 8. S. 8hitney# S. Larg(# `. S. "lden# C. `. *ustedt# ]e Xhu# `.
<ar&# <. 5. Mc3uen# ). ". Muller# Lrains and grain boundaries in single!layer graphene atomic patchwor& %uilts,
'ature /:# /+-..1# (KDN(D+.
D. `.C. Meyer# C. Sisielows&i# R. 3rni# M.). Rossell# M. ,. Crommie# and ". Xettl# )irect Imaging of 5attice "toms and
Topological )efects in Lraphene Membranes# 'ano 5ett.9# /+--K1# (CK+N(CK6.
.-. `.*. 8arner# M.*. Rummeli# Thomas Lemming# . uchner# and L.". ). riggs# )irect Imaging of Rotational
Stac&ing ,aults in ,ew 5ayer Lraphene# 'ano 5etters D /+--D1# .-+ N .-6.
... *. 5. Min and ). ". Muller# "berration!corrected "),!ST3M depth sectioning and prospects for reliable ()
imaging in S=T3M# >ournal of Electron Microscopy CK/(1; .CJN.6C /+--D1.
.+. *anfei ]an# M!ray dynamical diffraction from multilayer 5aue lenses with rough interfaces# <hys. Rev. JD# .6CV.-
/+--D1.
.(. 5i ]ang# C. ). Spataru# S.L. 5ouie# and M. ]. Chou# 3nhanced electron!hole interaction and optical
absorption in a silicon nanowire# <hys.. Rev. JC# +-.(-VbR# /+--J1.
.V. `. Chen# M.". Reed# ".M. Rawlett# and `.M. Tour# Science# +K6# .CC-N.CC+ /.DDD1.
.C. C.<. Collier# L. Mattersteig# 3.8. 8ong# et al.# Science +KD# ..J+N..JC /+---1.
.6. Richter# C.".# ).R. Stewart# ).".". Ohlberg# R.S. 8illiams# "ppl. <hys. "# K-# .(CCN.(6+ /+--C1.
.J. S.!M. Soo# ".!,. ,u9uwara# `.!<. *an# 3. 0ogel# C. Richter# and `. onevich# 'ano 5ett.# 0ol. V# +.-JN+... /+--V1.

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Metrology roadmap July 27 2011

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