A 1.8V 1MS/s Rail-to-Rail 10-bit SAR ADC in 0.

18m CMOS
Saisundar. S
1
, Jia Hao Cheong
1
and Minkyu Je
1

1
Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)
11 Science Park Road, Singapore Science Park II, Singapore 117685
Email: sankas@ime.a-star.edu.sg

Abstract This paper presents a 10-bit, 1MS/s, rail-to-rail
successive approximation register analog-to-digital converter
(SAR ADC). The ADC uses a bootstrapped sampling switch
to achieve better linearity and also adopts a generalized non-
binary redundant algorithm and a rail-to-rail dynamic
latched comparator to obtain higher Effective Number of
Bits (ENOB). This ADC designed and fabricated in 0.18m
CMOS process achieves a signal-to-noise-and-distortion ratio
(SNDR) of 58.9dB at 1MS/s which corresponds to an ENOB
of 9.5. It also obtains a good linearity (DNL/INL) value of
less than 0.46LSB. At 1.8V supply, the ADC attains a Figure
of Merit (FOM) of 181fJ/conversion-step. The ADC also
consumes 34.6W from a 1.2V supply with an ENOB of 8.7
resulting in a FOM of 83fJ/conversion-step.
Index Terms SAR ADC, non-binary, redundant
algorithm, bootstrapped switch.
I. INTRODUCTION
Analog-to-digital converters (ADC) are indispensable in
applications such as wireless sensor networks, industrial
monitoring and data acquisition that convert the analog
signals to digital quantities for processing, transmission
and control. Technology scaling results in lower supply
voltage, smaller device dimensions, faster operation and
lower power. Designing ADCs with low supply voltage is
a challenging task because the threshold voltage of the
devices does not scale as fast as the supply voltage. A
direct consequence of reducing the supply voltage is the
reduction of input dynamic range. This necessitates the
input stage to be rail-to-rail to compensate for the reduced
input common-mode range and dynamic range.
The resolution of SAR ADCs is limited; because the
capacitor matching that can be realized in the process
severely affects the achievable ENOB. Algorithmic
techniques have helped in achieving a higher ENOB [1].
This paper presents a 1MS/s, rail-to-rail input range
SAR ADC for data acquisition applications. The ADC
uses the generalized non-binary redundant algorithm to
mitigate comparator errors and mismatch of capacitors to
obtain better ENOB. For better linearity and faster
settling at low supply voltages a bootstrapped sampling
switch is used. This ADC utilizes a rail-to-rail latched
comparator operating at high speed which has better
linearity than the time domain comparator used in [3].
II. ARCHITECTURE
The architecture of the SAR ADC is shown in Fig. 1.
The SAR ADC consists of 5 major building blocks
described in following subsections.
Fig. 1. Architecture of SAR ADC
A. Bootstrapped Sampling Switch
ADCs employ a sample and hold circuit in front end to
achieve high precision, linearity and dynamic range. A
transmission gate (TxGate) switch has a non-linear
variation of ON-Resistance (Ron) when compared to a
bootstrapped switch for the entire input range as shown in
Fig. 2.
Fig. 2. Variation of Ron with input voltage
This non-linear Ron will translate directly as an input
dependant distortion and affect the SNDR and linearity of
the ADC. Hence, the bootstrapped switch [5] shown in
Fig. 3 is used to sample the input. The sample and hold
function is performed by the same capacitor array. The
bootstrapped switch provides a good linearity by
maintaining a nearly constant Ron for the entire input
range. The switch is sized based on the settling time
required for the ADC.


83 978-1-4673-2305-5/12/$31.00 c 2012 IEEE
Fig. 3. Bootstrapped sampling switch
B. Capacitor Array with Redundant Algorithm
The unit capacitor in the capacitor array should be sized
such that the kT/C noise is lesser than quantization noise.
The kT/C noise limit on the minimum acceptable
capacitor size given by (1), where N is the resolution of
the ADC and Vfs is the full-scale voltage range shows that
the capacitor needs to be to be at least 16fF.
2 2
) /( ) 2 12 ( Vfs kT C
N
(1)
The relation between process variation () for the MIM
capacitor and the achievable ENOB is given by
) ( log
2
= ENOB (2)
Based on the process variation statistical data, the MIM
cap should be at least 400fF to attain an ENOB of 10.4.
Hence, the unit capacitor was sized more than 400fF with
margin for variations. The ENOB achievable by ADC is
limited by the capacitor matching, comparator errors and
incomplete DAC settling. To subside these errors the non-
binary redundant algorithm [1] is adopted to obtain a
higher ENOB. The step size is non-binary and the
algorithm introduces a redundant bit in the conversion and
provides error correction. The algorithm relaxes the
settling time of DAC [1] that can be expressed as
) / ln( q p me Settlingti = (3)
where, p is the step size voltage change and q is the
redundancy in that corresponding step and is the settling
time of the capacitor array. The optimum sizing obtained
by iterative simulation of the algorithm gave a settling
time of 2.3. Segmented capacitor array architecture is
used to reduce the MSB capacitor size without changing
the effective capacitor value. The attenuation capacitor
sizing can be obtained from [3].
C. Comparator
A rail-to-rail dynamic latched comparator [2] shown in
Fig. 4 is used in the design. The comparator has additional
switch transistors that reduce the static current
consumption during the reset state. The comparator is
sized such that it has a resolution of 11 bits and can
resolve the input in less than half a clock cycle. To
minimize comparator mismatch, the input devices were
kept large and the current mirror used long-length
transistors. The layout was done carefully utilizing the
common-centroid technique along with addition of
dummy devices and dummy routing to acquire good
matching.

Fig. 4. Rail-to-Rail dynamic latched comparator
D. Switching Array and Digital SAR Logic
The switching array was implemented using MOSFET
switches. The SAR logic generates the necessary timing,
control and sampling signals. Based on the decision of the
previous bit it switches the capacitor to either Vref_hi or
Vref_lo.
III. MEASUREMENT RESULTS
The prototype was fabricated using a one-poly-six-
metal (1P6M) 0.18m CMOS technology. The full chip
microphotograph and the zoomed-in view of the ADC
core with the bias generation are shown in Fig. 5. The
total area of the chip is 1.9mm x 1.9mm, with the ADC
core taking up only 950m x 250m.

Fig. 5. Microphotograph and the zoomed-in view of the ADC

The top plate routing parasitic capacitance affects the
linearity and offset of the ADC. To reduce this, sampling
switch and comparator were placed close to the capacitor
array. The layout of digital logic and the switch array were
placed symmetrical to the capacitor array. The Fig. 6
shows the static and dynamic performance of the ADC.
The measured differential non-linearity (DNL) and
integral non-linearity (INL) of the ADC are -0.4/+0.36
LSB and -0.46/+0.36LSB respectively and the peak
SNDR is 58.9dB.
Fig. 7 shows the signal-to-noise-and-distortion ratio
(SNDR), spurious-free dynamic range (SFDR) and ENOB
of the ADC as a function of normalized input frequency
(F
in
/F
s
) varied from DC to Nyquist frequency at 1MS/s.
The ENOB is 9.5 at low frequencies and drops to about
9.1 at Nyquist frequency with a 1.8V supply. With a 1.2V
84 2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
supply the ENOB is 8.7 at low frequencies and 8.3 at
Nyquist. The SAR ADC consumes 131W of power with
a 1.8V supply. The FOM (power/2
ENOB
*F
s
) of the ADC is
181fJ/conversion-step.

Fig. 6(a). DNL/INL plot of the ADC

Fig. 6(b). Spectral plot of the ADC output

Fig. 7(a). SNDR/SFDR as function of input frequency@1MS/s

Fig. 7(b). ENOB as a function of input frequency @1MS/s
The reference DAC consumes 57.7% of power while
the digital consumes 16.2% power and the analog circuits
consume the remaining. With a 1.2V supply and 0.6V
input swing the ADC consumes 34.6W resulting in an
FOM of 83fJ/conv-step. The high power consumption
from the reference supplies can be reduced by adopting
techniques such as triple-level switching [3] or by
reducing the reference voltages for low swing, low data-
rate applications.
IV. CONCLUSION
A 10-bit, 1MS/s SAR ADC has been designed and
fabricated in 0.18m technology .The ADC occupies an
active area of 0.2375mm
2
and the use of bootstrapped
switch aids to obtain a good linearity of less than
0.46LSB. The redundant algorithm also helps to attain a
good ENOB of 9.5 with a FOM of 181fJ/conversion-step.
It also achieves an ENOB of 8.7 and a FOM of
83fJ/conversion-step with a 1.2V supply. The
performance summary is presented in Table I and the
comparison with recently published SAR ADCs is shown
in Table II.

REFERENCES
[1] T. Ogawa et al., An SAR ADC algorithm with redundancy
and digital error correction, The 22nd Workshop on
Circuits and Systems, 2009, pp. 66-71.
[2] H.C. Hong and G.M. Lee, A 65-fJ/conversion-step 0.9-V
200-kS/s rail-to-rail 8-bit successive approximation ADC,
IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp.
2161-2168, October 2007.
[3] J.H. Cheong et al., A 400-nW 19.5-fJ/Conversion-Step 8-
ENOB 80-kS/s SAR ADC in 0.18m CMOS, IEEE
Transactions on Circuits and systems II, vol.58, no. 7, pp.
407-411, July 2011.
[4] C.C.Liu et al., A 10-bit 50-MS/s SAR ADC With a
Monotonic Capacitor Switching Procedure, IEEE Journal
of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April
2010.
[5] A. M. Abo and P. R. Gray, A 1.5-V, 10-bit, 14.3-MS/s
CMOS pipeline analog-to-digital converter, IEEE Journal
of Solid-State Circuits, vol. 34, no.5, pp. 599-606, May
1999.
[6] G.Y. Huang, C.C. Liu, Y.-Z. Lin, and S.J. Chang, A 10-bit
12-MS/s successive approximation ADC with 1.2-pF input
capacitance, in IEEE ASSCC Dig. Tech. Papers, pp. 157-
160, November 2009.
TABLE I
PERFORMANCE SUMMARY@1MS/S
Supply voltage(V) 1.8 1.2
Input swing(V) 1.8 0.6
SNDR (dB) 58.9 54.1
SFDR (dB) 70 70
ENOB (bits) 9.5 8.7
Analog/Digital/Reference
power(W)
34.2/21.2/75.6 12.2/7.6/14.8
Total power(W) 131.0 34.6
TABLE II
COMPARISON WITH OTHER SAR ADC DESIGNS
[2] [3] [4] [6] This Work
Technology(m) 0.18 0.18 0.13 0.13 0.18
Supply voltage(V) 1 1 1.2 1.2 1.2 1.8
Sampling speed
(MS/s)
0.4 0.08 50 12 1
Resolution(bits) 8 10 10 10 10
DNL(LSB) 0.9 0.7 0.91 1.27 0.4
INL(LSB) 0.53 1.5 1.36 2.97 0.46
ENOB(bits) 7.31 8 9.18 8.16 8.7 9.5
Power(W) 6.15 0.4 826 320 34.6 131
FOM(fJ/conv-step) 97 19.5 29 95 83 181
2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) 85