Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP

Lab 3: Comparator and 7 Segment Decoder

4
LAB: 03
TITLE: COMPARATOR AND 7 SEGMENT DECODER


Learning Outcomes: At the end of this lab, student able to

1. Design sequential magnitude comparator
2. Design BCD to seven segment decoder

Laboratory Equipment:

1. Labsheet
2. Computer
3. Altera Maxplus II


Theory:

Sequential Magnitude Comparator

Digital or Binary Comparators are made up from standard AND, NOR and
NOT gates that compare the digital signals present at their input terminals and
produce an output depending upon the condition of those inputs. For example,
along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller
than or equal to the value at input B.
(1)


The digital comparator accomplishes this using several logic gates that
operate on the principles of Boolean algebra. There are two main types of digital
comparator.

Identity Comparator is a digital comparator that has only one output
terminal for when A = B either "HIGH" A = B = 1 or "LOW" A = B = 0

Magnitude Comparator is a type of digital comparator that has three output
terminals, one each for equality, A = B greater than, A > B and less than A < B
The purpose of a Digital Comparator is to compare a set of variables or
unknown numbers, for example A (A
1
, A
2
, A
3
, .... A
n
) against that of a constant or
Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 3: Comparator and 7 Segment Decoder
4
unknown value such as B (B
1
, B
2
, B
3
, .... B
n
) and produce an output condition or
flag depending upon the result of the comparison.

For example, a magnitude comparator of 1-bit, A and B inputs would
produce the following three output conditions when compared to each other.

A > B , A = B , A < B

This is useful if we want to compare two variables and want to produce an
output when any of the above three conditions are achieved. Figure 1 show the
simple 1-bit comparator.


Figure1: 1-bit Comparator

The operation of a 1-bit digital comparator is given in the Table 1.

Table 1: 1-bit Comparator Truth Table
Input Output
B A A > B A = B A < B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

Digital comparators actually use Exclusive-NOR gates within their design
for comparing their respective pairs of bits. When we are comparing two binary or
BCD values or variables against each other, we are comparing the "magnitude" of
Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 3: Comparator and 7 Segment Decoder
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these values, a logic "0" against a logic "1" which is where the term Magnitude
Comparator comes from.

Multi-bit comparators can be constructed to compare whole binary or BCD
words to produce an output if one word is larger, equal to or less than the other. A
very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit
words are compared to each other to produce the relevant output with one word
connected to inputs A and the other to be compared against connected to input B
as shown in Figure 2.

Figure 2: 4-bit Magnitude Comparator

Seven Segment Decoder

A seven-segment display is often used on computers, watches, DVD
players and many electronic devices to display numbers and some characters. It
consists of seven independent lights, actually light-emitting diodes (LEDs), in an
8 configuration as shown in Figure 3. By turning on different segments, you can
display different numbers and some letters.
(2)



Figure 3: Number Display On 7 Segment

Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 3: Comparator and 7 Segment Decoder
4
Binary-coded-decimal (BCD) is a common way of encoding decimal
numbers with 4 binary bits as shown (Table 1):

Table 2: Decimal to BCD digit number
Decimal
number
0 1 2 3 4 5 6 7 8 9
BCD
Digit
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

Decoder is needed to change the BCD number to display in seven segment. For
an example number 0 will display segment a,b,c,d,e and f.


Figure 4: Segment of 7 segments

Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 3: Comparator and 7 Segment Decoder
4
Procedure:

Part A1 Designing 1-bit Sequential Magnitude Comparator

1. You need to design 1-bit comparator which have three output A>B, A=B
and A<B.

2. Complete the comparator truth table below.

1-bit
Input
Output
C D E
A B A > B A = B A < B
0 0
0 1
1 0
1 1

3. Based on the truth table, produce the comparator output equation.










4. Draw a logical schematic comparator and save as 1comparator.gdf

5. Execute the comparator with the possible input and compare the answer
with the truth table













C =
D =
E =
Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 3: Comparator and 7 Segment Decoder
4
Part A2 Designing 2-bit Sequential Magnitude Comparator

1. Construct the 2-bit comparator truth table.

2-bit Input
Output
C D E
A
2
A
1
B
2
B
1
A > B A = B A < B









2. Based on the truth table, produce the 2-bit comparator output equation.










3. Draw a logical schematic comparator and save as 2comparator.gdf

4. Execute the comparator with the possible input and compare the answer
with the truth table.














C =
D =
E =
Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 3: Comparator and 7 Segment Decoder
4
PART B Design BCD to seven segment decoder

1. Based on table 2 and figure 4, complete the BCD to 7 segment decoder
truth table (Table 6).

2. Note that the truth-table corresponds to a seven-segment device whose
display elements are active low. That is, each element will be active when
its corresponding input is '0'.

Table 6: BCD to 7 segment decoder truth table



















3. Based on the truth table, construct Karnaugh Map to simplify the equation
for each output:














4. Draw the logical schematic based on the equations above

BCD Seven segment
A
3
A
2
A
1
A
0
a b c d e f g










b =
a =
c =
d =
e =
f =
Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 3: Comparator and 7 Segment Decoder
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5. Save file as 7seg_decoder.gdf and create a symbol.

6. Generate the related waveform and execute into the decoder.

7. Make sure you get the correct output.



Question:

1. What is the function of sequential magnitude comparator?

2. Explain the differences between 1-bit comparator and 2-bit comparator

3. How to display letter A on the 7-segment?

4. Explain what is meant by active-low signaling. Why do you think active-low
signaling is used?

5. Explain how the seven segments can be used to display Hexadecimal
number?



Conclusion:

Write a conclusion on all labs you have made
















Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 3: Comparator and 7 Segment Decoder
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Resources

1. ______http://www.electronics-tutorials.ws/combination/comb_8.html; Basic
Electronics Tutorials by Wayne Storr. Last updated: June 2011

2. ______http://www.ece.mtu.edu/labs/EElabs/EE2304/EE2304_website_200
8/week_4_bcd_to_seven_segment.html; Department of Electrical and
Computer Engineering, Michigan Technological University, Last updated
2/15/01,Timothy J. Schulz