Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP

Lab 4: Adder Component in Arithmetic Logic Unit

4
LAB: 04
TITLE: ADDER COMPONENT IN ARITHMETIC LOGIC UNIT


Learning Outcomes: At the end of this lab, student be able to

1. Design binary Half Adder and Full Adder using Boolean Algebra
2. Manipulate Full Adder gate level to create a Parallel Binary Adder
3. Modify the Parallel Binary Adder to do Addition and Subtraction in a parallel
arithmetic element
4. Explain operation a Binary Coded Decimal Adder using Full Binary Adder
and Half Binary Adder block


Laboratory Equipment:

1. Labsheet
2. Computer
3. Altera Maxplus II


Theory:

Adder: Half and Full Adder

The adder is a major component of an Arithmetic Logic Unit (ALU) of a
CPU. A half adder adds two bits and produces a sum bit and a carry bit. A full
adder is constructed using two half adders, and it adds three input bits to produce
a sum bit and a carry bit.

An n-bit binary adder can be created by cascading full adders. Full adders
are cascaded by connecting the carry output of one adder to the carry input of the
next. A brief description of a half adder and a full adder is given below.

A half adder is a logical circuit that performs an addition operation on two
binary digits. The half adder produces a sum and a carry value which are both
binary digits. The Boolean logic for a half adder is as follows.

S = A XOR B
C = A AND B
Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4

Figure 1 show the block diagram of a half adder is shown below.

Figure 1: Half Adder block diagram
A full adder is a logical circuit that performs an addition operation on three
binary digits. The full adder produces a sum and a carry value, which are both
binary digits. The Boolean logic for a half adder is as follows.

S = (A xor B) xor Ci
Co = (A and B) or (Ci and (A xor B)) = (A and B) or (B and Ci) or (Ci and A)

The block diagram of a full adder is shown below.

Figure 2: Half Adder block diagram
Parallel Adders

An n-bit adder may be constructed by cascading n 1-bit address. Sum will
be delayed with respect to CARRY. In the case of an n-bit parallel adder, the carry
delay. Parallel adders are digital circuits that compute the addition of variable
binary strings of equivalent or different size in parallel.


The schematic diagram of a parallel adder is shown in Figure 3.
Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
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Figure 3: Parallel Adder block diagram

Ripple-Carry adder

The Ripple Carry Adder (RCA) is constructed by cascading full adders (FA)
blocks in series. One full adder is responsible for the addition of two binary digits at
any stage of the ripple carry. The carryout of one stage is fed directly to the carry-
in of the next stage.

A number of full adders may be added to the ripple carry adder or ripple
carry adders of different sizes may be cascaded in order to accommodate binary
vector strings of larger sizes.

For an n-bit parallel adder, it requires n computational elements (FA). The
carry out is then transmitted to the carry in of the next higher-order bit. The final
result creates a sum of four bits plus a carry out (c
4
).

Figure 4: Parallel Adder: 4-bit Ripple-Carry Adder Block Diagram
Even though this is a simple adder and can be used to add unrestricted bit
length numbers, it is however not very efficient when large bit numbers are used.
Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4
One of the most serious drawbacks of this adder is that the delay increases
linearly with the bit length.

Each full adder has to wait for the carry out of the previous stage to output
steady-state result. Therefore even if the adder has a value at its output terminal, it
has to wait for the propagation of the carry before the output reaches a correct
value.

An example, the addition of x
4
and y
4
cannot reach steady state until c
4

becomes available (Figure 4). In turn, c
4
has to wait for c
3
, and so on down to c
1
.
The delay of ripple carry adder is linearly proportional to n, the number of bits,
therefore the performance of the RCA is limited when n grows bigger. The
advantages of the RCA are lower power consumption as well as a compact
layout giving smaller chip area.

A twos complement subtraction circuit

An adder also can be modifying to subtraction circuit. However, it has to
use twos complement method. As we know,

A - B = A + (-B)

So to subtract B from A, we can instead add the negation of B to A. To find A - B
with an adder, well need to 1s complement each bit of B, then set the adders
carry in to 1. The net result is A + B + 1, where B + 1 is the 2s complement
negation of B.

The only differences between the adder and subtractor circuits are the
subtractor has to negate B
3
B
2
B
1
B
0
. The subtractor sets the initial carry in to 1,
instead of 0. XOR gates let us selectively complement the B input.

Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4
When Sub = 0, the XOR gates output B
3
B
2
B
1
B
0
and the carry in is 0. The
adder output will be A + B + 0, or just A + B.
When Sub = 1, the XOR gates output B
3
B
2
B
1
B
0
and the carry in is 1.
Thus, the adder output will be a twos complement subtraction, A - B.

Logical Unit

The logical unit is simply a collection of three boolean operations, AB, A+B,
NOT B. As with the full adder, each of their outputs is AND with the corresponding
enable line. On the very right, all of the outputs are OR together. However, only
one of the four inputs could potentially be a 1 because of the enable lines.


Figure 5: 1-bit Logical Unit

Figure 5 only represents a 1-bit ALU. Most likely, an 8-bit ALU is more convenient
for useful operations. To create an 8-bit ALU, this diagram needs to be repeated 8
times, linking the Carry-Out to the Carry-In of the next one each time.




Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4
Procedure:

Part A Designing Half Adder and Full Adder

1. Based on the Half Adder and Full Adder Boolean Algebra below design a
logic schematic.

Half Adder: Sum: S
h
= AB + AB
Carry: C = AB

Full Adder: Sum: S
f
= ABC
in
+ ABC
in
+ ABC
in
+ ABC
in

Carry: C
out
= AB + AC
in
+ BC
in


2. Create symbol for each logical schematic and named as HalfAdder.gdf
and FullAdder.gdf

3. Generate every possible input using waveform editor

4. Complete the Half Adder and Full Adder truth table

Table 1: Half Adder
a b c s
h






Table 2 : Full Adder
a b c
in
c
out
s
















Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4
Part B : Create a n-Bit Parallel Adder Using Full Adder

1. Using the Full Adder symbol your have created on Part A, create 4 Bit-
Parallel Adder.

2. Figure 6 shows the schematic logic diagram for 4 Bit Parallel Adder


Figure 6

3. Save the file as 4bitFA.gdf.

4. Complete the table below by changing the decimal number input A and B
to binary number

Table 3: 4-bit parallel adder input and output data.
Operation
A + B
4-bit input A 4-bit input B 4bit output with carry
A
4
A
3
A
2
A
1
B
4
B
3
B
2
B
1
C
5
S
4
S
3
S
2
S
1

2 + 3 0 0 1 0 0 0 1 1
7 + 9
12 + 8
15 + 7
13 + 10

5. Generate waveform signal for data input A and B to execute in the 4 bit
parallel adder.

6. Based on the output waveform, complete table 3.

7. Check the answer does the 4-bit parallel adder give the correct answer.







Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4
Part C: Modify Parallel Binary Adder for Addition and Subtraction

1. Using the 4-bit parallel adder you have made in part D, modify the
schematic logic circuit to do addition and subtraction.

2. Save your design and create symbol as AU.gdf

3. Figure 7 shows the schematic logic for adder and subtractor.


Figure 7

4. The 4-bit parallel adder can be modified to work as 4-bit parallel adder /
subtractor b including 4 exclusive-OR gates to provide the 1's complement
of B and adding 1 from the M input to make it the 2's complement.

5. Complete table 4 with the appropriate value.

Table 4: 4-bit parallel adder/subtractor input/output data.
Operation

4-bit input A 4-bit input B 1s complement 4-bit output with carry
A - B
A
4
A
3
A
2
A
1
B
4
B
3
B
2
B
1
B
4
B
3
B
2
B
1
M C
5
S
4
S
3
S
2
S
1

8 + 10

9 + 7

5 3

6 2

14 9

15 11


Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4
6. Generate waveform signal for data input A and B to execute in the 4 bit
parallel adder/subtractor

7. M bit must be set to 0 for addition and 1 for subtraction

8. Based on the output waveform, complete table 4.

9. Check the answer does the 4-bit parallel adder/subtractor operation give
the correct answer.




































Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4
Part D: Designing Logical Unit

1. Design 4-bit logical unit that can perform the logical operation:
a. A AND B
b. A OR B
c. NOT B

2. Figure 8 show the 1-bit logical unit, modify the logic schematic to create 4-
bit logical unit


Figure 8

3. The operation of Logical Unit is based on the pin selection. Refer to table 5

Table 5
Pin selection
Operation
S
1
S
2
S
3

1 0 0 A AND B
0 1 0 A OR B
0 0 1 NOT B

4. Save your design and create symbol as LU.gdf

5. Generate waveform signal to execute on the logical unit based on data
input in table 6

6. Check the answer does the 4-bit logical unit operation give the correct
answer.









Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
4
Table 6: 4-bit Logical Unit Truth Table

Operation
Input
Hexadecimal
number
Pin
selection
4-bit data Input A 4-bit data Input B 4-bit data output Z
A B S
1
S
2
S
3
A
3
A
2
A
1
A
0
B
3
B
2
B
1
B
0
Z
3
Z
2
Z
1
Z
0

AND 4 9

OR 4 9

NOT 4 9

AND E 6

OR E 6

NOT E 6




Question:

1. Explain the operation of BCD Adder using Full Binary Adder and Half
Binary Adder

2. What is the purpose of Parallel Adder?

3. What is the differences between of Parallel Adder and Parallel
Adder/Subtractor logical schematic?

4. What is the function of XOR gate in Parallel Adder/Subtractor logical
schematic?

5. By using the same 1-bit logical unit in Part D, can we create a 8-bit logical
unit?


Conclusion:

Write a conclusion on all labs you have made







Computer Architecture and Organicationy [EC303], Department of Electrical Engineering, PSP
Lab 4: Adder Component in Arithmetic Logic Unit
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Resources:

1. ______http://users.encs.concordia.ca/~asim/COEN_6501/Lecture_Notes/L
2_Notes.pdf

2. ______http://www.cs.uiuc.edu/class/fa05/cs231/lectures/10-Subtraction-
6up.pdf

3. ______http://library.thinkquest.org/25111/alu.shtml