Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 2: Counter
LAB: 2

TITLE: Counter


Learning Outcomes:

At the end of the practical, student able to:
i. Explain binary counter operation using JK Flip-flop.
ii. Design a 3-bit sequence counter.

Laboratory Equipment:

i. Computer
ii. Software Altera Max Plus II

Theory:
Counter can be developed by cascading the flip-flop. It has been categorized into two,
asynchronous and synchronous counter. We can define the asynchronous counter as a counter
where the flip-flop is triggered from external clock and the subsequent flip-flop clock is triggered
by the output Q from previous flip-flop. This counter is also known as a ripple counter. Figure 1
below is an example of logic schematic for asynchronous counter.



Figure 1: 2-bit asynchronous forward counter

Table 1 below summarized the flip-flop schematic connection for forward or backward
counter.

Table 1
Connection
between
CLK
CLK
Q Count down Count up
Q Count up Count down



Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 2: Counter
In asynchronous counter, the more the flip-flop been used in the circuit, it will add more
propagation delay to the output. A synchronous circuit can be use to solve this problem where
all the flip-flop in the schematic receives the clock pulses at the same time. Besides counting
forward and backward, this counter can be designed to count randomly.

Figure 2: 2-bit synchronous forward counter

Procedure:

Part A: Binary Counter Using JK Flip-flop


Figure 3: 2-bit asynchronous counter

1. Based on Figure 3, redesign the schematic using IC 74112 (in Altera MaxPlusII library)
into graphic editor.
2. Save the schematic as JKcounter.gdf
3. Test and generate the waveform for JK counter.
4. Prove that the designed circuit is counting upward.



Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 2: Counter
Part B: Design 3-bit sequence counter

Design a counter based on specification below:
3-bit counter
Using JK flip-flop
Counting upward
Counts on every negative edge triggered

1. Calculate the numbers of flip-flop that will be used in the schematic design using below
formula.








2. Fill in the next state diagram.
















3. Complete the excitation table based on Table 2 given below.

Table 2
Q
n
Q
n+1
J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

2
n
-1 = M ; M = largest number in list




n =

Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 2: Counter
Table 3: Excitation table
Q
n
Q
n+1
Output
A B C A B C J
A
K
A
J
B
K
B
J
C
K
C










4. Draw six Karnaugh Maps (K-Map) for each output.


5. From the K-Map, simplify the Boolean equation.











J
A
=
K
A
=
J
B
=
K
B
=
J
C
=
K
C
=

Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 2: Counter
6. Based on the derived Boolean equation above, draw a synchronous counter in Figure 4.


Figure 4

7. Redesign the schematic in Figure 4 into graphic editor using IC 74112.
8. Save the schematic as 3counter.gdf
9. Test and generate the timing diagram for the counter.
10. Group the output nodes as below Figure 5.


Figure 5: Timing diagram for 3-bit counter



Architecture Computer & Organization[EC303], Department of Electrical Engineering, PSP

Lab 2: Counter
Question:

Asynchronous Counter
i. Design a 2-bit asynchronous backward counter.
ii. Prove the circuit counts downward using waveform editor.

Synchronous Counter
i. Design a 3-bit backward counter (positive edge triggered).
ii. Prove the circuit counts downward using waveform editor.



Conclusion :

Your conclusion should be related to your practical and theoretical understanding on the related
topic. (not less than one page of explanation)