An Efficient Bit Reduction Binary Multiplication

Algorithm using Vedic Methods

M.E.Paramasivam, Dr.R.S.Saeenian,
!ecturer " E#E $ Research Memer " S%&A S'PR%, Assistant Professor " E#E $ #entre (ead " S%&A S'PR%,
Advanced Research #entre, Sona #ollege of )echnology, Advanced Research #entre, Sona #ollege of )echnology,
Salem, )amil &adu, '&D'A. Salem, )amil &adu, '&D'A.
*sivam+sonatech.ac.in saeenian+sonatech.ac.in
AbstractAn efficient technique for multiplying two binary
numbers using limited power and time is presented in this paper.
The work mainly focuses on speed of the multiplication operation
of multipliers, by reducing the number of bits to be multiplied. The
framework of the proposed algorithm is taken from Mathematical
algorithms given in Vedas and is further optimied by use of some
general arithmetic operations such as e!pansion and bit"shifting.
The proposed algorithm was modeled using Verilog, a hardware
description language. #t was found that under a given $.$ V supply
voltage, the designed % bit multiplier dissipates a power of %&.$'
m(. The propagation time of the proposed architecture was found
to ).)$ns
Keywords-Multipliers; Vedic Mathematics; bit reduction; binary
multiplication
9. '&)R%D,#)'%&
Multipliers have an important effect in designing arithmetic,
signal and image processors. Many mandatory functions in such
processors ma-e use of multipliers .for e/ample, the asic
uilding loc-s in 0ast 0ourier transforms .00)s1 and multiply
accumulate .MA#1 are multipliers1. )he advanced digital
processors no2 have fast it3parallel multipliers emedded in
them. Multipliers for unsigned numers are designed using
di44ying array of 2ays 2ith each method having its o2n
advantages and tradeoffs. 'n recent years, high3speed multipliers
play an important role 2hile designing any architecture and
researchers are still 2or-ing on many factors to increase the
speed of operation of these asic elements. Algorithms for
designing high3speed multipliers have een modified and
developed for etter efficiency. &e2 array structures have een
proposed. &umer of hyrid adders 2ere developed to
sustitute the operations of a simple multiplier. )he increased
comple/ity of various applications, demands not only faster
multiplier chips ut also smarter and efficient multiplying
algorithms that can e implemented in the chips. 't is up to the
need of the hour and the application on to 2hich the multiplier
is implemented and 2hat tradeoffs need to e considered.
5enerally, the efficiency of the multipliers are classified ased
on the variation in speed, area and configuration.
35. PREV'%,S 6%R7
Various methods e/ist for the reduction in the computation
time involved y the multiplier 2ith other factors as trade3offs.
(igh3speed, it3parallel multiplication can e classified into
*#orresponding Author
)his 2or- 2as carried out y ma-ing use of the oards donated to Sona
#ollege of )echnology under the Altera ,niversity Program y Altera
Semiconductors Pvt. !td., 'ndia .
three types .a1 shift3and3add
multipliers that generate
partial products se8uentially
and accumulate. )his re8uires
more hard2are and is the
slo2est multiplier. )his is
asically the array multiplier
ma-ing use of the classical
multiplying techni8ue 2hich
consumes more time to
perform t2o sutas-s,
addition and shifting of the
its and hence consumes 9 to
: cycles of cloc- period. .1
generating all the partial
product its in parallel and
accumulate them using a
multi3operand adder. )his is
also called as parallel
multiplier y using the
techni8ues of 6allace tree ;<=
and Booth algorithm;>=, .c1
using arrays of almost
identical cells for generation
of it products and
accumulation.
Booth algorithm proves to
e good for a highly pipelined
machines, 2ith each of the
stages eing fed to another
level. (o2ever, this is a poor
choice for a single3cycle
multiplier. )he Booth
multiplier can e modified to
implement a 6allace
multiplier, 2hich is a fast 2ay
to design a single cycle
multiplier. )he most
commonly used parallel
multiplier for V!S'
reali4ation is the array
multiplier due to the regular
cellular array structure ;9=.
(ere the multiplicand and the
multipler are summed up one
y one y means of a series of
carry3save adders. But this
relatively increases the
hard2are that 2ould re8uire
for reali4ation. )he numer of
logic gates is proportional to
n
9
. )he delay is proportional
to n, 2here n refers to the
numer of its. )hus the
algorithm proves to e area
inefficient for larger numer
of its. Reducing the given
digital inary multiplication
into its e8uivalent smaller it
value, therey increasing the
area efficiency is also one of
the most challenging area in
processor architecture.
61. VED'
#
MA)(
EMA)'
#S
)he Sans-rit 2ord ?Veda@
means -no2ledge ;A=. )he
hymns of the Rig Veda are
considered the oldest and
most important of the Vedas,
having een composed
et2een <BCC B#. )he gift
that the 'ndians gave to the
2orld, thousands of years
ago, and 2hich is no2
currently employed in our
gloal silicon chip
technology, 2as none other
than the invention of 4ero and
decimal points. )he concept
of 4ero has een evidently
descried in PingalacharyaDs
#handa Shastra, 2hich dates
ac- to 9CC B.#. using
Sans-rit couplets ;E=. Earliest
mention in Anuyogadvaara
Sutra .<CC B#1 is as follo2s
?)he total numer of human
eings in the 2orld, 2hen
e/pressed in terms of
denominations, occupies 9A
places@. Sans-rit scholars
translated these vedic
documents and 2ere really
surprised at the depth and
readth of the -no2ledge
contained y them.
978-1-4244-4791- 6/10/$25.00 c 2010
IEEE 25
Some maFor te/ts li-e ?5anita Sutras@ .'n Sans-rit, the ancient
language of 'ndia, the 2ord ?Sutra@ means G)hread of
7no2ledgeG12ere devoted to mathematical -no2ledge, 2hich
mainly addressed the geometry of construction of sacrificial
altars, geometrical figures such as straight lines, rectangles,
circles and triangles. Many mathematical methods descried in
the Vedas 2ere previously un-no2n and created great
ama4ement among scholars. Some of the ancient te/ts 2ere lost
during the course of time due to various untold reasons. )hus the
astonishing system of calculation orn in the Vedic Age 2as
deciphered during the start of the 9C
th
century. During <A<< and
<A<: Sri Bharathi 7irshna )irtha .<::H3<A>C1 ;>=, a
mathematician and the pontiff of the famous San-ara Mutt in
'ndia, carried out research y interrelating various ranches of
mathematics and the e/isting ancient Sans-rit te/t. After an
e/tensive study, he proposed <> algorithms .named as ?sutras@
in Sans-rit1 for easier and faster calculations. )he most
astonishing feature in the Vedic mathematics is its coherence.
'nstead of a mi/ture of unrelated techni8ues, the entire system is
marvelously interconnected and fused.
)he <> sutras of Vedic mathematics ;H= are given in the
tale <, ut the discussion of all the algorithms is eyond the
scope of this paper.
)AB!E '. )(E <H A!5%R')(MS '& VED'# MA)(S
*o Vedic +utras in +anskrit ,nglish Meaning
<.
By one more than the one
efore.
9.
All from A and the last
from <C.
E. Vertically and #ross32ise
H. )ranspose and Apply
B.
)he summation if e8ual to
Iero
>.
'f %ne is in Ratio the
%ther is Iero
J.
By Addition and y
Sutraction
:.
By the #ompletion or
&on3#ompletion
A. Differential #alculus
<C. By the Deficiency
<<. Specific and 5eneral
<9.
)he Remainders y the
!ast Digit
<E.
)he ,ltimate and )2ice
the Penultimate
<H.
By %ne !ess than the %ne
Before
<B. )he Product of the Sums
<>. All the Multipliers
'V. VED'# M,!)'P!'ER
)he formula ;H= simply means K
?all from A and the last from <C@. )he algorithm has its est
case in multiplication of numers, 2hich are nearer to ases
of <C, <CC, <CCC i.e., increased po2ers of <C. )he procedure
of multiplication using the &i-hilam involves minimum
mental manual calculations, 2hich in turn 2ill lead to
reduced numer of steps in computation, reducing the space,
saving more time for computation. )he numers ta-en can e
either less or more than the ase considered. )he
mathematical derivation of the algorithm is given elo2.
#onsider t2o n3it numers / and y to e multiplied.
)hen their complements can e represented as /< L <C
n
3 /
and y< L <C
n
" y. )he product of the t2o numers can e
given as p L /y. &o2 a factor <C
9n
M<C
n
./My1 is added and
sutracted on the right hand side of the product e8uation,
2hich is mathematically e/pressed as sho2n elo2.
1p L /y M <C
9n
M<C
n
./My1 3 <C
9n
3 <C
n
./My1 %n
simplifying 2e get,
2p L N<C
n
./My1 3 <C
9n
O M N<C
9n
3<C
n
./My1M/yO
1= <C
n
N./ M y1 3 <C
n
O M N.<C
n
" /1 . <C
n
" y1O
2= <C
n
N/ " y<O M N/< y<O
3= <C
n
Ny " /<O M N/< y<O
0rom the aove e8uation 2e can derive the left hand side
of the product as N/ " y<O or Ny " /<O and the right hand side
as /<.y<
)he asic operations involved in the algorithm for a
given set of numers is given elo2.
#onsider AA / AJ
(ere the &earest Base L <CC
AA .<CC " AA1
AJ .<CC " AJ1
#olumn < #olumn9
AA <
AJ E
A> P CE
9 Digits 9 Digits
Result L AA / AJ L A>CE
)he &i-hilam Sutra can also e modified for inary
arithmetic. 0urther, e/ploiting certain asic properties of
multiplication li-e shifting and also y ma-ing use of the
26 2010 IEEE 2nd International Advance
Computing Conference
&i-hilam Sutra a ne2 multiplication algorithm has proposed
here2ith.
1. The Proposed Algorithm
)he pseudo code of the algorithms proposed in this paper
is given elo2. )he algorithm is roadly divided in three parts
namely the initiali4ation, preprocessing and processing.
)he proposed algorithm evidently reduces a given H it
multiplication to a 93it multiplication y ma-ing use of asic
shifting and addition operations, as a result of 2hich the carry
propagation in any standard H / H 3 it multiplier is reduced to
a great e/tent.
2. Pseudo Code
.a1 'nitiali4ation
'nitiali4e K flag< L flag9 L flagE L flagH L C
.1 Preprocessing
'nput H3it inary numers a and
n<L &umer of least significant consecutive 4eros in
a n9 L &umer of least significant consecutive 4eros
in n L n< M n9
a<L Right shift a y
n< <L Right shift
y n9
.c1 Processing
1.'0 .a<Q <CCC $ < Q <CCC1
)(E& a<L <CCCC 3 a<R
<L <CCCC 3
<R flag< L <
2.'0 .a<Q <CC $ < Q <CCC1
)(E& < L < 3 <CCCR
;'f < Q <CC $ a< Q <CCC, )(E& a< L a< 3
<CCC= flag9 L <
;Solution L a< / <CCC M< / a<=
3.'0 a< Q <CC $ < Q <CC
)(E& a< L <CCC 3 a<R
< L <CCC "
<R flagE L <
4.'0 .a< Q <C $ < Q <CC1 )(E&
< L < 3 <CCR
;'f < Q <C $ a< Q <CC, )(E& a< L a< 3
<CC= flagH L <
;Solution L a< / <CC M < / a<=
5.'0 .a< L <1 )(E& p< L < or '0 .< L <1 )(E& p< L
a< 5%)% Step J
6.Perform 93it multiplicationK p< L a< / <
7.'0 .flagH L <1 )(E&
p< L a< / <CC M p<R
< L <CC M <R
:. '0 .flagE L <1 )(E&
p< L N !(S L <CCC 3 .a< M <1 M carry of R(SO or
NR(S L .E3it1p<OR
a< L <CCC M a< R < L <CCC M <
9.'0 .flag9 L <1 )(E&
p< L a< / <CCC M p<
R < L <CCC M<
10. '0 .flag< L <1 )(E&
p< L N!(S L <CCCC 3 .a< M <1 M carry of R(SO or
NR(S L .H3it1 p<OR
11. p L !eft shift p< y n its
12. Return the product p
13. E&D
C. Analysis of the Algorithm
'n the preprocessing stage, the least significant
consecutive 4ero its of oth the multipliers and the
multiplicand are removed, therey decreasing the
computational time. )he effect of the removed 4ero its is
efficiently incorporated y shifting the final product to the left
y e8ual numer of its. 0or certain cases, 2hen the given H
it numers are not reduced y its si4e in the preprocessing
stage, the algorithm is further proceeded therey reducing the
it si4e of oth the numers to E y using the asic principles
of &i-hilam Sutra. 'f the numers thus otained are e/actly E3
it numers, the algorithm is once again applied to reduce the
multiplication to 9 / 93it, the multiplication of 2hich can e
done 2ith the help of any standard multiplier.
'n certain other conditions, if the numers otained after
preprocessing stage are H3it and E3it numers, the larger
numer is e/panded as a sum of inary <CCC and is converted
into a E3it numer. )his reduces the entire multiplication to a
E3it multiplication operation, follo2ed y a shift and an
addition operation. A E3it multiplication is further reduced to
a 93it multiplication operation as e/plained in the previous
case. )he same method is true for the case for numers of E
it and 9 it si4e.
0inally, another possiility might arise, 2here either of the
numers is <. 'n that case, the output is al2ays e8ual to the
other numer, irrespective of the value of the numer otained
after processing. )he proposed multiplier algorithm can
further e e/tended for larger numers 2ith some
modifications in the algorithm conditions chec-ing steps
accordingly
22. S'M,!A)'%& A&D 'MP!EME&)A)'%& %0 )(E PR%P%SED
A!5%R')(M
)he algorithm 2as designed for : it input using Verilog3
(D! and implemented using an automatic synthesis, place
and route approach of Altera Suartus ''. A very high
performance, ACnm, process 2as used for the implementation
2ith standard cell lirary designed for high speed
applications. )ale '' summari4e the implementation results.
0ig. < sho2s the floor plan of the proposed algorithm.
)he po2er consumed y the proposed multiplier, along
2ith the other operating conditions is sho2n in the tale E
elo2. )he ma/imum operating fre8uency of the proposed
multiplier 2as found to e <BC.J>M(4 under normal
operating conditions and 2ith all the input signals having
normal inputs. 't is evident from the tale given elo2 that
only <AC< logic elements are re8uired for the proposed
architecture in a ACnm scale.
2010 IEEE 2nd International Advance Computing
Conference 27
TABLE II. RES%,R#E U)'!'IA)'%&
-etails *umber of
elements
Estimated Total logic
elements 1,901
Total combinational functions 833
Logic element usage b numbe! of LUT
in"uts
# in"ut
functions #8#
3 in"ut
functions $39
$ in"ut
functions 110
Logic elements b mode
no!mal mode %%9
a!it&metic
mode '#
I() "ins $3
Total memo!
bits 1%0$#
TABLE III. *%6ER +%&S,MP)'%& %0 )(E *R%P%SED A!5%R')(M
.perating /onditions /alculated 0ower
In"ut ,oltage ,++ 1.$ ,
Total T&e!mal *o-e!
.9.39m/
0issi"ation
L,TTL I() 1tanda!d 3.3 ,
1tatic +o!e T&e!mal
#%.3'm/
*o-e!
0issi"ation
Ambient tem"e!atu!e $'+ I() *o-e! dissi"ation $$.03m/
2igu!e 1. +&i" *lanne! of t&e "!o"osed -o!3
V'. #)4+LU1I)4
)he proposed vedic multiplication architecture presented in this paper is a ne2 efficient method for decomposing a perfect
inary multiplication into smaller si4e and hence reducing the computation time and po2er consumption. 0urthermore, the
hard2are costs of memory re8uired and the comple/ity of the multiplier can e reduced. )his test chip 2as designed, faricated,
and tested in ACn m #M%S process to chec- the functionality and various other design aspects.
A+54)/LE067E4T
)he authors profusely than- Altera Semiconductors, 'ndia for donating oards to carry out this proFect. )he authors also 2ish
to than- the Sona Management for the continuous financial and moral support to2ards this R$D 2or-. )he authors 2ould li-e to
than- their colleagues of the S%&A S'PR% Research group of Sona #ollege of )echnology, Salem and their family memers for
many fruitful discussions.
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28 2010 IEEE 2nd International Advance
Computing Conference