Characterization of interface traps in the subthreshold

region of implanted 4H and 6H-SiC MOSFETs

Yu (Anne) Zeng
*
, Amela Softic, Marvin H. White
Lehigh University, Sherman Fairchild Laboratory, Bethlehem, PA 18015, USA
Received 5 January 2002; received in revised form 9 February 2002; accepted 14 February 2002
Abstract
In this paper the interface trap densities (D
it
) of 4H and 6H-SiC MOSFETs in the subthreshold region have been
studied. Interface trap densities in this region were extracted as a function of trap energy (E
T
) from the transfer
characteristics. We show these interface trap densities increase exponentially approaching the onset of strong inversion
for both polytypes, and D
it
E
T
is higher in 4H than in 6H through the subthreshold region. These results are consistent
with previous reports [16].
2002 Elsevier Science Ltd. All rights reserved.
Keywords: Interface traps; Interface trap density; Subthreshold region; 6H-SiC; 4H-SiC; MOSFET
1. Introduction
Silicon carbide is the only wide-band semiconductor
with a native oxide, which makes it an ideal candidate
for MOS device fabrication in high power applications.
However, the oxide quality grown on a SiC surface is
very poor compared to the oxide grown on a silicon
surface, because there exists a large density of interface
traps in the SiC/SiO
2
system. Dierent methods, in-
cluding capacitancevoltage (CV ) measurement [3,5],
and Hall eect measurement [6], have been employed to
extract interface trap densities.
In this paper, we present a technique for the extrac-
tion of the interface trap density in the subthreshold
region. Although this technique has been used for
Si MOSFETs, we believe this is the rst time for SiC
MOS devices. The results achieved demonstrate the
utility of this technique to extract D
it
in the subthreshold
region.
2. Analysis
The currentvoltage relationship in the subthreshold
region can be expressed as [7]
I
DS
I
0
exp
qV
GS
nkT
_ _ _ _
1
_
exp
_

qmV
DS
nkT
__
I
m
1
_
exp
_

qmV
DS
nkT
__
1
where
n 1
C
d
C
it
C
ox
2
m 1
C
d
C
ox
3
I
m
I
0
exp
qV
GS
nkT
_ _
4
Here C
ox
is dened as the oxide capacitance, C
d
is the
depletion capacitance, and C
it
is the interface trap ca-
pacitance.
The extraction procedure for the interface trap density
D
it
C
it
=q requires the determination of the parameter n
from the log I
DS
vs. V
GS
transfer characteristics as
Solid-State Electronics 46 (2002) 15791582
www.elsevier.com/locate/sse
*
Corresponding author.
E-mail address: yuz3@lehigh.edu (Y.A. Zeng).
0038-1101/02/$ - see front matter 2002 Elsevier Science Ltd. All rights reserved.
PII: S0038- 1101( 02) 00108- 9
n
q
2:3kT
o log I
DS
oV
GS
_ _
1
5
with a subthreshold swing dened by
S 2:3
kT
q
n volts=decade 6
A plot of log1 I
DS
=I
m
) vs. V
DS
yields the ratio
m
n
2:3
kT
q
o log 1
I
DS
Im
_ _
1
oV
DS
_
_
_
_
_
_ 7
where the parameter m is obtained by combining Eqs.
(5) and (7).
D
it
is extracted at a given gate bias V
GS
, which cor-
responds to a value of surface potential /
S
D
it
/
S

C
it
/
S

q

C
ox
q
n m 8
where /
F
6/
S
62/
F
, and the extracted interface trap
densities are located in the range of E
G
=2/
F
6E
C

E
T
6E
G
=2.
The relationship between gate voltage, V
GS
, and sur-
face potential, /
S
, is determined with the Berglund
technique [8] and the transconductance change method
[9], which yields the additive constant at /
S
/
F
, where
/
F
is the Fermi potential.
3. Device fabrication
Devices used in this work [2] are n-channel MOS-
FETs in the implanted p-wells on 6H- and 4H-SiC
(n/n

) wafers. These wafers were purchased from CREE

with 10 lm n-type epilayer (10
16
cm
3
) on n

substrate
(10
18
cm
3
). The aluminum-implanted p-well has a
doping concentration of 10
17
cm
3
and a depth of 0.7
lm. Nitrogen is implanted to form source and drain
regions with doping of 10
19
cm
3
and junction depths of
0.4 lm. The thermally grown oxide thickness is about
400

AA. A schematic cross section of the MOSFET is
shown in Fig. 1.
4. Experimental results
Figs. 24 describe the measurements on device #1,
which is a 4H-SiC NMOS transistor with W =L 500
lm=10 lm.
Figs. 5 and 6 describe the measurements on device
#2, which is a 6H-SiC NMOS transistor with W =L
500 lm=10 lm.
5. Discussion
The extracted interface trap densities for 6H- and
4H-SiC MOSFET were replotted in Fig. 7 in order to
make a comparison.
Fig. 1. Schematic cross-section of the n-channel SiC MOS-
FETs.
Fig. 2. Transfer characteristic of 4H-SiC MOSFET with
W =L 500 lm=10 lm.
Fig. 3. Extraction of m=n ratio V
GS
5:0 is shown as an
example, m=n 0:277, n 41:0, m 11:4.
1580 Y.A. Zeng et al. / Solid-State Electronics 46 (2002) 15791582
In Fig. 7, the extracted interface trap densities for
both 4H and 6H-SiC MOSFETs show an exponential
increase when approaching the onset of strong inver-
sion. By comparing D
it
E
T
in 4H and 6H-SiC, we notice
that D
it
E
T
is much higher in 4H than in 6H-SiC. These
results are consistent with former reports (e.g. the data
from Hall eect measurement in Ref. [6]). In addition,
the subthreshold swing (with interface traps) of a SiC
MOSFET, which is reected in the value of parameter
n, is much larger than that of a Si MOSFET because of
the much higher interface trap densities in a SiC MOS-
FET.
Acknowledgements
The authors would like to thank Dr. Anant K.
Agarwal and Nelson S. Saks for providing helpful in-
formation and discussions. We also thank a former
graduate student, Dr. Vickram R. Vathulya for fabri-
cating the devices. The nancial support of the Oce of
Naval Research (Dr. John C. Zolper) and the Sherman
Fairchild Foundation are gratefully acknowledged.
References
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Fig. 4. Extracted interface trap density in 4H-SiC NMOS as a
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Fig. 5. Transfer characteristic of 6H-SiC MOSFET with
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Fig. 6. Extracted interface trap density in 6H-SiC NMOS as a
function of trap energy.
Fig. 7. Comparison of D
it
E
T
in 6H and 4H-SiC.
Y.A. Zeng et al. / Solid-State Electronics 46 (2002) 15791582 1581
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