L08 Marie

L08 - MARIE
9/24/2014
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Robert F. Kelly, 2012-2014
ISE218 Fundamentals of Information Technology
SESSION 8 MARIE
Reading: Sections 4.8-4.11
Objectives
Better understand the operations of a computer
by examining a very simple processor that
includes many important features of a processor
Understand the major components (control unit,
registers, memory, ALU, and data path)
Understand the fetch-decode-execute cycle
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L08 - MARIE
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MARIE
Machine Architecture that is Really Intuitive and
Easy (MARIE)
Simple computer that illustrates hardware
concepts
Enable you to comprehend system architectures
that are much more complex
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MARIE Characteristics
Binary, two's complement data representation
Stored program, fixed word length data and instructions
4K words of word-addressable main memory
16-bit data words
16-bit instructions, 4 for the opcode and 12 for the
address
A 16-bit arithmetic logic unit (ALU)
Seven registers for control and
data movement
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2 bytes per word 2 bytes per word
Opcode is the numeric
value of the operation
(e.g., Load Register)
Opcode is the numeric
value of the operation
(e.g., Load Register)
MARIE
instruction
MARIE
instruction
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MARIE Addressing
12 bit address
12 bit binary number ranges from 0 to 2
12
-1
2
12
= 2
4
* 2
4
* 2
4
= 16 * 16 * 16
= 4,096
12 bit address allows for 4K addressable memory
Every memory location has an address from 0 to
4095
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Remember, memory is
usually byte addressable
Remember, memory is
usually byte addressable
MARIE Architecture
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Programs and
data are stored
in memory
Programs and
data are stored
in memory
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MARIE Registers
Accumulator(AC) - 16-bit register that holds a
conditional operator (e.g., "less than") or one
operand of a two-operand instruction
Memory address register (MAR) - 12-bit register
that holds a memory address (an instruction or
the operand of an instruction)
Memory buffer register (MBR) - 16-bit register
that holds data either
after its retrieval from memory or
before its placement in memory
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Operand is a parameter to
the operation
Operand is a parameter to
the operation
MARIE Registers
Program counter, PC, a 12-bit register that holds
the address of the next program instruction to be
executed
Instruction register, IR, which holds an instruction
immediately preceding its execution
Input register, InREG, an 8-bit register that holds
data read from an input device
Output register, OutREG, an 8-bit register, that
holds data that is ready for the output device
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MARIE Architecture
Registers are interconnected, and connected with
main memory through a common data bus
Each device on the bus is identified by a unique
number that is set on the control lines whenever
that device is required to carry out an operation
Separate connections are also provided between
the accumulator and the memory buffer register,
and the ALU and the accumulator and memory
buffer register
permits data transfer between these devices without
use of the main data bus
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MARIE Data Path
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Instruction Set Architecture
Instruction Set Architecture (ISA) - specifies the
operations that the machine can perform and
format of instructions
Interface between a computers hardware and its
software (i.e., SW abstraction of HW)
Some ISAs include hundreds of different
instructions for processing data and controlling
program execution
The MARIE ISA consists of only thirteen
instructions
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MARIE has a 4-bit opcode MARIE has a 4-bit opcode
MARIE ISA
This is the format
of a MARIE instruction:
Fundamental MARIE instructions:
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Address X is contained
in the Address field
Address X is contained
in the Address field
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Example
This is a bit pattern for a LOAD instruction as it
would appear in the IR:
Opcode is 1 (Load X)
Address from which to load the data is 3
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Destination of the
load (AC) is implicit
Destination of the
load (AC) is implicit
All data from memory
moves first into the MBR
All data from memory
moves first into the MBR
Example
This is a bit pattern for a SKIPCOND instruction
as it would appear in the IR:
Opcode is 8 and bits 11 and 10 are 10, meaning
that the next instruction will be skipped if the
value in the AC is greater than zero
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Conditions
00 AC < 0
01 AC = 0
10 AC > 0
Conditions
00 AC < 0
01 AC = 0
10 AC > 0
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Micro-operations
IN MARIE, each machine operation consists of
one or more discrete steps (micro-operations)
Specified using register transfer language (RTL)
In the MARIE RTL
M[X] indicates the actual data value stored in memory
location X
indicates the transfer of bytes to a register or
memory location
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Used here to illustrate the
operation of the hardware
Used here to illustrate the
operation of the hardware
Microcode
A layer of hardware-level instructions used to
execute machine code
Resides in special high-speed memory
Usually not visible to a programmer
A simple way to implement a complex
architecture
Examples
Classic example IBM 360
Current game programming systems
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Fewer current
processors are
microprogram
controlled
Fewer current
processors are
microprogram
controlled
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Sample RTL
The RTL for the LOAD
instruction is:
MAR X (load address
into the memory address
register)
MBR M[MAR] (move
data stored in MAR
address into MBR)
AC MBR (move MBR
data to accumulator)
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Text has RTL code for
all MARIE instructions
Text has RTL code for
all MARIE instructions
Sample RTL
RTL for the ADD
instruction is:
MAR X (load address
into the memory address
register)
MBR M[MAR] (move
data stored in MAR
address into MBR)
AC AC + MBR (add
data in MBR to
accumulator)
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A Simple Program
Consider the simple MARIE program given below.
We show a set of mnemonic instructions stored at
addresses 0x100 0x106 (hex):
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A Simple Program
Lets look at what happens inside the computer when
our program runs.
This is the LOAD 104 instruction:
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4.10 A Simple Program
Our second instruction is ADD 105:
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Fetch-Decode-Execute Cycle
Series of steps that a computer carries out for
each instruction in the ISA
Steps
1. Fetch an instruction from memory, and place it into
the IR
2. Decode the instruction to determine what needs to be
done next (based on leftmost 4 bits of instruction)
3. If a memory value (operand) is involved in the
operation, it is retrieved and placed into the MBR
When completed, the instruction is executed
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Fetch-Decode-Execute Cycle
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Interrupts
All computers provide a way of interrupting the
fetch-decode-execute cycle
Interrupts occur when:
A user break (e.g., Control+C) is issued
I/O is requested by the user or a program
A critical error occurs
Interrupts can be caused by hardware or software
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Software interrupts are
also referred to as traps
Software interrupts are
also referred to as traps
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Interrupt Processing
Interrupt processing involves adding another step
to the fetch-decode-execute cycle as shown
below.
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Interrupt Processing
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ISR interrupt
service routine
(code to execute
for a given
interrupt)
ISR interrupt
service routine
(code to execute
for a given
interrupt)
Saving the
variables and
registers is
referred to as
saving the state
of the process
Saving the
variables and
registers is
referred to as
saving the state
of the process
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Interrupt Handling
It is common to disable all interrupts during the
time in which an interrupt is being processed.
Typically, this is achieved by setting a bit in the flags
register
Interrupts that are ignored in this case are called
maskable
Nonmaskable interrupts are those interrupts that
must be processed in order to keep the system in
a stable condition
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More advanced processors
support more advanced interrupt
handling features
More advanced processors
support more advanced interrupt
handling features
Instruction Processing
Interrupts are very useful in processing I/O
MARIE uses a modified form of programmed I/O
All output is placed in an output register, OutREG
CPU polls the input register, InREG, until input is
sensed
The value is copied into the accumulator
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L08 - MARIE
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Have You Satisfied Objectives?
Better understand the operations of a computer
by examining a very simple processor that
includes many important features of a processor
Understand the major components(control unit,
registers, memory, ALU, and data path
Understand the fetch-decode-execute cycle
29

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