Christian Kam Pen Dissertation

Evaluation of CMOS Architectures Below 50 nm
Gate Length by Numerical Simulations

Untersuchung von CMOS Architekturen mit Gatelngen kleiner 50 nm
mittels numerischer Simulationen
Der Technischen Fakultt der
Universitt Erlangen-Nrnberg
zur Erlangung des Grades
DOKTOR-INGENIEUR
vorgelegt von
Christian Kampen
Erlangen 2010
Als Dissertation genehmigt von
der Technischen Fakultt der
Universitt Erlangen-Nrnberg
Tag der Einreichung: 02.06.2010
Tag der Promotion: 03.12.2010
Dekan: Prof. Dr.-Ing. Reinhard German
Berichterstatter: Prof. Dr.-Ing. Heiner Ryssel
Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel
iii
Dedicated to my grandfather Dr. med. Franz Mauer
(25.10.1921-28.01.2007)
iv
Theyre all coming back again
The same faces that turned their backs
Are now letting me back in
How quickly the tides change
How quickly they remember my name
Did they think Id sit around waiting for them to stand by my side?
Did they think Id sit around waiting for them to arrive?
Theyre all leaving again
The same faces that came back are now walking away
How quickly the tides change
How quickly they forgot my name
Its all water under a bridge now anyway
How quickly we forget
Blacklisted
Acknowledgement
I would like to express my gratitude to all those who gave me the possibility and helped me to write this
thesis. First of all, I would like to thank my supervisor Prof. Dr. Heiner Ryssel for the possibility to work
at Fraunhofer IISB, as well as for his guidance during my research and writing of this thesis.
Special thanks go to Dr. Alexander Burenkov for excellently supervising my thesis. Without working
under his supervision I would not have been able to conduct this research and successfully complete this
thesis.
I would like to thank TimFhner for the working relationship on the CoLiDe framework, for the technical
discussions, and for the support in terms of computer scientic questions.
Big thanks go to Dr. Jrgen Lorenz for giving me the chance to work in the department of Technology
Simulation at Fraunhofer IISB.
This research has been in part supported by the European Commission Information Society Technologies
Program, under PULLNANO project contract No. IST-026828, Fraunhofer Internal Program under Grant
No. MAVO 817 759, and Fraunhofer Advanced Research Project 500674 Advanced Tunneling Effect
Based Devices".
Besides, I would like to thank all colleagues and students with whom I had the pleasure to work with.
In particular, I would like to thank Dr. Gheorghe Ardelean, Dr. Valrie Aubry-Fortuna (University Paris-
Sud), Dr. Eberhard Br, Dr. Anton Bauer, Prof. Dr. Arnaud Bournel (University Paris-Sud), Felicitas
Coenen, Dr. Andreas Erdmann, Dr. Peter Evanschitzky, Dr. Michael Jank, Dr. Stfan Koffel, Ina Ko-
drasi, Daniel Kunder, Dr. Alberto Martinez-Limia, Auron Medjzini, Dr. Christian Motzek, Dr. Michael
Otto, Dr. Peter Pichler, Cathrine Prinz, Oliver Rudolph, Hans Schermer, David Schindele, Dr. Thomas
Schnattinger, Ulrich Schpka, Dr. Thomas Schulz (Inneon/IMEC), and Matthias Sekowski.
Big love and thanks go to my family for their love, support, and funding.
Additional thanks go to the members of my bands s.punch (2000-2008) (Matthias, Stefan, Alexander,
and Robert), Facing The Swarm Thought (Matthias, Cornelius, Matthias, Michael, and Peter), and Dolly
Blaster (Florian, Stefan, Jens, and Paul) for their understanding and for supporting me during this time.
You guys ROCK!
v
vi Acknowledgement
Abstract
A full device simulation study of MOSFETs up to the circuit level is presented in this thesis. Bulk
MOSFETs, single gate fully depleted silicon on insulator (SG FDSOI) MOSFETs, double gate fully de-
pleted silicon on insulator (DG FDSOI) MOSFETS, and triple gate (TG) FinFETs below 50 nm gate
lengths were investigated by means of TCAD and SPICE simulations. A novel charge carrier transport
model is presented in order to take quasi-ballistic charge carrier transport into account in conventional
Drift-Diffusion simulations. Process options for improving the electrical MOSFET behavior by means
of mechanical stress are discussed. A modied piezo model for taking saturation of hole mobility en-
hancement at high mechanical stress values into account is presented. The impact of Schottky contact
resistances on the electrical behavior of MOSFET devices at decreasing device dimensions is investiga-
ted by means of process simulations, device simulations, and measurements. Suggestions for efciently
reducing contact resistances are made and demonstrated by process and device simulations. Classical
and alternative MOSFET architectures are investigated and compared by numerical process and device
simulation concerning their suitability for fullling the requirements of high performance (HP) devices,
low operating power (LOP) devices, and low standby power (LSTP) devices of the 32 nm technology
node of the International Technology Roadmap for Semiconductors (ITRS). Several process options we-
re used to improve the MOSFET behavior to achieve I
on
-I
off
and CV/I requirements demanded by the
ITRS. SPICE parameters of LSTP bulk and SOI MOSFETs were extracted using classical bulk MOS-
FET compact models. A method of efcient multi-gate compact modeling using classical bulk compact
models is presented. DG FDSOI, and TG FinFET transistors were modeled using extended compact mo-
deling. Circuit simulations of an inverter, 7 stage ring oscillator, 4-bit ripple carry adder, and 6-transistor
static random access memory (6-T SRAM) cell were performed using classical and alternative MOSFET
architectures. The different behavior of bulk MOSFETs, SG FDSOI MOSFETs, DG FDSOI MOSFETs,
and TG FinFET transistors under integrated circuit conditions is discussed. Finally, the impact of process
variations on the electrical performance of classical and alternative MOSFET architectures is demonstra-
ted. Lithography simulations were coupled to process and device simulations to investigate the impact of
lithography parameter uctuations on the physical gate length and the nal MOSFET behavior. A SPICE
parameter extension is presented to take the impact of four different process variations into account in
SPICE simulations. The impact of gate length uctuations, body thickness uctuations, ash annealing
peak temperature uctuations, and dose uctuations of source/drain region implantation were modeled
using SPICE simulations. Additionally, threshold voltage uctuations due to random discrete dopants
(RDD) were taken into account in SPICE simulations in case of bulk MOSFETs. Finally, the impact of
process variations on integrated circuits is discussed. Classical and alternative MOSFET architectures
based integrated circuits were investigated concerning their stability against process variations.
vii
viii Abstract
Zusammenfassung
Diese Doktorarbeit beinhaltet eine Simulationsstudie ber das elektrische Verhalten von MOS Feldef-
fekttransistorbauelementen (MOSFETs) bis hin zur Schaltungsebene. Dabei wurde das elektrische Ver-
halten von konventionellen MOSFETs, single gate fully depleted silicon on insulator (SG FDSOI)
MOSFETs, double gate fully depleted silicon on insulator (DG FDSOI) MOSFETs und FinFETs mit
drei Gateelektroden (TG FinFET) mittels TCAD und SPICE Simulationen untersucht. Die Gatelngen
der untersuchten Transistoren lagen dabei unter 50 nm.
Fr die Untersuchungen dieser kleinen Transistoren wurde ein neues Ladungstrgertransportmodell ent-
wickelt, welches das quasi-ballistische Verhalten der Elektronen und Lcher in konventionellen Drift-
Diffusionssimulationen berechnet. Um das elektrische Verhalten der Bauelemente zu verbessern, wur-
den unterschiedliche Prozessschritte, die mechanische Spannungen im Kanal der Transistoren erzeugen,
begutachtet. Dazu wurde ein verbessertes Piezomodell entwickelt, das eine Sttigung der Lcherbeweg-
lichkeitssteigerung bei hohen mechanischen Spannungen bercksichtigt.
Der Einuss von Schottky Kontaktwiderstnden, welcher durch die zunehmende Miniaturisierung der
heutigen MOSFET Bauelemente immer weiter zunimmt, wurde ebenfalls in dieser Arbeit mit Hilfe nu-
merischer Prozesssimulationen, Bauelementesimulationen und Messungen untersucht. Optionen fr die
effektive Reduzierung von Kontaktwiderstnden werden in dieser Arbeit prsentiert.
Konventionelle und alternative MOSFET Bauelementearchitekturen wurden mit numerischen Prozess-
und Bauelementesimulation daraufhin beurteilt, ob sie den Anforderungen fr Bauelemente mit ho-
her Schaltgeschwindigkeit, Bauelemente mit niedriger Leistungsaufnahme whrend des Betriebes und
Bauelemente mit niedriger Leistungsaufnahme im Ruhezustand des 32 nm Technologieknotens der In-
ternational Technology Roadmap for Semiconductors (ITRS) gengen. Dazu werden in dieser Arbeit
unterschiedliche Prozessierungsmglichkeiten diskutiert, mit denen sich das elektrische Verhalten der
untersuchten Bauelemente dahingehend verbessern lsst, um das On-Strom zu Leckstrom und CV/I
Verhltnis zu erreichen, das von der ITRS gefordert wird.
SPICE Parameter der untersuchten CMOS Bauelemente fr niedrige Leistungsaufnahme im Ruhezu-
stand wurden mit konventionellen MOSFET Kompaktmodellen extrahiert. Dazu wird in dieser Arbeit
eine Methode vorgestellt, mit der MOSFETs mit mehreren Gateelektroden mit Hilfe konventioneller
Kompaktmodelle modelliert werden knnen. Mit dieser Methode wurden anschlieend Kompaktmodel-
le von DG FDSOI MOSFETs und TG FinFETs erzeugt.
Schaltungssimulationen einer Inverterstufe, eines siebenstugen Ringoszillators, eines 4-Bit Ripple Car-
ry Addierers und einer SRAM Zelle, basierend auf konventionellen und alternativen MOSFET Archi-
tekturen, wurden durchgefhrt. Das elektrische Verhalten von konventionellen MOSFETs, SG FDSOI
MOSFETs, DG FDSOI MOSFETs und TG FinFETs in integrierten Schaltungen wurde dabei in dieser
Arbeit diskutiert.
ix
x Zusammenfassung
Der Einuss von Prozessschwankungen auf das elektrische Verhalten von konventionellen und alterna-
tiven Bauelementearchitekturen wurde ebenfalls in dieser Arbeit untersucht. Zu diesem Zweck wurden
Lithographiesimulationen mit Prozess- und Bauelementesimulationen gekoppelt, um den Einuss von
Lithographieparameterschwankungen auf die physikalische Gatelnge und das Bauelementeverhalten zu
beobachten.
Zustzlich wurde in dieser Arbeit eine erweiterte Form der SPICE Kompaktmodellierung entwickelt,
mit der die Einsse von Gatelngenschwankungen, Schwankungen der Filmdicke von SOI Transisto-
ren, Schwankungen der Spitzentemperatur von so genannten Flash-Ausheilungen und Schwankungen
der Ionenimplantationsdosis in SPICE Simulationen bercksichtigt werden knnen. Der Einuss von
einzelnen statistisch verteilten Dotieratomen auf die Einsatzspannung von konventionellen MOSFETs
wurde dabei ebenfalls in den SPICE Simulationen bercksichtigt. Diese erweiterten Kompaktmodelle
wurden schlielich dazu verwendet, um die Einsse der jeweiligen Prozessschwankungen auf integrier-
te Schaltungen zu untersuchen. Dabei wurden Schaltungen, basierend auf konventionellen und alternati-
ven MOSFET Architekturen, auf ihre Stabilitt gegenber diesen Prozessschwankungen beurteilt.
Contents
Abstract vii
Zusammenfassung x
1 Introduction 1
2 Fundamentals 5
2.1 CMOS Device Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Numerical Simulation Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Process Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 SPICE Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Basic Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Compact Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Simulating Quasi-Ballistic Carrier Transport 21
3.1 A Field Dependent Saturation Velocity for sub-50 nm Channel Lengths . . . . . . . . . . 22
3.2 Current Saturation due to Self-Heating . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Comparison of the Advanced Drift-Diffusion Model to Monte Carlo Simulations . . . . 27
3.3.1 MOSFET Scaling Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.2 Device Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
xi
xii Contents
3.4 Comparison of Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . 30
3.5 Ballisticity Correction Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Mechanical Stress 37
4.1 Process Induced Mechanical Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.1 Mechanical Stress due to Silicidation . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.2 Contact Etch Stop Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2 Impact of Mechanical Stress on the Charge Carrier Mobility . . . . . . . . . . . . . . . 45
4.2.1 A Modied Piezo Model for <110> Channel PMOSFETs on <100> Si Substrates 46
4.2.2 Hole Mobility Simulation Results Using the Modied Piezo Model . . . . . . . 47
5 Parasitic Contact Resistances 51
5.1 Experimental Investigation of R
co
(A
co
) Dependence . . . . . . . . . . . . . . . . . . . 52
5.1.1 Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1.2 Measurement of Contact Resistances at Different Contact Areas . . . . . . . . . 53
5.2 Improved Contact-Pad Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2.1 MOSFET Performance Improvement by Alternative Contact Pad Architectures . 56
5.2.2 Doping Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6 MOSFET Architectures by Comparison 61
6.1 Devices, Simulation Setup, and Parameter Extraction . . . . . . . . . . . . . . . . . . . 61
6.1.1 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.2 Extraction of Electrical MOSFET Parameters . . . . . . . . . . . . . . . . . . . 66
6.2 Simulation Methodology Using the Example of High Performance Devices . . . . . . . 69
6.2.1 Device Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2.2 Electrical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3 Process Options for MOSFET Performance Improvement . . . . . . . . . . . . . . . . . 77
6.3.1 Mechanical Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.2 Impact of Contact Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Contents xiii
6.4 Assessment of Different CMOS Device Architectures . . . . . . . . . . . . . . . . . . . 84
6.4.1 Static Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4.2 Dynamic Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.4.3 Area Consumption and Process Effort . . . . . . . . . . . . . . . . . . . . . . . 88
7 Compact Modeling and Circuit Simulation 91
7.1 SPICE Parameter Extraction Methodology . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1.1 Extraction of Basic MOSFET Parameters . . . . . . . . . . . . . . . . . . . . . 91
7.1.2 Bulk MOSFETs and Single Gate FDSOI MOSFETs . . . . . . . . . . . . . . . 93
7.2 Compact Modeling of Multi-Gate MOSFETs . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.1 Double Gate Fully Depleted Silicon on Insulator MOSFET Compact Modeling . 95
7.2.2 Triple Gate FinFET Compact Modeling . . . . . . . . . . . . . . . . . . . . . . 98
7.3 Circuit Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3.1 Inverter and Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.3.2 4-Bit Ripple Carry Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.3 6 Transistor Static Random Access Memory Cell . . . . . . . . . . . . . . . . . 108
8 Process Variations 113
8.1 Lithography Induced Gate Length Variations . . . . . . . . . . . . . . . . . . . . . . . . 114
8.1.1 Lithography Process Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.1.2 Coupled Lithography and Device Simulation . . . . . . . . . . . . . . . . . . . 115
8.1.3 Compact Modeling of Threshold Voltage Dependence on Gate Length and Body
Thickness Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8.2 Compact modeling of R
co
(T
peak
, N
2
) Dependence . . . . . . . . . . . . . . . . . . 121
8.3 Low Standby Power CMOS Devices Under the Impact of Process Variations . . . . . . . 123
8.4 Circuit Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.4.1 Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.4.2 Memory: Static Random Access Memory Cell . . . . . . . . . . . . . . . . . . 133
xiv Contents
9 Conclusions and Outlook 139
10 References 145
A MOSFET Architectures by Comparison: List of Results 155
A.1 High Performance Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
A.2 Low Operating Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
A.3 Low Standby Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
B Own Publications 159
C Copyright Agreements 161
List of Figures 163
List of Tables 171
List of Symbols 173
List of Acronyms 177
Index 179
Chapter 1
Introduction
Since the invention of the eld effect transistor (FET) in the year 1928 by J. E. Lilienfeld [1] and the
rst practical implementation of a bipolar transistor in the year 1948 by J. Bardeen [2] (Fig. 1.1(a)),
there has been an amazing evolution of semiconductor devices. Todays metal oxide semiconductor eld
effect transistors (MOSFETs) have already been scaled into the nanometer regime (below 100 nm), with
physical gate lengths of 40 nm [3] and below (Fig.1.1(b)). The invention of the integrated circuit (IC)
by J. Kilby (1958) [4] and the development of the complementary MOS circuit (CMOS) technique by
F. Wanlass (1963) [5] offered completely new possibilities for electronic engineers. Since this moment, it
was possible to design circuits based on thousands of MOSFETs on a little piece of silicon. Compared to
the rst computer ENIAC, e.g., which was based on 17468 vacuum tubes and which had a weight of 27 t,
the rst microprocessor developed by Intel (Intel 4004) in the year 1971 [6] consisted of 2300 transistors
on a silicon area of 1/8 1/6 (Fig. 1.2(a)). Due to the good scalability behavior of MOSFETs, todays
computer processors consists of more than one billion transistors on nearly the same area of silicon. A
new integrated circuit, for demonstrating the new 32 nm technology of Intel in 2008 [7] (Fig. 1.2(b)), is
based on more than 2 billion transistors on nearly the same chip area like the Intel 4004. The result of this
(a) First bipolar transistor based on
germanium (J. Bardeen, 1948 [2])
(b) Silicon on insulator MOSFET
Lgate = 40 nm (IBM, 2003) [3]
Figure 1.1 Transistor evolution
1
2 1 Introduction
(a) Intel 4004 4-bit, 2300 transistors (1971) [6]
(b) Intel 32 nm shuttle including SRAM and key logic:
more than 2 billion transistors (2008) [7]
Figure 1.2 Integrated circuit evolution
high integration density of CMOS devices and the consequential high computing power is a whole bunch
of new electronic devices, developed in the last years. Especially mobile devices like mobile phones,
MP3-players, laptops, and digital cameras have become very popular. But also in the eld of automotive
electronics, microelectronic devices have become more and more important. Since the new applications
require in most of the cases high computing performance and low power consumption, mobile devices
in particular, IC designs become more and more complex, while the dimensions of transistors on ICs
continuously are scaled down to save silicon area and achieve higher integration density. The most
popular law for the evolution of integrated circuits is Moores law, which denes that the number of
transistors on a chip increases exponentially over the years, while the price of one transistor on the chip
decreases exponentially. To fulll the rules of Moores law, transistor dimensions are scaled down by
a factor of 0.7 at each transistor generation. On account of the aggressive scaling of recent years,
several problems appeared, e.g. increasing leakage currents and short channel effects. Furthermore, the
complexity of processes increases with decreasing dimensions of the semiconductor devices. Not only
the processing of ICs becomes more complex, also process and contamination controlling gets more
difcult to handle by shrinking the device dimensions. Due to the fact that IC processing is not a 100 %
stable procedure, little uctuations during processing, e.g. during lithography, have a great effect on
the MOSFET behavior. These so called process variations always have been and still are a major topic
for CMOS processing, as they rst of all lead to a separation of the manufactured chips into different
performance groups and secondly, decreasing the production yield of operative ICs. To either reduce or
even eliminate some of the above mentioned effects appearing in so called short channel MOSFETs [8],
a discussion of using alternative MOSFET architectures has started. One of the most promising concepts
for future CMOS technologies is the use of silicon on insulator (SOI) transistors. In this architecture,
the silicon substrate is isolated from the channel by a buried oxide layer. By isolating the substrate from
the channel, substrate leakage currents are completely suppressed and short channel effects are better
controlled. Another possibility that has been proposed is to replace conventional planar MOSFETs
by three dimensional transistors. FinFET transistors, e.g., are one of the representatives of such 3D
MOSFET architectures. But also different materials are in discussion for replacing silicon. Carbon
nano-tubes or graphene layers, which are mono atomic layers of carbon, are potential representatives for
beyond silicon and CMOS technology.
1 Introduction 3
For investigating how alternative CMOS device architectures might fulll the requirements of future IC
generations, numerical simulations are an attractive solution. As most of the physical effects in silicon
are known, well understood, and already translated into numerical computation models, technology com-
puter aided design (TCAD) software tools are able to simulate most of the silicon processing steps in a
realistic way, as well as the electrical MOSFET behavior. Due to TCAD software tools, it is possible to
save time and money. By a combination of process and device simulation, e.g., an experimental process
can be pre-adjusted on a computer, and the resulting device can be characterized before starting device
processing in a clean room. On the other hand, continuously shrinking device dimensions lead to ever
new effects in the electrical performance and have to be translated into numerical models for keeping the
simulation tools up to date.
This thesis presents a study of classical and alternative MOSFET architectures below 50 nm gate length,
starting from processing up to integrated circuit level, by means of numerical process, numerical device,
and SPICE simulations. Bulk MOSFETs, fully depleted silicon on insulator MOSFETs, double gate
fully depleted silicon on insulator MOSFETs, and three dimensional triple gate FinFETs were investi-
gated and compared concerning their potential use in future CMOS applications. To achieve this, novel
device simulation models were developed and used in device simulations for ensuring adequate realistic
conditions during the simulation study at low computational effort. Additionally, innovative and exist-
ing process options for improving the electrical behavior of CMOS devices were designed and analyzed
during this thesis.
A new model for taking quasi-ballistic charge carrier transport in sub-50 nm MOSFETs in classical Drift-
Diffusion simulations into account is presented. The model was compared to Monte Carlo simulations
of MOSFETs with gate lengths down to 10 nm and experimental results of sub-50 nm silicon on insula-
tor devices for demonstration of model validity. Process options for charge carrier mobility improvement
by means of mechanical stress were investigated and are discussed in this work. As mechanical stress
is primary used to improve the hole mobility to achieve drive current equalization of NMOS and PMOS
transistors, a closer look at existing models for simulating the impact of mechanical stress on the hole mo-
bility was taken. A modication of the linear piezo model is nally presented in this thesis, which takes
into account mobility enhancement saturation at high mechanical stress values. Simulation results were
compared to measurements and simulations presented in the literature, using existing models and the
modied piezo model. The impact of Schottky contact resistances, resulting from metal/silicon Schottky
barriers at source and drain, on the electrical MOSFET performance at decreasing MOSFET dimensions
is discussed in this thesis. Existing simulation models were compared to measurements concerning their
accuracy. Additionally, proposals for reducing Schottky resistances without increasing the whole MOS-
FET layout area are suggested. In total 24 MOSFET devices were modeled and simulated including four
different MOSFET architectures, using device specications of the 32 nm technology node of the Inter-
national Technology Roadmap for Semiconductors ITRS (Version 2007) [9] for high performance, low
operating power, and low standby power devices. The electrical behavior of bulk MOSFETs, single gate
fully depleted silicon on insulator MOSFETs, double gate fully depleted silicon on insulator MOSFETs,
and triple gate FinFET transistors is presented in this thesis and investigated on the suitability of fulll-
ing the requirements of the ITRS. SPICE parameters of low standby power devices were extracted to
discuss the practicalness of the respective device architecture under integrated circuit conditions. An ef-
cient method for multi-gate MOSFET compact modeling is presented to render the electrical behavior
of low standby power double gate fully depleted silicon on insulator MOSFETs and triple gate FinFETs.
4 1 Introduction
Finally, the impact of different process variations on the electrical performance of single MOSFET de-
vices and circuit blocks is discussed. Therefore, a framework of coupled lithography simulations, process
simulations, and device simulations is presented. The framework was used to investigate how lithogra-
phy parameter uctuations might effect the physical gate length of MOSFET devices and inuence the
electrical behavior. Additionally, existing SPICE parameters were analyzed with respect to their depen-
dence on several process variations to qualitatively reproduce the behavior of TCAD models under the
impact of process variations. In total, 2,000,000 TCAD and SPICE simulations of single MOSFET de-
vices and integrated circuit blocks were performed to evaluate the stability of alternative and classical
MOSFET architectures under the inuence of different process variations.
Chapter 2
Fundamentals
This chapter serves as a short overview about the whole thematic to be discussed in this thesis. At
rst, different CMOS device architectures are presented and reviewed. Secondly, the main simulation
ows used in this work are sketched. Finally, the main simulation models used in this thesis are briey
introduced.
2.1 CMOS Device Architectures
The rst MOSFET architecture presented here is the conventional bulk MOSFET (Fig. 2.1(a) [10]). This
kind of CMOS device architecture was and is still widely used in the logic and memory IC industry.
The device architecture has been modied and improved over the last three decades to achieve the best
switching performance at the lowest static power consumption achievable. However, the community of
device engineers agrees that the days of the bulk MOSFET architecture are counted [11, 12, 13]. Due
to the bulk silicon device design, it is becoming hard to suppress leakage currents and to achieve a
good electrostatic control of the channel by the gate at short gate lengths [11, 12, 13]. Therefore, device
engineers proposed to use alternative CMOS device architectures.
The silicon on insulator (SOI) architecture is most promising for future CMOS applications [12, 13]. In
this technology, the channel region of the MOSFET is isolated fromthe silicon substrate by a buried oxide
(BOX) layer (Fig. 2.1(b) [14]). Due to the isolation of the channel from the silicon substrate, leakage
currents into the substrate are completely suppressed. The substrate leakage currents generally can be
separated into two classes: pn-junction current and gate induced drain leakage (GIDL) current [8, 15].
Furthermore, due to the isolation of the silicon body from the substrate, latch up effects [8], which
lead in a bulk CMOS circuit to bypassing of NMOS and PMOS transistors and, in the worst case, to a
destruction of the circuit, are completely suppressed. A further improvement when using SOI technology
is an efcient suppression of short channel effects, if very thin silicon lm thicknesses are used [16, 17].
Whereas in bulk MOSFET devices the channel doping concentration and so called heavily doped pocket
implants serve for suppressing the punch-through [15, 8] between the source and drain electrodes, it
is not necessary to use high channel doping concentrations in SOI transistors anymore. Therefore, it
was decided to use the initial doping concentration of silicon after crystal growth as channel doping
concentration, which is, in case of SOI wafers, between 10
15
and 10
16
cm
3
. In the literature, these
5
6 2 Fundamentals
(a) (b) (c) (d)
Figure 2.1 CMOS device architectures to be investigated: (a) Bulk MOSFET [10]; (b) SG FDSOI MOS-
FET [14]; (c) DG SOI MOSFET [22]; (d) FinFET [23]
non-intentionally doped channels are denoted as so called "undoped" channels [18]. To go conform
with other works dealing with the topic of SOI devices, the expression of "undoped" channels is used
in this thesis, too, to indicate non-intentional doping of MOSFET channels. The lightly doping of the
channel regions improves the charge carrier mobility of the transistors as impurity scattering probability
is minimized [19, 20]. However, to achieve a good electrostatic control of the channel, the body of the
SOI transistor has to be very thin [16, 17]. Additionally, it was demonstrated in the literature that the
electrostatic behavior of the so called single gate SOI MOSFET can be improved by creating a very high
doped region below the buried oxide, oppositely the channel region [21].
Another way to improve the electrostatics of MOSFET devices is to use multiple gate electrodes. Fig-
ure 2.1(c) [22] shows the architecture of a so called double gate MOSFET that is based on SOI technol-
ogy. Due to the second gate electrode, the electrostatics of the channel can be better controlled by the
gate voltage than in a single gate transistor [12]. This leads to an excellent control of the drain induced
barrier lowering (DIBL), which is the shift of the threshold voltage at rising drain voltage, and a steep
slope of the subthreshold current. A second advantage of using two gate electrodes is the doubling of
the drive current, if the MOSFET is completely symmetrical. This leads to the possibility to reduce the
MOSFET layout area.
The device engineering community also proposed three dimensional MOSFET architectures for using
more than two gates, to improve electrostatic stability and saving layout area. FinFETs (Fig. 2.1(d) [23]),
e.g., are representatives for such three dimensional MOSFET architectures [24]. They are based, in most
of the cases, on SOI technology. Here, thick silicon layers of approximately 60 nm to 70 nm are used. In
the region of the channel, so called ns are etched out of the silicon layer. The gate oxide is formed and
the poly-silicon gate is deposited and patterned. The gate electrode then encloses the ns on three sides:
top, front, and back. It is, therefore, possible to produce, e.g., triple gate MOSFETs. Due to the three
dimensional structure, planar layout area on the silicon die can efciently be saved. However, processing
of FinFETs still has several problems to be solved. To efciently save layout area, the spaces between
the ns have to be as small as realizable, while the n height has to be as high as possible. Thus, one
has to deal with shadowing effects during implantation and with lithography and etching problems [25].
Furthermore, for a good electrostatic control it is important to pattern very thin ns, which often leads to
re-crystallization problems during annealing [26].
Not only new MOSFET architectures are in discussion, but also using specic mechanical stress as
MOSFET performance booster. It could be demonstrated that tensile mechanical stress of the silicon
2.2 Numerical Simulation Principles 7
lattice along the channel enhances the electron mobility, while compressive stress of the silicon lattice
along the channel enhances the hole mobility [27]. Three major techniques are used by the industry
to apply mechanical stress: pre-strained silicon channels [28], silicon-germanium pockets, and stress
liners [29]. Pre-strained silicon channels are formed by depositing silicon on a silicon-germanium layer.
Due to the larger lattice constant of silicon-germanium, the deposited silicon layer is tensile strained.
The larger lattice constant of silicon-germanium can additionally be used to compressively strain the
channel. Germanium is, therefore, implanted into the source/drain regions of a MOSFET, followed
by an annealing step. During annealing, germanium compounds with silicon to silicon-germanium.
The resulted SiGe regions nally compress the channel region due to their greater lattice volume [30].
A further option for creating mechanical stress that came into discussion is the use of contracting or
distending nitride contact etch stop layers (CESL). These so called stress liners [29] can be used to either
apply compressive or tensile mechanical stress to the channel regions of MOSFET devices. A more
detailed discussion about the use of stress liners can be found in Chapter 4.
2.2 Numerical Simulation Principles
In this section, the basic principles and simulation models used in this work are discussed. In princi-
ple, TCAD simulation studies are separated into three parts: process simulation, re-meshing to adjust
the numerical mesh for the device simulation, and device simulation. The procedure becomes a little
more complex if three dimensional simulations should be performed. Here, the basic three dimensional
structure is formed in a CAD software rst, and is then passed to a process simulation tool to perform,
e.g. ion implantation and annealing simulations, followed by re-meshing, and device simulation again.
Figure 2.2 displays the two main simulation ows that are widely used in this work.
Figure 2.2 Simulation ow used in this work
8 2 Fundamentals
2.2.1 Process Simulation
SentaurusProcess (SProcess) of Synopsys is used for the process simulation part. The software is an
advanced 1D, 2D, and 3D process simulator which is suitable for silicon and other semiconductor mate-
rials. It includes several models for standard silicon processing steps, like oxidation, deposition, etching,
implantation, and diffusion. Furthermore, it accounts for mechanical stress which has become a big topic
in the CMOS industry in the last years [31].
2.2.1.1 Geometrical Patterning of MOSFET Devices
The geometrical patterning of MOSFET architectures that will be presented in this work is mainly
done by using standard models for oxidation, deposition, etching, and chemical mechanical polishing
(CMP) [31]. Starting with a substrate, silicon for bulk MOSFETs and SOI substrate for SOI and FinFET
devices, the gate oxide is deposited on the whole substrate. Then, a poly-silicon layer is deposited on the
oxide lm. It is anisotropically etched using a negative mask for patterning the gate electrode. An addi-
tional oxide layer is isotropically deposited on the gate stack, serving as a lateral alignment layer for the
low doped drain (LDD) implantation step to form the source/drain extensions. Followed by the LDD im-
plantation, a nitride layer is deposited isotropically on the whole gate stack to form spacers for the highly
doped drain (HDD) implantation step by anisotropic etching. They serve also as a mask for removing
the remaining oxide layer. Subsequently, additional silicon is deposited to elevate the source/drain re-
gions. These elevated source/drain layers are in most of the cases named as SEG layers [18], which is
the acronym for selective epitaxial growth layers. The elevation of the source/drain regions has several
positive effects. First of all, the DIBL effect is reduced, as the impact of the drain potential on the chan-
nel region decreases. Secondly, the SEG layer offers the possibility to implant large amounts of dopants,
which is benecial for low contact resistances. Finally, in todays CMOS processes, the source/drain con-
tacts are silicided to increase the active contact area. The silicidation, however, consumes part of the
silicon. Therefore, the SEG layer serves as a kind of a silicon reservoir for the silicidation, too. Fol-
lowing the SEG layers formation, a new oxide layer is deposited isotropically to serve as scattering lm
for the HDD implantation step to form the active source/drain regions. Finally, an annealing step is per-
formed to activate the implanted dopants, to anneal defects of the crystal lattice, and to re-crystallize
amorphous silicon layers resulting from ion implantation.
2.2.1.2 Simulation of Ion Implantation
Ion implantation is the commonly used method for doping todays CMOS devices. Since Shockley
obtained the patent of ion implantation technique in the year 1957 [32], this technique stood up to other
doping techniques as epitaxy and spin-on-dopant sources. However, doping by ion implantation causes
several problems, e.g. of creating radiation induced defects in the crystal lattice and amorphization of
silicon [33]. In this work, ion implantation was simulated using analytical models, based on empirical
point-response distribution. In case of 2Dsimulations, an ion beamincident at a point (, ) is assumed to
generate a distribution function F(x, y, , ) [34, 31]. The nal ion concentration at a certain point (x, y)
is then calculated by computing the superposition of all distribution functions of all possible points of
incidence ((s), (s)) on the surface of the implanted structure (gas to solid interface
gas
in SProcess):
N(x, y) = N
2
_
gas
F(x, y, (s), (s))ds. (2.1)
In Eq. (2.1), N
2
is the total dose per exposed area and N(x, y) is the nal doping prole [34, 31]. In 2D
simulations, F(x, y, , ) is usually approximated by
F(x, y, , ) = f
p
(x (s)) f
l
(y (s), x (s)), (2.2)
where f
p
(x(s) is the vertical distribution function and f
l
(y (s), x(s)) is the lateral distribution
function [35]. While the vertical distribution function is only dependent on the depth x, the lateral
distribution f
l
(y, x) depends on both, the lateral spread y and the depth x, which determines the shape
of f
l
. Two major vertical distributions f
p
(x (s)) of the implanted ions are used in SProcess for
calculating the primary doping prole in silicon [31]:
Gaussian distribution:
f
p
(x) =
1
2
p
exp
_
(x R
p
)
2
2
2
p
_
, (2.3)
where the projected range R
p
is the rst moment and is the standard deviation (the second
moment) of the projected ranges. The skewness (third moment) of the prole is zero in this ap-
proximation, while the fourth moment, the kurtosis of the gaussian prole is 3.
Pearson distribution, which satises the equation
d
dx
f
p
(x) =
x R
p
a
b
0
+b
1
(x R
p
) + b
2
(x R
p
)
2
f
p
(x), (2.4)
where b
0
, b
1
, b
2
, and a depend on the second and third moment but should not be discussed in
detail in here. In SProcess, mainly type IV, type V, type VI, and dual Pearson distributions are
used for calculating the nal doping prole in silicon, dependent on the conditions for a (= b
1
),
b
0
, and b
2
[31].
The lateral distribution f
l
(y (s), x(s)) of the implanted ions is dened by a Gaussian distribution
in SProcess. To account for the correlation between the lateral and the vertical ion scattering, the standard
deviation
l
of the lateral ion spread is, in general, assumed to be dependent on the depth x:
f
l
(y, x) =
1
2
l
(x)
exp
_
y
2
2
2
l
(x)
_
. (2.5)
In this work, arsenic ions were used to form the n
+
-regions, while boron ions were used to form the p
+
-
regions. Due to very thin body thicknesses used for the SOI transistors, very low implantation energies
in the range of 1 keV to 5 keV for arsenic and 0.2 keV to 1 keV [36] for boron were used in the simulation
of ion implantation. Using these energies also in corresponding bulk MOSFETs, leads to very shallow
junctions. Shallow junctions in bulk MOSFETs are needed to ensure comparable conditions to ultra thin
body SOI devices, where the depth of the doping proles is limited by the silicon body thickness. The
ion doses N
2
of arsenic and boron commonly used in this work are within a range of 1 10
14
cm
2
to
2 10
15
cm
2
. To minimize channeling of the ions through the silicon lattice [33], a tilt of 7
was used
in the ion implantation setup of planar devices.
10 2 Fundamentals
2.2.1.3 Simulation of Activation and Diffusion of Implanted Dopants
Simulation of activation and diffusion of implanted dopants is an important issue, as the amount of the
active doping concentration has a big impact on the MOSFET performance. Generally, diffusion and
activation of implanted dopants is done by annealing at high temperatures above 800
C [37]. Here, the

implanted dopants diffuse by means of either interstitials or vacancies, dependent on the kind of dopant.
Additionally, they are built in the silicon lattice, where they can contribute to the current transport. They
are activated. Furthermore, annealing at high temperatures leads to re-crystallization of amorphous layers
and to elimination of point defects, resulting from ion implantation [33]. To calculate the diffusion of the
implanted dopants, the diffusion current J
D
has to be computed by
J
D
= D
N
cN
c
+c D
N
c N
c

_
q
kT
_
. (2.6)
In Eq. (2.6) [38], the rst term is well known as Ficks rst law and the second term denotes the eld
dependent diffusion. D
N
c is the effective diffusion coefcient, N
c
is the diffusive species concentration,
c is the charge of the respective species, and is the electrostatic potential, while k is Bolzmanns
constant, q is the elementary charge, and T is the temperature. The implanted dopants diffuse by means
of point defects of the silicon lattice, either interstitial or vacancies. Therefore, the effective diffusion
coefcient of any respective dopant-point-defect pair has to be calculated by the Arrhenius equation:
D
N
c = D
0
exp
_
E
a
kT
_
. (2.7)
D
0
is the Arrhenius pre-factor of the specic dopant-point-defect pairs and E
a
is the respective activation
energy. The re-distribution of the implanted dopants can nally be expressed by an extension of Ficks
second law of diffusion [39, 38, 31]:
N
c
t
= J
D
+G
trans
N
c G
cluster
N
c . (2.8)
Equation 2.8 describes the change of the overall diffusive species concentration N
c
per unit time. G
trans
N
c
determines the number of additional diffusive species, generated from cluster break-up, and is, therefore,
added to the overall diffusive species concentration N
c
. G
cluster
N
c
, on the other hand, denotes the formation
of clusters and has to be subtracted from the overall diffusive species concentration, as clusters cannot
contribute to the diffusion current [38]. To calculate the nal active net doping concentration, several
models are available in SProcess. However, in this work, special activation models for arsenic [40] and
boron [41] are used and discussed later.
For modern CMOS devices, rapid thermal annealing (RTA) or millisecond annealing (MSA) techniques
are commonly used. They are based on very high temperatures (above 1000
C) at small time scales

(below 1 min). A positive effect when using RTA or MSA is a relatively small redistribution of the
implanted dopant prole at high activation rates. Two examples of such RTA and MSA schemes are the
so called spike annealing and the ash annealing. Figure 2.3 shows the proles of a spike annealing
(RTA, dashed line) and a ash annealing (MSA, solid line) [42]. The bottom time scale belongs to the
spike annealing prole, while the top time scale belongs to the ash temperature prole. As can be seen,
Figure 2.3 Temperature proles vs. the annealing time of a spike an-
nealing (dashed lines) and a ash annealing (solid line) [42]
the temperature peak of the ash annealing prole is much sharper with a higher temperature (here:
T
peak
1300
C, t
peak
=1 ms) compared to the spike annealing prole (here: T
peak
=1070
C, t
peak
=5 s).
Due to the respective requirements of the different MOSFET architectures discussed in this work, the
most feasible annealing scheme has to be chosen for the particular MOSFET architecture. In case of
conventional bulk MOSFETs it is useful to have very shallow, but also highly doped source/drain ex-
tensions. In thin body SOI devices, on the other hand, the depth of the extensions does not play a role,
as the vertical diffusion is limited by the insulator layer below the silicon body. In addition, the chan-
nels of ultra thin body (UTB) FDSOI MOSFETs are in most of the cases very lightly doped, different
to conventional bulk MOSFETs, for improving the charge carrier mobility. Therefore, it is important for
SOI devices to control the lateral diffusion below the gate electrode to reduce short channel effects and
fringing capacitances. Due to the non-intentionally doped channels of SOI devices, the concentration
differences between the highly doped source/drain extensions and the more or less undoped channel re-
gions leads to a wide redistribution of the source/drain proles under the gate stack and therefore, to a
decrease of the effective channel length during annealing.
To use advanced annealing schemes like spike annealing and ash annealing in numerical process simu-
lations, it is important to have valid simulation models for diffusion and activation of dopants. In todays
CMOS devices arsenic and boron are most commonly used. To simulate diffusion and activation of
arsenic and boron by using RTA or MSA, calibrated simulation models have to be used. The arsenic
model [40], used in this work, takes into account solid phase epitaxial re-growth (SPER), calculates the
forming of inactive As4V clusters by two parallel reactions, and calculates the interstitial evolution into
extended defects [40]. Furthermore, diffusion coefcients, as well as the three-phase segregation model
for the silicon/silicon-oxide interface were veried [40], by means of comparing simulation results to
measured spike annealed and ash annealed proles of arsenic doped samples.
The model, used in this thesis to simulate diffusion and activation of boron in silicon [41], is based on
the boron-interstitial-clusters (BICs) approach [41]. Boron-interstitial-clusters are responsible for deac-
tivation of boron in silicon. The advantage of this specic model is its simplicity, which reduces the
12 2 Fundamentals
computational effort. In principle, clustering reactions of boron and interstitials are very complex. The
model only takes six reactions into account and gives a quantitative description of the defect transfor-
mation at time scales typical for RTA and ash annealing. Like the arsenic simulation model, the boron
model was veried [41] with measurements of spike annealed and ash annealed proles of boron doped
samples.
2.2.1.4 Process Simulation of Mechanical Stress
Mechanical stress has become a very important performance booster for CMOS devices in recent years.
However, the type of mechanical stress, tensile or compressive, and direction of forces along the crys-
tal lattice for achieving the maximum charge carrier mobility enhancement differ for NMOS and PMOS
transistors. Thus, process simulations are a suitable solution to nd practical process options to achieve
the maximum performance boost for both classes of MOSFETs. To calculate mechanical stress during
processing, the basic equations of elastic deformation in solid state materials are used in process simula-
tors [43, 31]. They dene the force equilibrium in the quasi-static deformation regime of solid materials
in the device structure. The strain tensor
kl
, which is related to the local deformation, is calculated at
rst:
kl
=
1
2
_
k
x
l
+

l
x
k
_
. (2.9)
In Eq. (2.9),
k
and
l
are the deformation vectors and x
k
and x
l
are the coordinates. Strain is then
related to stress by Hookes law [43]:
ij
= E
ijkl
kl
. (2.10)
ij
is the stress tensor and E
ijkl
is the elasticity modulus of the respective material. i, j, k, and l denote
the coordinates of a three dimensional system and the direction of the force. Thereby, i and j are the
coordinates for stress and k and l are the coordinates for strain. SProcess includes ve material models
for viscoelastic materials, purely viscous materials, purely elastic materials, anisotropic materials, and
plastic materials [31]. The global force equilibrium conditions inside of solid materials are given by
ij
x
j
= 0. (2.11)
By nite element method, Eqs. (2.9) and (2.11) are solved under certain boundary conditions to calculate
the strain and the stresses in the system at rst [31]. Secondly, the boundary conditions which are
required to solve the equations of force equilibrium have to be dened. In this work, a displacement of
zero at the boundary of the simulation domain was used, as set by default in SProcess [31]. Thirdly, the
material specic properties for the respective materials have to be set. This point is discussed in detail in
Chapter 4. Fourthly, stress causing mechanisms have to be selected, e.g. material growth, densication,
or intrinsic stress. The resulting stress distribution is nally calculated during a temperature step by
SProcess [31].
2.2.2 Device Simulation
Device simulation was mainly done in this work using SentaurusDevice (SDevice) of Synopsys. SDe-
vice provides one dimensional, two dimensional, and three dimensional simulations for a wide range of
semiconductor devices. It features advanced simulation models for charge carrier transport in semicon-
ductors, especially those needed for deeply nano-scaled CMOS devices with high numerical robustness.
SDevice offers the opportunity to use three different models of charge carrier transport in silicon: Drift-
Diffusion, Hydrodynamic, and Monte Carlo. Mixed-Mode simulations, which can be understood as
SPICE simulations with numerical device models, offer the ability to investigate the electrical behavior
of novel CMOS devices under circuit conditions [31].
In the eld of TCAD, device simulation is dened as the simulation of charge carrier transport in semi-
conductor devices. The simulation of charge carrier transport in semiconductors is based on ve equa-
tions. The rst equation, the Poisson equation (Eq. (2.12)) [44, 8], calculates the electrostatic potential
in dependence on the electron n and hole p concentration, the charge density due to defect traps and
xed charges
trap
, and the concentration of ionized donors N
d
and acceptors N
a
:
= q(p n +N
d
N
a
)
trap
. (2.12)
In Eq. (2.12), is the dielectric constant of the respective material. The electron and hole concentrations
can be calculated by the Boltzmann relation at thermal equilibrium:
n = n
i
exp
_
q( )
kT
_
(2.13)
p = n
i
exp
_
q( )
kT
_
, (2.14)
where n
i
is the intrinsic charge carrier concentration, which is temperature dependent, k is Boltzmanns
constant, T is the absolute temperature, and is the Fermi potential. The two additional equations to be
solved for simulating charge carrier transport are to calculate the electron and hole current densities J
n
and J
p
. However, the calculation of the current densities is dependent on the respective charge carrier
transport simulation method, e.g. Drift-Diffusion, Hydrodynamic, or Monte Carlo.
2.2.2.1 Drift-Diffusion Method
The major device simulations in this work were done by conventional Drift-Diffusion simulations, since
they are fast, ensure a reliable convergence behavior, and many models for different physical effects are
already available for this kind of simulation method. As mentioned previously, the calculation of the
current densities of electrons J
n
and holes J
p
is dependent on the respective simulation method that is
used. In the Drift-Diffusion approach, the electron current density J
n
is computed by solving
J
n
= qn
n
F +qD
n
dn
dx
, (2.15)
while the hole current density is calculated by
J
p
= qp
p
F qD
p
dp
dx
. (2.16)
14 2 Fundamentals
In Eqs. (2.15) and (2.16) [44, 8],
n
and
p
are the electron and hole mobilities, F is the electric eld,
which is calculated from the electrostatic potential, and D is the diffusion coefcient of either electrons
(D
n
) or holes (D
p
).
2.2.2.2 Carrier Recombination/Generation
In Subsubsection 2.2.2.1, the basic principles of current transport simulation in semiconductors were
described. In this subsubsection, the simulation model for simulating charge carrier generation and
recombination is briey introduced. Generation of a charge carrier occurs if energy is applied to a
valence electron, higher than the band gap of the semiconductor material (E
g,Si
= 1.12 eV). This valence
electron is shifted into the conduction band and can contribute to the current transport. During the
generation process, a hole in the valence band is generated which can contribute to the current transport
as well. If the electron loses its energy, e.g. due to electro-magnetic wave (photon) or thermal energy
(phonon) emission, it drops back to the valence band energy level and recombines with a hole. The
generation/recombination effect is the absolutely basic effect which differentiates the semiconductor
materials from insulator and conductor materials.
To simulate generation/recombination, the model of Shockley, Read, and Hall is used in this work [45,
44, 31]:
R
SRH
net
=
np n
2
i
n
(n +n
1
) +
p
(p +p
1
)
(2.17)
with
n
1
= n
i
exp
_
E
trap
kT
_
(2.18)
and
p
1
= n
i
exp
_
E
trap
kT
_
. (2.19)
In Eq. (2.17), R
SRH
net
is the generation/recombination rate and
n
and
p
are the carrier life times of elec-
trons and holes, respectively. E
trap
in Eqs. (2.18) and (2.19) is the difference between the quasi Fermi
energy level E
qF
and the trap energy level E
T
(E
trap
= E
T
E
qF
). Equations (2.18) and (2.19) also de-
note that the factors n
1
and p
1
only differ from the intrinsic charge carrier concentration n
i
if traps are
specied in the simulation setup. If no traps are assumed, n
1
and p
1
are equal to n
i
.
2.2.2.3 Mobility Calculation
The impact of, e.g., acoustic and optical phonons, impurities, and surface roughness on the carrier mo-
bility at low electric elds was simulated using several models. Each model calculates a proper mobility,
depending on the effect, respectively. The different mobility factors were nally combined to one low
eld mobility
low
by Matthiessens rule [8, 31]:
1
low
=
1
b1
+
1
b2
+... +
1
s1
+
1
s2
+... . (2.20)
bi
are the bulk mobility contributions and
si
are the surface mobility partitions [31].
One contribution to the total carrier mobility, calculated by the simulation software, is the so called
constant mobility
const
, which already includes the mobility reduction due to optical phonons and a
temperature dependence:
const
=
L
_
T
300K
_
. (2.21)
The maximum mobility reachable by the carriers in undoped bulk silicon is given in Eq. (2.21) by
L
.
is a tting exponent which is typically 2.5 and 2.2 for electrons and holes, respectively [31].
The impact of doping on the charge carrier mobility was calculated by the Masetti [46] model in this
work:
dop
=
min1
exp
_
N
c
N
a
+N
d
_
+

const
min2
1 + ((N
a
+N
d
)/N
r
)

1
1 + (N
s
/(N
a
+N
d
))
. (2.22)
Here,
min1
,
min2
, and
1
are tted reference mobilities [46], N
c
, N
r
, and N
s
are tted reference doping
concentrations [46] and and are tting exponents [46, 31]. N
a
and N
d
are the acceptor and donor
concentrations. The rst two terms in Eq. (2.22) characterize the "min-max" behavior of the mobility at
increasing doping concentrations. The third term, which is neglected at a doping concentration below
5 10
19
cm
3
, accounts for the decreasing mobility at the highest doping level [46].
To take scattering effects due to surface roughness at the silicon/oxide interface into account, the model
proposed by Lombardi [47] was used. In this model, not only the effect of surface roughness is calculated,
but also the inuence due to acoustic phonon scattering is regarded. The impact on the mobility due to
surface roughness is expressed by
sr
=
_
(F
/F
ref
)
Z
+
F
3
_
. (2.23)
In Eq. (2.23) [47, 31], F
is the transverse electric eld normal to the gate oxide surface, F

ref
is the
reference eld of 1 V/cm, and and are t parameters extracted from experiments [47]. In the original
Lombardi model, the exponent Z
was set to a value of 2 [47], but was adjusted in SDevice [31] by

Z
= Z +

(n +p)N
ref
(N
a
+N
d
+N
1
)
. (2.24)
Z is equal to 2, like in the original Lombardi model [47], N
ref
is a reference doping concentration of
1 cm
3
. N
1
, , and
are t parameters [31].

As already mentioned, the Lombardi model also includes the effect of acoustic phonon scattering. This
contribution to the mobility limiting mechanisms is calculated by
ac
=

F
+
((N
a
+N
d
)/N
0
)
F
1/3
(T/300K)
. (2.25)
Here, , , , and are tting parameters [47, 31].
In addition, a factor D is used in the nal implementation of the low-eld mobility. D is dened as
D= exp(x/l
crit
), where x species the distance from the silicon/oxide interface and l
crit
is a t param-
16 2 Fundamentals
eter [31]. This factor is nally used in Matthiessens rule as nominator in the surface roughness
sr
/D
and the acoustic phonons
ac
/D mobility impact.
The last contribution to the low eld mobility is given by the effect of carrier-carrier scattering. Here,
the model of Choo [48] and Fletcher [49] was used:
cc
=
(T/300K)
3/2
np
_
ln
_
1 +
_
T
300K
_
2
(pn)
1/3
__
1
, (2.26)
where and are t parameters.
The low eld mobility can nally be calculated by
1
low
=
1
const
+
1
dop
+
1
sr
D
-1
+
1
ac
D
-1
+
1
cc
. (2.27)
The low-eld mobility determines the drift velocity of the carriers at low electric elds. The drift velocity
v
drift
is expressed by a product of the low-eld mobility and the electric eld F that acts on the carriers:
v
drift
=
low
F . (2.28)
According to Eq. (2.28), the drift velocity increases if the electric eld increases. However, at high
electric elds (> 10
6
V/cm) a saturation of the carrier velocity is observed in silicon. The saturation
of the carrier drift velocity can be explained by the increasing probability of scattering events between
carriers and phonons or impurities. To model this effect, the Caughey-Thomas [50] model was used in
this work (Eq. 2.29). This model assumes a velocity convergence to a xed saturation velocity v
sat
at
innitely high electric elds, which cannot be exceeded:
high
=

low
_
1 +
_
low
F
v
sat
_
_
1/
. (2.29)
The parameter in the Caughey-Thomas model (Eq. (2.29)) is a t parameter, which amounts to 1.1 for
electrons and 1.2 for holes. For electrons in silicon, v
sat
is 1.0 10
7
cm/s and for holes 0.85 10
7
cm/s [50].
2.2.2.4 Quantum-Mechanical Depletion
Due to the very small dimensions of the transistors investigated in this work, quantization of the charge
carriers at the silicon/oxide interface cannot be neglected anymore [51]. The quantization leads to a
shift of the threshold voltage of about 20 mV to 100 mV and lowering of the drive current. Furthermore,
the gate capacitance is lowered, since the effective dielectric thickness is increased by the quantization
effects. To account for this effect, the modied local density approximation (MLDA) represents a feasible
simulation model, because it is a fast and steady converging method [31, 52]. The MLDA assumes a
triangular potential at the silicon/insulator interface which acts as a quantum well for the charge carriers.
Thereby, the depletion region below the gate oxide increases, as the charge carrier concentration at the
silicon/insulator interface is lowered in comparison to the classical charge carrier distribution in the
inversion layer. The conned charge carrier density at the silicon/oxide interface can be calculated by
n
MLDA
(z,
n
) = N
C
_
2
__

0
d
1 + exp[(
n
)]
[1 j
0
(2z
/
n
)]. (2.30)
In Eq. (2.30), z is the distance from the silicon/oxide interface, n
MLDA
represents the quantum conned
charge carrier density at the silicon/oxide interface,
n
the energy difference between the conduction
band and the quasi-Fermi potential of electrons, j
0
the Bessel function of the 0-th order, and
n
the
electron thermal de Broglie wavelength [31].
2.2.2.5 Schottky Contact Resistances
A further effect to be taken into account if sub-50 nm scaled CMOS devices are simulated are Schottky
contact resistances of the silicon/metal transition at the source/drain contact regions. It is shown in the
literature that these contact resistances are limiting the static and dynamic behavior of transistors all-out
if the geometrical dimensions continue to be scaled down [51, 53, 54, 8]. The resistivity of the contacts
results from the Schottky barrier at the silicon/metal interface. The contact resistances are dependent on
the active doping concentration at the silicon/metal interface, the contact area, and the Schottky barrier
height
B
[54, 8]. Thus, a Schottky contact model is used in the device simulation of small size CMOS
transistors [55, 31]. The model calculates a voltage drop at the silicon/metal interface due to the contact
resistance R
co
. According to the Schottky contact theory, applied to the metal/silicon interface into
account, R
co
can be expressed by
R
co
= R
300 K
T
0
exp
_
q
B
E
0
_
, (2.31)
where E
0
can be calculated by
E
0
= E
00
coth
_
E
00
kT
0
_
(2.32)
and E
00
is determined by
E
00
=
qh
4
|N
d
N
a
|
s
m
t
. (2.33)
In case of Eqs. (2.31), (2.32), and (2.33) [55], R
is the Schottky resistance at an innity high doping

concentration (or zero Schottky barrier
B
),
s
is the permittivity of the semiconductor material, m
t
is
the tunneling mass, and T
0
is the lattice temperature. The current density at the metal/silicon interface
over the contact area s and voltage drop at the contact (V
applied
-) can nally be expressed by
_
s
n [
J
p
(
F
) +

J
n
(
F
) +

J
D
(
F
)]ds =
(V
applied
)
R
co
. (2.34)
V
applied
in Eq. (2.34) is the voltage applied at the contact,

J
n
,

J
p
, and

J
D
are the electron, hole, and
diffusion current densities in semiconductor near the contact surface, respectively, is a t parameter,
and n is the contact surface normal pointing into the contact materials.
18 2 Fundamentals
2.2.2.6 Mechanical Stress
Mechanical stress has become a common performance booster for improving the electrical behavior of
CMOS devices in the last years. Due to the shrinking device area A, the mechanical stress increases
at decreasing dimensions ( = F/A) if the force F stays at a constant level. It was reported in several
works that mechanical stress can improve the charge carrier mobility [27]. Especially tensile stress along
the channel direction improves the electron mobility, while compressive stress along the channel leads
to an improvement of the hole mobility [27]. To take the impact of mechanical stress on the charge
carrier mobility into account in the device simulation, several models were developed and presented [56,
30, 57]. The impact of mechanical stress on the electron mobility was calculated in this work using the
deformation potential model (Eq. (2.35)) [58, 31, 59]. According to this model, conduction and valence
band energies of silicon are shifted when stress is applied:
E
C,i
=
d
(
11
+
22
+
33
) +
u
ii
E
V,i
= a(
11
+
22
+
33
) + E (2.35)
E =
_
b
2
2
((
11
22
)
2
+ (
22
33
)
2
+ (
11
33
)
2
) + d
2
(
2
12
+
2
13
+
2
23
) .
In Eq. (2.35),
kl
is the strain rate tensor (Eq. (2.9)) and
d
,
u
, a, b, and d are the deformation poten-
tials [58, 31]. E
C,i
and E
V,i
nally dene the energy shift of the respective conduction and valence
energy sub-bands i. The change in the band gap directly inuences the effective masses of the charge
carriers and the effective density of states in the conduction and valence bands [59]. The charge carrier
mobility can be calculated by
low
=
v
drift
F
=
q
2m
, (2.36)
where is the carrier life time and F is the electric eld. Therefore, the mobility is inuenced by
mechanical stress, since the effective masses m
of the carriers are modied by mechanical stress.

In the literature, the deformation model is also proposed to be used for the stress affection of the hole
mobility. In the manual of the simulation tool SDevice [31], however, it is proposed to use the Intel
model [56] for the impact of mechanical stress on the hole mobility. But, it could be shown in this work
(Chapter 4) that the Intel model has a limited eld of application in realistic CMOS device simulations.
Therefore, a modied model for the impact on the hole mobility by mechanical stress is presented in
Chapter 4.
2.3 SPICE Simulations
The evaluation of different MOSFET architecture also includes the study of how different CMOS de-
vices behave under integrated circuit conditions. SPICE (Simulation Program with Integrated Circuit
Emphasis) simulations offer the best possibilities for efcient circuit simulations. As the SPICE method
is based on analytical models, they have the advantage of being fast, ensure reliable convergence behav-
ior, and are able to simulate even complex circuits with hundreds of devices. In this work, the software
HSPICE of Synopsys was used for the circuit simulation part [60].
2.3 SPICE Simulations 19
2.3.1 Basic Principles
SPICE simulations are based on so called compact models. Compact models are an analytical description
of a device, e.g. resistors, capacitors, inductors, but also active devices as diodes, bipolar transistors, and
MOSFETs. They dene, e.g., how the device behaves if voltage is applied, under temperature, or which
kind of noise the device produces [60]. The circuit description is done in netlist les. These netlists are
based on circuit theory. Like it is common in circuit theory, devices are plugged together by dening
nodes at the electrodes of devices. By solving the Kirchhoff equations at each node in the circuit, the nal
behavior is calculated. Therefore, these simulations offer the possibility to observe the circuit behavior
not only at the input nodes or output nodes, but also in between different gates or devices, which is rather
complicated in experiments. SPICE simulations offer besides circuit simulations also the possibility to
do so called worst cases analysis of a circuit. Thereby, critical device parameters are varied by a Monte
Carlo approach. The Monte Carlo method uses a given distribution for a specic parameter, e.g. the low
eld threshold voltage of a MOSFET, and simulates the circuit for a given number of variations. After
each simulation run the critical parameter is randomly changed again within the given distribution and
the simulation is started again. Thus, efcient variability studies of circuit behavior under, e.g. process
variations, are possible.
2.3.2 Compact Models
The most famous and commonly used compact models are the BSIM models [61]. However, the BSIM
models have several disadvantages, especially if the behavior of new device architectures with gate
lengths below 50 nm should be reproduced [62]. Therefore, it was decided to use the EPFL-EKV com-
pact model [63] in this thesis. The EKV MOSFET model was designed for sub-micron CMOS technolo-
gies especially for low-power circuits. Compared to BSIM, it has the advantage of low complexity and
of a symmetrical behavior of the MOSFET devices, with respect to the source/drain capacitances [62],
which is not given by BSIM models. Although the EKV model is a compact model for describing bulk
MOSFETs, it also offers the possibilities to reproduce the electrical behavior of SOI devices. A detailed
description of the model, as well as the equations solved during the simulations can be found in the EKV
manual [63].
20 2 Fundamentals
Chapter 3
Simulating Quasi-Ballistic Carrier
Transport
The main part of this thesis is the investigation of modern sub-50 nm scaled CMOS devices by numerical
device simulations. Consequently, valid charge carrier transport models have to be used to draw accurate
conclusions about the electrical performance. One effect to be taken into account if charge carrier trans-
port in sub-50 nm gate length MOSFET devices should be simulated, is velocity overshoot [8]. In long
channel MOSFET transistors, the charge carriers are accelerated by an electric eld, but are scattered on
or deected by acoustic and optical phonons, impurities, and the surface. Consequently, the charge car-
riers lose energy, which is partly absorbed by the silicon lattice and converted into phonons again. Due
to this effects, a thermal equilibrium between the charge carriers and the silicon lattice is established.
Furthermore, scattering and deection lead to a maximum drift velocity v
drift
the charge carriers could
reach, which saturates at 1 10
7
cm/s [8] and is, therefore, called saturation velocity v
sat
. In short channel
MOSFETs, of approximately 250 nm and below [8], some of the charge carriers are not able to get into
thermal equilibrium with the silicon lattice. The reason for this effect is a decreasing probability of scat-
tering and deection of the charge carriers, because of the smaller distance to be covered. These carriers
are called hot carriers. Due to the fact that hot carriers are not in thermal equilibrium with the silicon
lattice, they are able to exceed the saturation velocity. From the literature, this effect is well known as
velocity overshoot [8]. By further scaling down the channel length, the amount of hot carriers continu-
ously increases, because of decreasing scattering and deection probability. Even some of the carriers
may pass the channel without being scattered. At channel lengths of 80 nm and below, the expression
of quasi-ballistic charge carrier transport came into play, as part of the carriers perform a quasi free
ight through the channel, while the other part is still scattered or deected [64]. If the channel length
is scaled down below the mean free path of optical phonons, which is in bulk silicon 7.6 nm [44], it can
be assumed that no scattering or deection of the charge carriers happens anymore. Then, the term of
ballistic charge carrier transport is used in the literature [64]. Due to the decreasing probability of scat-
tering and the velocity overshoot, device engineers observed a notable enlargement of the on-current and
the transconductance [8]. Thus, a discussion about quasi-ballistic and ballistic MOSFETs as a chance
for nano-electronics has started [65]. In this thesis, the channel lengths of the investigated MOSFET
devices are in the range of quasi-ballistic channels. However, the possibility of the used charge carrier
21
22 3 Simulating Quasi-Ballistic Carrier Transport
Figure 3.1 Comparison between HD, MC, DD simulations, and experimental results
transport simulation models has to be ensured or to be created to take the effect of drift velocities above
the saturation velocity into account. Most of todays Monte Carlo (MC) simulation tools are already
able to simulate this effect [31]. However, Monte Carlo device simulations have several disadvantages
in terms of computation time and exibility concerning the plugin of different physical effects like, e.g.
mechanical stress, quantum mechanical depletion, and contact resistances, which are important for sim-
ulating modern CMOS devices. Another possibility would be to use the Hydrodynamic (HD) transport
model. But, it is shown in the literature that, in most cases, the Hydrodynamic transport model conse-
quently overestimates the on-current (Fig. 3.1), especially at small gate lengths [66]. Furthermore, the
convergence behavior of the Hydrodynamic transport model worsens, if the complexity of the simula-
tion setup increases. Drift-Diffusion (DD) simulations, on the other hand, offer great advantages in all
mentioned points. Todays DD tools, however, are not able to take quasi-ballistic charge carrier transport
into account and, therefore, consequently underestimate the drive currents of modern MOSFETs, if DD
simulation results are compared to experiments and MC simulations (Fig. 3.1).
This chapter aims at presenting a novel modication of the conventional Drift-Diffusion transport model
to take quasi-ballistic charge carrier transport under high-eld conditions into account. The main model
requirements are a fast converging behavior at low computational effort and the ability to reproduce
experimental results, well as Monte Carlo simulation results.
3.1 A Field Dependent Saturation Velocity for sub-50 nm Channel
Lengths
The rst proposal for including the effect of velocity overshoot into the classical Drift-Diffusion trans-
port model was made by Bude [19]. Bude compared DD simulations to MC simulations at physical gate
lengths down to 40 nm and proposed to raise the saturation velocities of electrons and holes in the DD
approach up to 2.2 10
7
cm/s and 1.5 10
7
cm/s, respectively. Thus, he was able to achieve a good agree-
ment between MCsimulations and DDsimulation results. Asecond proposal was made by Granzner [66]
3.1 A Field Dependent Saturation Velocity for sub-50 nm Channel Lengths 23
who suggested an equation for calculating the saturation velocities in dependence on the physical gate
length. These values for the saturation velocities, however, were veried only for gate lengths down
to 40 nm, as well as for a constant supply voltage and constant doping concentration. This work, in-
stead, aims at nding a DD transport model modication valid for different geometrical shapes, doping
concentrations, and supply voltages. It should work, therefore, for any kind of MOSFET device.
Based on the work of Bude [19] and Granzner [66] a closer look at the saturation velocity was taken
in this work. Both, Bude and Granzner found the saturation velocity v
sat
, used in the Caughey-Thomas
model (Eq. (2.29)) [50] for high-eld saturation, of the carriers to be too small for modern sub-50 nm
CMOS devices. The saturation velocity in undoped silicon follows the equation [8]:
v
sat
=
_
8E
Ph
3m
, (3.1)
where E
Ph
denotes the optical phonon energy ( 0.063 eV in silicon [44]) and m
the effective mass

of a charge carrier. Equation (3.1) already indicates that the limiting factor for the carrier velocity are
scattering events due to the presence of optical phonons. By Eq. (3.1), the saturation velocity can be
calculated to be 1 10
7
cm/s for electrons and 8.5 10
6
cm/s for holes [31]. Furthermore, Eq. (3.1) is only
applicable for charge carriers which are in thermal equilibrium with the silicon lattice. If hot carriers are
considered, a different approach for the maximum drift velocity has to be found.
When talking about quasi-ballistic carrier transport, one has to start with the assumption that some elec-
trons are accelerated in the channel without being scattered. On the other hand, there must be a limiting
factor for the carrier velocity anyway, as electrical measurements of the output characteristics of sub-
50 nm scaled MOSFETs show a saturation behavior of the drain current. Therefore, the only limiting
factor for the charge carrier velocity is the channel length [20]. It denes the maximum acceleration
distance, and the driving force from the electric eld in the channel, which acts on electrons. Because
the DD transport model uses a position dependent approach, a proper way to simulate the nal veloc-
ity of carriers at the end of the channel is to calculate the velocity at each point in the channel region.
By a classical mechanical approach, the velocity can be calculated by transforming the potential energy
of electrons into kinetic energy, by the law of energy conservation. The potential energy itself can be
expressed by
E
pot
(x) =
_
q(x) for electrons
q(x) for holes ,
(3.2)
where q is the elementary charge and (x) is the electrostatic potential at a certain point x along the
channel. The potential energy can be translated, keeping in mind the law of energy conservation, into a
kinetic energy E
kin
(x):
E
pot
(x
0
) E
pot
(x) = E
kin
(x), (3.3)
where E
pot
(x
0
) denotes the initial energy (at the channel beginning) and E
pot
(x) is the potential energy
at the point x in the channel.
Considering the fact that valence electrons in silicon are not free in the channel region, a model that
regards non-parabolicity has to be used to correctly correlate the potential energy to the kinetic electron
energy. Here, the spherical model [67] is used for the energy bands non-parabolicity:
E
kin
(E
kin
+ 1) =
h
2
k
2
2m
. (3.4)
In Eq. (3.4), denotes the non-parabolicity factor, which is in the range of 0.3 eV
1
to 0.5 eV
1
, and k
denotes the wave vector. The propagation velocity of electrons can be expressed by the group velocity
v
g
of electrons [67]:
v
g
(E
kin
) =
1
h
dE
kin
dk
. (3.5)
After solving Eq. (3.4) for E
kin
(k) and taking the derivative, the group velocity depending on the kinetic
energy E
kin
is obtained:
v
g
(E
kin
) =
_
2
m
_
E
kin
(E
kin
+ 1)
2E
kin
+ 1
. (3.6)
E
kin
can be substituted by E
pot
(x
0
) E
pot
(x), using Eqs. (3.3) and (3.6). Therefore, the position depen-
dent expression for the group velocity of the charge carriers can be expressed by
v
g
(x) =
_
2
m
_
(E
pot
(x
0
) E
pot
(x))((E
pot
(x
0
) E
pot
(x)) + 1)
2(E
pot
(x
0
) E
pot
(x)) + 1
. (3.7)
In standard MOSFET architectures the absolute value of the electrostatic potential increases over the
channel length. By calculating the velocity v
g
(x) at every point x along the channel region, an acceler-
ation of the electrons along the channel can be simulated, since the velocity increases in relation to the
electrostatic potential.
The saturation velocity in bulk silicon should not be changed itself, but an expression for its increase
in sub-50 nm CMOS devices should be found. Therefore, the gain of the saturation velocity v
sat
over
the default v
sat,0
for bulk silicon is calculated. Equation (3.3) denotes that the kinetic energy can be
calculated by the change of the electrostatic potential between a point x and a point of reference x
0
.
In this case, x
0
is at the beginning of the channel, where the electrons are in thermal equilibrium and
the electrostatic potential can be set to nearly zero. Hence, the so called built in potential
b
(x), which
depends on the doping concentration, can be subtracted from the complete electrostatic potential for
taking only the acceleration in the channel region into account:
E
pot
(x) = q((x)
b
(x)). (3.8)
By means of subtracting
b
(x) from (x), it is ensured that the potential energy is approximately set
to zero at the source region and increases in the channel region where the electric eld should affect
the electrons. Therefore, the constant potential energy E
pot
(x
0
) can be set to zero, which leads to the
substitution of E
kin
(x) = E
pot
(x). That leads to a new denition of Eq. (3.7):
v
g
(x) =
_
2
m
_
E
pot
(x)(E
pot
(x) 1)
1 2E
pot
(x)
. (3.9)
3.2 Current Saturation due to Self-Heating 25
According to this, a relation for the increase of the saturation velocity v
sat
can be dened by
v
sat
(x) =
_
_
0 for E
pot
(x) = 0
0 for |v
g
(x)| v
sat,0
v
g
(x) v
sat,0
for |v
g
(x)| > v
sat,0
.
(3.10)
The saturation velocity only changes, if the group velocity of charge carriers v
g
(x) is greater than the
default saturation velocity v
sat,0
, like it is specied by Eq. 3.10. Therefore, the improved position
dependent saturation velocity v
sat
is calculated by
v
sat
(x) = v
sat,0
+v
sat
(x). (3.11)
Since v
sat
(x) is added to v
sat
, the effective masses of electrons and holes used in Eq. (3.1) have to be
used for the calculation of the group velocity. Therefore, m
in Eq. (3.7) was set to 0.78 m

0
and 1.09 m
0
for electrons and holes, respectively, like they are used in SDevice [31].
The new saturation velocity v
sat
(x) of Eq. (3.11) is regularly used in the Caughey-Thomas
model (Eq. (2.29)) [50] for the local electron and hole mobility
high
(x) under high electric eld condi-
tions:
high
(x) =

low
(x)
_
1 +
_
low
(x)F(x)
v
sat
(x)
_
_
1/
. (3.12)
The implementation of the discussed changes of the saturation velocity and the Caughey-Thomas
model (3.12) is accomplished in a so called Physical Model Interface (PMI) of SDevice [31], which
can simply be included in the device simulation setup le [31].
3.2 Current Saturation due to Self-Heating
When talking about quasi-ballistic charge carrier transport in sub-50 nm CMOS devices, it has to be
noted that the effect is only valid in the channel region. If the charge carriers enter the heavy doped drain
region they are intensively scattered and lose their kinetic energy. This energy loss can be taken into
account by using the model of self-heating in the device simulation, as in the long run the lost kinetic
energy is absorbed by the silicon lattice in the form of heat. The temperature dependence of the charge
carrier mobility in Eq. (3.12) is, thereby, given by the low eld mobility
low
(x). To simulate self-heating
of CMOS devices, a thermal resistance network of material specic thermal resistances was used, like
shown in Fig. 3.2. The network, which is presented here, is designed for a SOI MOSFET, but can also be
extended for conventional bulk CMOS devices, by skipping the thermal resistance for the buried oxide
(BOX) R
th,tbox
and the silicon body thickness R
th,tbody
.
Figure 3.2 Thermal resistance network
The material related thermal resistances R
th
dened below can be expressed by
R
th
=
t
m
A
m
m
, (3.13)
where t
m
species the material thickness, A
m
the material area, and
m
the thermal conductivity of the
material [44].
In the SOI case (Fig. 3.2), the thermal resistances R
th,thermode
at the respective thermodes [31] can be
determined by
R
th,gate
= R
th,gatemetal
+R
th,tox
R
th,source
= R
th,metal
+R
th,1/2L
body
R
th,drain
= R
th,source
(3.14)
R
th,bulk
= R
th,tbody
+R
th,box
+R
th,substrate
.
Finally, the self-heating of the device is calculated on the basis of thermal power dissipation P
th,diss
,
which is known from the voltage and current at the electrodes [31]:
P
th,diss
=
T T
0
R
th,compl
. (3.15)
In Eq. (3.15), T is the temperature inside the device and T
0
is the ambient temperature, which by default
is 300 K [31].
3.3 Comparison of the Advanced Drift-Diffusion Model to Monte Carlo Simulations 27
The nal temperature T
i
inside the device, is determined by an iteration procedure:
T
i+1
= P
th,diss
i
R
th,compl
+T
0
, (3.16)
where P
th,diss
i
is the power dissipation in i-th iteration and T
i+1
is the temperature, to be computed for
the next iteration step. P
th,diss,0
is rst calculated at 300 K, then T
1
is achieved by solving Eq. (3.16), etc.
The whole procedure of adjusting the saturation velocity by an approximation of carrier acceleration and
taking the kinetic energy loss at the channel/drain interface into account by simulating the self-heating
of the device as described above, will, in the following, be referred to as the Advanced Drift-Diffusion
(ADD) model.
3.3 Comparison of the Advanced Drift-Diffusion Model to Monte Carlo
Simulations
First of all, the new carrier transport model is compared to Monte Carlo simulations. In the simulation
experiment, the Monte Carlo software MOCA [31] was used. Comparisons to further MC simulation
tools were also carried out during this thesis and are presented in the literature [68].
3.3.1 MOSFET Scaling Methodology
For investigating how the effective carrier saturation velocity behaves under scaling conditions, fully
depleted silicon on insulator (FDSOI) NMOS and PMOS transistor TCAD models with gate lengths
between 50 nm and 10 nm were used. Three scaling scenarios were examined. At rst, a constant eld
scaling scenario was assumed, where the geometrical dimensions and the supply voltage were reduced
by a scaling factor , while the doping concentrations of the source/drain and channel regions were
increased by . was calculated by L
gate,new
/L
gate,old
. Thereby, the gate lengths were scaled, starting at
a length of 50 nm, down to 10 nm, using 5 nm steps. Instead of scaling down the gate voltage V
gate
by
as well, the gate voltage V
gate
was increased at each step by a factor of 1.01 while the drain voltage
V
drain
was decreased by . In this way, as far as possible, short channel effects were compensated and
an almost constant gate-overdrive (V
gate
V
th
) was guaranteed. In the second scaling scenario, the same
scaling parameters mentioned previously were used, but the gate and the drain voltage were held at a
constant level of 1.5 V. Finally, nine ITRS technology nodes, 80 nm down to 32 nm (L
gate
=32 nm to
13 nm) [69], were chosen and the device dimensions and supply voltage were scaled as proposed by the
ITRS [69]. The doping concentrations were chosen and scaled as in the preceding scaling scenarios. All
scaling parameters are listed in Tab. 3.1. In Tab. 3.1, L
gate
denotes the dimensions for the physical gate
length, t
ox
the gate oxide thicknesses, t
body
the silicon body thicknesses, and f
N
the multiplier for the
initial doping concentrations of 1 10
15
cm
3
in the channel region and 1 10
20
cm
3
for the source and
drain regions, respectively.
3.3.2 Device Simulation Models
Several standard models, which were already discussed in Chapter 2, were used in the DD simulation
and MC simulation setups. Furthermore, the metal1 gate work functions in the DD setup and the MC
setup were adjusted to get comparable threshold voltages, for assurance of comparable simulation condi-
tion. After the simulation runs, the saturation currents of both simulations were extracted and compared
Table 3.1 Device dimensions for different scaling scenarios
Scaling L
gate
(nm) t
ox
(nm) t
body
(nm) V
drain
(V) f
N
50 1.5 12.5 1.5 1.0
45 1.35 11.25 1.35 1.11
40 1.18 10.0 1.18 1.26
35 1.04 8.75 1.04 1.44
Constant eld scaling 30 0.88 7.5 0.88 1.7
25 0.73 6.25 0.73 20.0
20 0.58 5 0.58 25.0
15 0.44 3.75 0.44 34.0
10 0.3 2.5 0.3 50.0
32 1.9 8 1.1 1.0
28 1.8 7 1.1 1.14
25 1.8 6.3 1.1 1.27
22 1.7 5.5 1.0 1.44
ITRS [69] 20 1.6 5 1.0 1.58
18 1.1 4.5 1.0 1.76
16 1.0 4 1.0 1.98
14 0.9 3.5 0.9 22.6
13 0.9 3.3 0.9 24.3
to each other. Thereby, the saturation current of the DD simulations were extracted from transfer charac-
teristics. Because Monte Carlo calculates the saturation current at a xed supply voltage in an iterative
procedure of the electrostatic potential and charge carrier distribution (1500 iterations were done), the sat-
uration current values were averaged over the last 900 iterations, when the electrostatic potential reached
a quasi-stationary state.
3.3.3 Simulation Results
The simulation results of the DD-MC comparison are displayed in Fig. 3.3. In each scaling case, the
conventional DD model (dashed line) underestimates the saturation current, compared to the MC simu-
lations (circles), like already reported in the literature [19, 66, 70]. Figures 3.3(a) and 3.3(b) display the
results of the rst scaling case, by scaling the drain voltage by the same factor like the geometrical di-
mensions and increasing the gate voltage by a factor of 1.01 in each scaling step. Here, the x-axis denotes
the physical gate length in nm, while the y-axis indicates the on-current values in A/m. In this case,
a very good correlation between the ADD model, which is denoted by the solid line, and Monte Carlo,
which is shown by the circles, was achieved for the on-current values, as well for the NMOS (Fig. 3.3(a))
as for the PMOS (Fig. 3.3(b)) device.
Figures 3.3(c) and 3.3(d) show the on-current results of scaling down the geometrical dimensions, by
holding the supply voltage at a constant value of 1.5 V. Here, a small deviation of the ADD model from
the simulation results of MOCA can be observed. For gate lengths below 20 nm, the ADD model slightly
underestimates the on-current in both cases, NMOS (Fig. 3.3(c)) and PMOS (Fig. 3.3(d)), in comparison
to MOCA. It seems that the ADD model, due to its analytical behavior, is not able to handle the situation
as accurate as Monte Carlo for high biased devices with gate lengths below 20 nm and very thin gate
3.3 Comparison of the Advanced Drift-Diffusion Model to Monte Carlo Simulations 29
(a) (b)
(c) (d)
(e) (f)
Figure 3.3 Comparison between the default DD model (dashed lines), MC simulations (circles) and the ADD
model suggested in this work (stars): (a) Constant scaling scenario: NMOS; (b) Constant scaling scenario:
PMOS; (c) Constant V
DD
scenario: NMOS; (d) Constant V
DD
scenario: PMOS; (e) ITRS scaling scenario:
NMOS; (f) ITRS scaling scenario: PMOS
oxide thicknesses. However, due to the improvement of the DD model, a more sufcient approximation
of the on-current was reached [69], in comparison to the conventional Drift-Diffusion model. In the third
case, using ITRS specications, a relatively good correlation of the ADD simulation results to the MC
results was achieved for both types of devices, NMOS (Fig. 3.3(e)) and PMOS (Fig. 3.3(f)). On average,
the deviation of the ADD from the MC results amounts to 10%, while the deviation of the DD and the
MC results is about a factor of 2.
3.4 Comparison of Simulation and Experimental Results
More important than comparing the model to Monte Carlo simulation tools is the comparison to exper-
imental results. Two examples from the literature were chosen to prove the validity of the ADD model.
The rst example from the literature is a FDSOI MOSFET with a physical gate length of 40 nm [3]. The
simulation setup used to simulate this device is described in detail in the literature [51, 68]. At this point,
it has to be mentioned that several physical effects such as quantum mechanical depletion, mechani-
cal stress due to electrode silicidation, and contact resistances were taken into account in the simulation
setup. The channel of the measured MOSFET was kept undoped. Therefore, the electrostatics of the
device is only dependent on the doping concentration, the position of the source/drain extensions, and
the device geometry [3]. In the simulation of the source/drain implantation, standard setups were used.
The ion dose and energy were assessed by tting the subthreshold behavior. Figure 3.4(a) shows the
linearly scaled transfer characteristics of these MOSFETs from measurement (circles) and simulations
(solid line). The threshold voltages correspond very well in the low drain biased case and in the high
drain biased case. Furthermore, the shape of the simulated characteristic ts perfectly to the experi-
mental results. The same behavior can be observed in the semi-logarithmic scaled transfer characteristic
(Fig. 3.4(b)). An advantage of the ADD model is highlighted in Fig. 3.5, which shows the output char-
acteristics. From the literature it is known that Monte Carlo simulations have the problem of showing a
non-saturation behavior compared to measurements (Fig. 3.1). In measurements, a complete saturation
of the slope of the drive current can be observed above approximately 0.6 V. In MC simulations, how-
(a) (b)
Figure 3.4 Comparison of the ADD model to experimental results: 40 nm gate length FDSOI [3]; squares:
experiment at V
drain
=0.1 V and 1.25 V; solid lines: simulation; (a) Transfer characteristic linearly scaled; (b)
Transfer characteristic semi-logarithmic scaled
3.4 Comparison of Simulation and Experimental Results 31
Figure 3.5 Comparison of the ADD model to the measured output
characteristic: 40 nm gate length FDSOI [3]; squares: experiment at
V
drain
=0.1 V and 1.25 V; solid lines: simulation
ever, the slope of the output characteristic also changes at 0.6 V, but does not saturate completely. Due
to the self-heating effect in the ADD model, the saturation behavior of the output characteristic at high
drain voltages matches very well to the measured characteristic (Fig. 3.5).
The second example chosen from the literature is a FDSOI with a physical gate length of 25 nm [18].
Because the process ow of the device is similar to the ow of the MOSFET discussed before [18, 3], al-
most the same process and device simulation setups could be used for the second example, like for the
rst one. The second MOSFET points out three major differences compared to the rst example. First of
all, the physical gate length is 25 nm, the gate oxide thickness is 1.2 nm, and the buried oxide is 170 nm.
Furthermore, the source/drain regions were elevated by SEG. Finally, nickel silicide was used for silici-
Figure 3.6 Mechanical stress in the channel region of the SOI MOS-
FET [18] after silicidation, calculated by process simulation
dating the source/drain contacts and the gate electrode [18]. According to process simulations, it could
be shown that the nal mechanical stress in the channel region is negligible, due to stress compensation,
because of the full silicidation of the poly-silicon gate. Figure 3.6 displays the mechanical stress distribu-
tion after the silicidation of the source/drain contacts and the gate electrode along the channel, calculated
by process simulation. The nal stress in the channel region was calculated to be approximately in the
range of 20 MPa tensile and 20 MPa compressive stress. Therefore, no signicant mobility enhancement
is achieved by these small values of mechanical stress [30]. A more detailed discussion about the topic
of mechanical stress is presented in Chapter 4. Additionally, it has to be mentioned at this place that two
devices of 64 nm width and 2 m width, respectively, are discussed in the publication [18]. To exclude
narrow width effects in this work, the experimental results of the MOSFET of 2 m width was used for
comparison to simulations.
Figure 3.7 combines the transfer characteristics of the NMOS and PMOS presented in [18]. Thereby,
Fig. 3.7(a) shows the linear scaled transfer characteristic and Fig. 3.7(b) the semi-logarithmic scaled.
Like already shown in case of the rst device discussed, the behavior is well reproduced and the simulated
curves match the measured ones very well.
(a) (b)
Figure 3.7 Comparison of the ADD model to experimental results: 25 nm gate length FDSOI [18]; squares:
experiment at V
drain
=0.05 V and 1.1 V; solid lines: simulation; (a) Transfer characteristic linearly scaled; (b)
Transfer characteristic semi-logarithmic scaled
3.5 Ballisticity Correction Factor
A further physical effect observed in CMOS devices with gate lengths below 100 nm is the reduction of
the effective charge carrier mobility at decreasing gate lengths [20]. This effect was observed and re-
ported the rst time by Shur [20] in high electron mobility transistors (HEMTs) based on GaAs. The
effect of decreasing charge carrier mobility was also observed in silicon MOSFETs [71, 72]. Conse-
quently, Shur dened an additional ballisticity mobility correction factor
bal
, which has to be added by
using Matthiessens rule to the low eld mobility
low
:
1
low
=
1
low
+
1
bal
. (3.17)
3.5 Ballisticity Correction Factor 33
The ballisticity correction factor
bal
[20] itself is determined by the physical gate length and is dened
by
bal
=
2qL
gate
m
v
th
, (3.18)
where v
th
is the thermal velocity [20]:
v
th
=
_
8kT
m
_
1/2
. (3.19)
Equation (3.18) indicates that the ballisticity correction
bal
, and therefore, the whole mobility converges
to zero as the channel length decreases to zero.
Monte Carlo simulations, presented in [73], of silicon MOSFETs showed an average mobility decreases,
even if no Shur correction was assumed [73]. In this simulation experiment [73], a fully depleted silicon
on insulator double gate MOSFET with homogeneous doping proles was used. The gate length was
scaled down from 1 m to 10 nm, while the other parameters were kept on constant value. Then, two
simulation scenarios were addressed [73]. At rst, the double gate MOSFET was simulated with standard
impurity and phonon scattering rates of charge carriers in the channel region [73]. Secondly, a ballistic
channel was assumed by switching off all scattering events in the channel region [73]. The use of the
standard scattering rates led to constant average charge carrier mobility of approximately 500 cm
2
/Vs
until a gate length of 200 nm was reached [73]. At 200 nm an apparent mobility reduction was observed if
the channel length continued to shrink [73]. This effect was also observed in other experiments [72, 71].
The results of the simulations, presented in [73], are shown by the triangles in Fig. 3.8 for channel
lengths of 100 nm to 6 nm. As shown in Fig. 3.8, the average mobility of the simulation experiment
presented in [73] (Fig. 3.8 triangles) converges to zero if the channel length decreases to zero. However,
it was claimed in [73] that this apparent mobility reduction can not be related to ballistic charge carrier
transport, but to non-stationary transport of the charge carriers. If the ballistic channel is assumed,
the average mobility behaves as formulated by Shur [20]. The results of the simulation experiment [73]
using ballistic channels are displayed in Fig. 3.8 and denoted by the solid line. By decreasing the channel
Figure 3.8 Decreasing low eld mobility at decreasing channel lengths
length, the average ballistic mobility converges to zero as well, whereas it tends to innity if the channel
length is increased [20, 73].
A comparable simulation experiment was undertaken in this work using the ADD simulation model. The
device used for the simulations was a single gate (SG) FDSOI device with a very small body thickness of
3 nm, buried oxide thickness of 6 nm and a gate oxide thickness of 1 nm. Due to these small dimensions,
short channel effects were suppressed. The gate length was nally scaled starting from 100 nm down
to 6 nm. The channel of the device was kept undoped, while a homogeneous doping of 1 10
20
cm
3
was assumed in the source/drain regions. The gate voltage was set to 1 V and the drain voltage was
set to 50 mV. The low eld mobility was extracted from the simulated transfer characteristic using a
coupling of Hamers method [74] and the Y-function method [75]. The results of the ADD simulations
are displayed in Fig. 3.8 (circles). As can be seen, the average mobility
0
calculated from the DD
simulations stays at a constant level of approximately 100 cm
2
/Vs until a channel length of 20 nm is
reached. At 20 nm, a degradation of the average mobility was observed which converges to zero, if the
channel length continues to shrink (Fig. 3.8 circles). These results correspond very well to the results of
the Monte Carlo simulations presented in [73]. So, the same effect of non-stationary transport seems to
be the reason for the apparent average mobility reduction in ADD simulations as well.
After the average low eld mobility was extracted, a closer examination of the lateral electric eld along
the channel, originated from the drain electrode, was made. Thereby, the lateral electric eld along the
channel was extracted, integrated over the whole area below the gate and nally divided by the area.
Figure 3.9(a) shows the behavior of the lateral electric eld at constant drain voltages of 50 mV and
decreasing gate lengths. As can be seen, the lateral eld increases approximately with the behavior of
1/L
gate
. The charge carrier mobility itself, on the other hand, is dependent on the electric eld by the
relation given by the Caughey-Thomas model (3.12) [50]. Equation (3.12) species an average mobility
decreases at increasing electric elds, like seen in Fig. 3.8 (circles). To compensate the increase of the
electric eld, the drain voltage was scaled down by the same factor as the physical gate length. Only a
small compensation, however, was achieved by this method, like shown in Fig. 3.9(a) (squares). But for
all that, it was not possible to hold the lateral electric eld at low level at decreasing channel lengths.
(a) (b)
Figure 3.9 Effect of increasing lateral electric eld at decreasing channel lengths: (a) Average lateral eld over
the physical channel length; (b) Low eld average apparent mobility as a function of the lateral electric eld
3.5 Ballisticity Correction Factor 35
The reduction of the lateral electric eld at small gate lengths leads to a shift of the deviation point of the
average charge carrier mobility from 20 nm to approximately 15 nm gate length. This is shown in Fig. 3.8
by the squares. Furthermore, a rise in the average mobility could be observed, starting at 100 nm gate
length till 20 nm was reached. Figure 3.9(b) nally shows the comparison between the average mobility
versus the lateral electric eld along the channel direction for the case of a constant drain voltage (circles)
and the scaled drain voltage (squares). As expected, the average mobility decreases with an increasing
average lateral electric eld in the channel region. Different from the linear decreasing behavior of the
average low eld mobility at constant drain voltages, the average mobility at scaled drain voltages rst
increases at larger gate lengths and small lateral elds and then nally decreases as well (Fig 3.9(b)
squares), as already observed in Fig. 3.8 (squares).
The results presented above lead to the question, if the physical effect of mobility reduction due to de-
creasing channel length and therefore, limited acceleration time of the charge carriers [20], is the reason
for the apparent mobility reduction in silicon? Because the experiments and Monte Carlo simulations,
which have been presented in the literature [20, 71, 72, 73] were carried out at constant drain voltages, the
reason in each case might be the increase of the lateral electric eld, even if a quasi lateral eld correction
by the Caughey-Thomas model (3.12) [50] is used for recalculating the average mobility [73].
Chapter 4
Mechanical Stress
In the previous chapter, the effect of quasi-ballistic charge carrier transport was discussed and how the
effect of minimized scattering probability enhances the charge carrier mobility. Other possibilities for
improving the charge carrier mobility are so called channel engineering methods. Mechanical stress can
be named as one of those more efcient and cheap methods of channel engineering techniques in mod-
ern CMOS device technologies [30]. It is reported in many works that tensile strain along the channel
direction improves the electron low eld mobility, while compressive strain along the channel direction
improves the low eld mobility of holes [27, 57, 30, 76, 77]. To take advantage of strain induced mo-
bility improvement, several process options have been developed for applying mechanical stress on the
channel. Three major techniques are used by the industry. The growth of strained silicon on a SiGe
layer is used to apply tensile stress along the channel direction and, therefore, enhances the performance
of NMOS transistors. For PMOS transistors, germanium is implanted into the source/drain regions to
form SiGe pockets to induce compressive strain along the channel direction. Because of the larger lattice
constant of SiGe than this of silicon, the stress in the channel nally depends on the germanium concen-
tration in the Si
1x
Ge
x
compound. The third method for applying stress to the MOSFET devices is the
deposition of intrinsically stressed nitride layers on the whole MOSFET geometry. These so called stress
liners are normally used as contact etch stop layers (CESL). Dependent on the deposition process, how-
ever, CESLs can either cause tensile stress or compressive stress along the channel direction. Mechanical
stress also occurs during processing of CMOS devices. Every oxidation process or silicidation step, e.g.,
mechanically stresses the MOSFET structure. These process induced mechanical stresses could, in some
cases, negatively impact the transistor performance. For example, if a process step results in compres-
sive mechanical stress in the channel region of a NMOS transistor, the low eld mobility of the electrons
decreases, which leads to lower on-currents and therefore, to higher switching delays.
This chapter aims at developing and adjusting models for silicidation induced mechanical stress, with
a focus on nickel mono-silicide, cobalt di-silicide, and titanium di-silicide. Furthermore, it is shown
how different contact etch stop layer setups might lead to a well controlled mechanical stress along the
channel direction to improve the electron and hole mobility. Finally, existing models for hole mobil-
ity enhancement by mechanical stress were investigated and compared with results from the literature.
Thereby, the simulation models are adapted to be used in commercially available simulation tools.
37
38 4 Mechanical Stress
4.1 Process Induced Mechanical Stress
From the literature, several CMOS process steps are already known to cause mechanical stress in the
MOSFET structure. The forming of shallow trench isolations (STI), silicidation of the source/drain
regions and the gate electrode are the major process steps that cause mechanical stress. In addition,
special process steps to apply mechanical stress to MOSFETs to improve the effective charge carrier
mobility are used by device engineers. To take some of these effects mentioned into account, new
simulation methods were developed in this work, but also state-of-the-art techniques are presented in a
short way as they are important for device simulations under mechanical stress conditions.
4.1.1 Mechanical Stress due to Silicidation
The silicidation of the source/drain contact areas and of the poly-silicon gate is a state-of-the-art pro-
cess for decreasing source/drain contact resistances and forming metal gate electrodes. Silicides are
chemical compounds of silicon and metal. Commonly used materials in the semiconductor industry are
nickel mono-silicide (NiSi), cobalt di-silicide (CoSi
2
), and titanum di-silicide (TiSi
2
). Because of the
silicidation process it is possible to metallize the whole source/drain contact area and, therefore, enlarge
the active contact area, which leads to an efcient reduction of the contact resistances [8]. During the
silicidation, silicon compounds with metal to silicide. This leads to a density difference between both
feed materials and the resulting silicide. The change of the density induces mechanical stress, which af-
fects the carrier transport behavior. Although the silicidation of contact areas and the poly-silicon gate
is a state-of-the-art process, only few process simulation models are available to simulate silicidation.
Furthermore, most of the silicidation simulation models calculate stress distributions not comparable to
measurements. Additionally, the simulation of the silicidation requires a lot of computational effort and
fails, in most of the cases, due to unstable convergence. Finally, electrical parameters of silicides are in
most of the cases not available in the device simulation tools, either. Therefore, a straightforward sim-
ulation of realistic silicidation processes and materials is not feasible at the moment in commercially
available TCAD tools.
A much more promising way to simulate silicidation induced stress is to use simplied models which are
based on the change of the material density during silicidation. Such models are presented in this thesis.
From the literature, many material parameters of silicides and the basic metals used for the silicidation
of planar samples are known [44, 78, 79]. In addition, stress values of planar silicon lms, resulting from
silicidation, are also known. Hence, it is possible to simulate the basic effects which cause mechanical
stress during the silicidation process.
4.1.1.1 Density Change During Silicidation
To take mechanical stress caused by silicidation into account, the change of the density during the silici-
dation was used. For this purpose, the atomic volumes of three materials (basic materials and resulting
material) have to be calculated. The volume per atom can be calculated by
V
x
= a b c
1
A
, (4.1)
4.1 Process Induced Mechanical Stress 39
Table 4.1 Lattice constants (a, b, c), lattice types, number of atoms in one crystalline cell A, atomic vol-
umes V
x
(single materials), and molecular volumes (compounds) [78]
Silicon Nickel Cobalt Titanium NiSi CoSi
2
TiSi
2
a (10
8
cm) 5.43 3.5241 3.5446 2.950 5.233 5.364 3.62
b (10
8
cm) 5.43 3.5241 3.5446 2.950 3.258 5.364 13.76
c (10
8
cm) 5.43 3.5241 3.5446 4.686 5.659 5.364 3.61
Type Diamond Cubic Cubic Hexagonal Orthor Cubic Orthor
A 8 4 4 6 4 4 4
V
x
(10
23
cm
3
) 2.0013 1.0938 1.1134 1.76 2.412 3.8614 4.495
where a, b, and c are the lattice constants and A is the number of atoms per cell. The change of the
density is expressed by
=
V
M3
V
M1
+V
M2
, (4.2)
where V
M3
is the molecular volume of the resulting material and V
M1
and V
M2
are the atomic volumes
of the basic materials. Table 4.1 contains the lattice constants, lattice types, number of atoms, and
cell volume of silicon, nickel, cobalt, titanium, and the resulting silicides nickel-mono-silicide (NiSi),
cobalt di-silicide (CoSi
2
), and titanium-di-silicide (TiSi
2
). The lattice constants and the kind of the
crystal lattice are taken from the literature [44, 78]. The "density increase" factor during silicidation was
calculated from the data in Tab. 4.1 to be 22 % for NiSi, 24.3 % for CoSi
2
, and 23 % TiSi
2
. The three
values calculated for NiSi, CoSi
2
, and TiSi
2
correspond to values presented in the literature, which were
published during this thesis [80].
4.1.1.2 Material Parameters
For simulating silicidation induced mechanical stress, it is not sufcient to calculate the change of the
density of the crystal lattice. Furthermore, the mechanical parameters of the resulting silicides have to
be implemented into the process simulator as well. The most signicant parameters in this case are
the Youngs modulus, the poisson ratio, the thermal expansion coefcient, the bulk modulus K, and the
shear modulus G. The bulk modulus K (Eq. (4.3)), which denes the resistance to uniform compression,
and the shear modulus G (Eq. (4.4)), which denes the ratio of shear stress to the shear strain [81] are
calculated from the Youngs modulus Y and the poisson ratio P [43]:
K =
Y
3(1 2P)
(4.3)
G =
Y
2(1 +P)
. (4.4)
For the implementation in SProcess, the parameters of the material statement Mechanics [31] were
changed. Table 4.2 summarizes the parameters and the values, respectively, to be changed for the dif-
ferent silicides. By using the material specic parameters listed in Tab. 4.2 and the density increase of
22 % for NiSi, 24.3 % for CoSi
2
, and 23 % for TiSi
2
it is possible to simulate lm stresses in planar sam-
ples equivalent to experimental results which are presented in [80]. In addition to the density change
during the silicidation, the thermal budget of the silicidation process has to be taken into account. It was
Figure 4.1 Silicidation resulted lm stress by using the density change
method and material specic parameters listed in Tab. 4.2
reported that at a certain temperature the stress in silicide lms relaxes, even during the phase change
process from metal to silicide [80]. If the sample is cooled down from the relaxation temperature, listed
in Tab. 4.2, stress is induced into the silicide lm and also into the silicon substrate, due to the difference
in the thermal expansion coefcients of silicon and the silicide [80]. It was shown in [80] that the force
per unit width, after silicidation and cooling down phase, increases in the silicide lms if their thick-
ness increases [80]. In this work, the silicidation resulted mechanical stress distribution was simulated,
in assumption of a full stress relaxation at the temperatures T
relax
listed in Tab. 4.2. Additionally, the vol-
ume mismatch due to different thermal expansion coefcients (Tab. 4.2) during the cooling phase and
the increase of the density was taken into account. Figure 4.1 shows the force per unit width calculations
for NiSi, CoSi
2
, and TiSi
2
at different silicide thicknesses t
silicide
and the comparison to measured data
taken from [80]. A very good match to experimental results was achieved in the case of CoSi
2
and TiSi
2
.
Because of no results at different silicide thicknesses were available for NiSi during this thesis, no com-
parison was possible. The lm stress of 720 MPa at a lm thickness of 50 nm NiSi as measured in [80],
however, was achieved by using the method mentioned above.
Table 4.2 Material parameters for NiSi, CoSi
2
, and TiSi
2
[80]
NiSi CoSi
2
TiSi
2
Youngs modulus Y (dyn) 1.5 10
12
1.6 10
12
2.64 10
12
Poisson ratio P 0.13 0.495 0.33
Thermal expansion Coefcient (10
6
K
1) 16.0 10.4 12.5

Relaxation temperature T
relax
350
C 500
C 650
C
Density increase 22 % 24.3 % 23 %
(a) Nickel mono-silicide (NiSi) silicidation
(b) Cobalt di-silicide (CoSi2) silicidation
(c) Titanium di-silicide (TiSi2) silicidation
Figure 4.2 Simulated silicidation resulted stress distribution in FDSOI MOSFETs for different silicides
Table 4.3 Impact of silicidation induced stress on the on-currents of NMOS and
PMOS single gate fully depleted silicon on insulator transistors;
X(V
DD
= 1.1 V ) = I
on,silicide
/I
on,default
Silicide I
on,NMOS
(A/m) X
NMOS
I
on,PMOS
(A/m) X
PMOS
NiSi 697.8 0.95 414.7 0.98
CoSi
2
667.0 0.91 428.5 1.02
TiSi
2
665.3 0.91 415.2 0.99
Finally, the silicidation models were used to simulate stress distributions in a FDSOI MOSFET. Asilicide
thickness of 10 nm was used to form the source/drain contacts. Additionally, a complete silicidation of
the gate electrode was assumed, like published several times [3, 18]. Figure 4.2 shows the resulted stress
distributions in XX direction (along the channel). The full silicidation of the gate electrode yields in
compressive stress in the channel region. Because of the smaller force per unit width in NiSi lms,
the nal compressive stress in the channel is the lowest (150 MPa) after the nickel silicidation as well
(Fig. 4.2(a)). The silicidation with cobalt leads to a higher compressive stress in the channel region
(300 MPa), twice as high as in the case of the nickel silicidation (Fig. 4.2(b)). The silicidation using
titanium results in the highest compressive stress (350 MPa) in the channel region (Fig. 4.2(c)). Although
the force per unit width is twice as high for TiSi
2
compared to CoSi
2
, the amount of stress in the channel
region does not differ signicantly.
The impact of silicidation on the on-currents of NMOS and PMOS transistors was simulated and is
presented in Tab. 4.3. The on-current of the NMOS transistor, by using the method of stress relaxation
at T
relax
and volume mismatch, was negatively impacted by the silicidation processes, as denoted by
the X
on,NMOS
factor. The on-currents of the PMOS transistors were partly negatively inuenced by
the silicidation. This effect mainly results from the compressive stress perpendicular to the channel
direction. Due to the higher piezo coefcients for holes than for electrons (Tab. 4.5), the on-current
degradation is much stronger for PMOS transistors than for NMOS transistors. This effect might be
compensated if advanced shallowtrench isolation techniques were used [82]. Otherwise, the combination
of different silicides for the source/drain contacts and the gate electrode can result in a performance
improvement. One example for mobility enhancement due to the combination of different silicides can
be found in the literature [3, 51]. It could be demonstrated in [51] that the combination of CoSi
2
, used
for source/drain silicidation, and NiSi, used to silicide the gate electrode, leads to tensile stress along the
channel direction, which is benecial for NMOS transistors.
Table 4.4 Average mechanical stress along the channel direction induced by contact etch stop layers and the
additional gate replacement technique [83]
CESL intrinsic stress 800 MPa 1000 MPa 1500 MPa 2000 MPa 2500 MPa
t
CESL
=10 nm 100 MPa 130 MPa 190 MPa 260 MPa 350 MPa
t
CESL
=20 nm 150 MPa 190 MPa 280 MPa 370 MPa 460 MPa
t
CESL
=10 nm+replacement 270 MPa 340 MPa 500 MPa 666 MPa 840 MPa
t
CESL
=20 nm+replacement 345 MPa 430 MPa 640 MPa 870 MPa 1100 MPa
(a)
(b)
Figure 4.3 Distribution of mechanical stress along the channel direc-
tion induced by tensile and compressive CESL: (a) Tensile CESL with
intrinsic stress of 800 MPa; (b) Tensile CESL with intrinsic stress of
2500 MPa
4.1.2 Contact Etch Stop Layer
Contact etch stop layers (CESL) are a commonly used method to apply mechanical stress to the channels
of MOSFET transistors. These layers consist of silicon-nitride deposited on the whole MOSFET geom-
etry to dene a stopping point for the etch process of contact holes. In this work, CESLs were mainly
used to introduce either tensile or compressive stress along the channel direction, to improve the charge
carrier mobility behavior. Using an intrinsic stress value of 800 MPa up to of 2500 MPa [84], the nitride
layers would have when they were deposited on a planar substrate, the resulting stress in the channel
was simulated, solving the stress relaxation equations, presented in Chapter 2, in the whole transistor
structure. Figure 4.3 shows up the resulting stress distribution along the channel direction for tensile
CESLs of intrinsic stress values of 800 MPa (Fig. 4.3(a)) and 2500 MPa (Fig.4.3(b)). In case of the ei-
ther 800 MPa tensile or compressive CESL, the average stress in the channel region was calculated to be
approximately 150 MPa, tensile or compressive, respectively. If the intrinsic stress of the CESL is as-
sumed to be 2500 MPa, the nal stress along the channel direction amounts to 460 MPa. The results of
the simulations for different intrinsic stress values and two CESL thicknesses are presented in Tab. 4.4.
Although the intrinsic stress values of the CESL are very high in some cases of the simulation experi-
ment, the resulting stress in the channel is only nearly a fth. This origins from the geometrical structure
of the gate stack, which is not able to transfer the complete stress directly to the channel.
(a)
(b)
Figure 4.4 Mechanical stress along the channel direction induced by
tensile and compressive CESL and the gate replacement technique [83]:
(a) Tensile CESL with intrinsic stress of 800 MPa, (b) Tensile CESL
with intrinsic stress of 2500 MPa
4.2 Impact of Mechanical Stress on the Charge Carrier Mobility 45
4.1.2.1 Gate Replacement for Stress Enhancement
To enhance the stress induced by nitride stress liners in the channel, the gate replacement technique
proposed by Yamakawa [83] can be used. Here, a dummy poly-silicon gate electrode serves to form
the gate stack. Then, either a compressive or tensile contact etch stop layer is deposited on the nished
MOSFET structure. Finally, the top of the gate stack is opened and the dummy poly-silicon gate is
removed and replaced by either a new poly-silicon electrode or a metal electrode [83]. During the
replacement, the impact of the CESL on the channel becomes stronger which increases the mechanical
stress in the channel region [83]. The nal stress is then conserved by the new gate electrode. Figure 4.4
shows the calculated stress distribution resulting from using CESLs with 800 MPa and 2500 MPa of
intrinsic stress and the gate replacement technique. As can be seen, if Fig. 4.4 is compared to Fig. 4.3,
the average stress value in the channel can nearly be doubled by using the gate replacement technique.
The average mechanical stress values for different conditions in the channel region are summarized in
Tab. 4.4.
4.2 Impact of Mechanical Stress on the Charge Carrier Mobility
The simulation of the impact of mechanical stress on the carrier mobility was and still is an important
issue for the device simulation community. The impact of mechanical stress on the low eld electron
mobility is by default calculated by the deformation potential model [85]. This model calculates the
change in the electron mobility as a function of the band gap and the change of the effective mass, which
are both inuenced by mechanical stress. Comparisons of simulations, using the deformation model, to
NMOS transistor performances from the literature [3] (Fig. 3.4 Chapter 3), show a good correspondence.
For simulating the enhancement of the low eld hole mobility, due to mechanical stress, two stan-
dard simulation models are accepted by the device simulation community. The rst one is the Intel
model [86, 56] which calculates the mobility enhancement by a change in the effective hole masses
of the longitudinal and the transverse contributions. The second model is a piezo coefcient based
model [58, 77] which treats the change in the mobility as a linear function of the applied stresses, multi-
plied with the piezo coefcients, respectively. However, both models are developed at low stress values
up to 500 MPa. Combinations of measurements and simulations, presented in the literature, show that
the hole mobility enhancement already saturates at stress values of 2 GPa [77]. Since the Intel model
and the piezo coefcient model have, by denition, a linear behavior, they do not saturate at high stress
values, which results in an overestimation of the hole mobility enhancement at high stress values. There-
fore, a model that accounts for a saturation behavior of the hole mobility enhancement has to be found.
Such a model is presented below.
Table 4.5 Piezo coefcients [30,77] and model parameters for the uniaxial
and biaxial mechanical stress
(TPa
1
) A
1
A
2
x
0

Longitudinal low 717.0 3.17 0.41 -0.60 0.464
Transversal low -338.0 0.269 1.282 -0.189 0.199
Longitudinal high 717.0 4.63 0.49 -0.746 0.397
Transversal high -338.0 0.54 2.98 0.549 0.360
4.2.1 A Modied Piezo Model for <110> Channel PMOSFETs on <100> Si Substrates
The model is based on the classical piezo coefcient model for the change of the charge carrier low eld
mobility
low
under the impact of mechanical stress (Eq. (4.5)) [30, 77]:
low
()
low,0
=
. (4.5)
Here,
and
are the piezo coefcient and the mechanical stress value parallel (
XX
) to the channel
direction and
and
are the piezo coefcient and the stress value perpendicular (

YY
) to the channel
direction. As Eq. (4.5) denotes, using the default piezo model leads to a linear behavior of the mobility
enhancement.
The approach for the improvement of the piezo coefcient based model is based on the Boltzmann
function
f(x) = A
2
+
A
1
A
2
1 + exp
_
x x
0
_ , (4.6)
which is used to describe the stress dependent low eld mobility
low
():
low
() = f()
low,0
. (4.7)
Like the linear piezo based model, the effect of two mechanical stress components are simply a sum of
the longitudinal (
(
low,0
) and the transversal (
(
low,0
) part for calculating the overall mobility shift for
uniaxial and biaxial applied stress. The change in the mobility ()/
0
due to one stress component
is expressed by
()
low,0
= A
2
+
A
1
A
2
1 + exp
_
x
0
_ 1.0. (4.8)
In Eq. (4.8), x
0
, A
1
, A
2
, and are t parameters and is the respective piezo coefcient. The nal
expression for the modied piezo model is dened by
low
()
low,0
=
(
low,0
+
(
low,0
+ 1.0. (4.9)
As a result of non-continuous behavior of the measured and simulated mobility enhancement for holes
from the literature [77], two cases of stress must be distinguished: low stress values below 1000 MPa;
high stress values above 1000 MPa. Table 4.5 shows the piezo coefcients in TPa
1
and the tting
parameters for the different stress components and for the two ranges of stress strength, low and high
stress. A feasible border between the ranges of low and high stresses was empirically found at 1 GPa.
The modied piezo model was included into SDevice by a physical model interface (PMI), like it was
done already for the advanced Drift-Diffusion model.
4.2.2 Hole Mobility Simulation Results Using the Modied Piezo Model
In the simulation experiment, a numerical model of a bulk PMOSFET with 100 nm gate length,
a gate-oxide thickness of 2 nm, and abrupt homogenous doping proles (N
sd
= 1 10
20
cm
3
,
N
ch
= 1 10
17
cm
3
) was used. The impact of mechanical stress was modeled directly in the de-
vice simulation tool by applying uniaxial
XX
,
YY
, or biaxial (
XX
=
YY
) uniform stress. The transfer
characteristic at low drain voltages was simulated, using conventional DD simulation models (see Chap-
ter 2) [31, 51], and the drain current (at V
gate
= 0.9 V and V
drain
= 0.05 V) was extracted. Stress values
of
XX
and
YY
were applied in range of -5000 MPa to 5000 MPa. The change in the low eld mobility
was nally calculated by the change in the drain current at the different stress values. Due to the fact that
the Intel model [86, 56] is presently a standard model for simulating mechanical stress induced hole mo-
bility enhancement, the results of the new model were compared to results computed by the Intel model.
In addition, both simulation models were compared to data from the literature [87].
(a) (b)
(c) (d)
Figure 4.5 Comparison of the low eld mobility enhancement calculated by the modied piezo coefcient
based model to results from the literature and the Intel model: (a) Stress along the xx direction (high stress
values); (b) Stress along the xx-direction (low stress values); (c) Stress along the yy-direction (low stress values);
(d) Biaxial stress (low stress values)
Figure 4.5(a) shows the simulation results for the case of mechanical stress along the channel direction
(
XX
). As can be seen, the mobility enhancement fromthe literature saturates at an enhancement factor of
nearly 4 just at stress values of above 2 GPa (Fig. 4.5(a) squares), while the default piezo model follows a
linear dependence on the stress and does not saturate (Fig. 4.5(a) triangles). The Intel model (Fig. 4.5(a)
stars) does not saturate either and calculates even a higher mobility enhancement than the default piezo
model [30, 77]. The modied piezo model (Fig. 4.5(a) circles), on the other hand, reproduces the results
from the literature and saturates at a factor of about 4 of mobility enhancement. In the case of low stress
values, the modied piezo model and the Intel model are able to reect the results from the literature
(Fig. 4.5(b)).
A problem located in the case of uniaxial stress applied perpendicular to the channel direction (
YY
) is
shown in Fig. 4.5(c). Here, the Intel model (Fig. 4.5(c) stars) already overestimates the change in the
hole mobility if small stress values are applied, compared to the results from the literature (Fig. 4.5(c)
squares). The modied piezo model (Fig. 4.5(c) circles), on the other hand, reects the literature re-
sults at low and high stress values. If biaxially applied stress is applied (Fig. 4.5(d)), the Intel model
(Fig. 4.5(d) stars) consequently underestimates the mobility enhancement that is presented in the liter-
ature (Fig. 4.5(d) squares). The modied piezo model (Fig. 4.5(d) circles) overestimates the mobility
enhancement at low compressive biaxial stress values but compares relatively well with the experiments
at low tensile biaxial stress values.
Figure 4.6 Mobility enhancement at high stress values for uniaxial
longitudinal, transversal and biaxial stress
Figure 4.6 combines the simulation results for three stress cases, uniaxial longitudinal, uniaxial transver-
sal, and biaxial, that are discussed in this work. In case of the longitudinal stress (Fig. 4.6 squares), the
mobility enhancement saturates at a factor of 4.6, if compressive strain is applied. The mobility degra-
dation due to tensile strain saturates at 50 %. Compressive transversal strain results, on the other hand,
in 50 % mobility degradation, while tensile transversal strain induces a mobility enhancement of a fac-
tor of 2.9. Compressive biaxial strain increases the mobility by a factor of 4.1. Tensile biaxial strain
reduces the low eld mobility for low stress values of about 13 %, but increases the mobility by a factor
Figure 4.7 Threshold voltage shift due to applied stress calculated by
the modied piezo model
of 2.5 in case of high tensile biaxial stresses. Table 4.6 presents the maximum calculated change in the
low eld mobility and the threshold voltage V
th
at stress values of 5 GPa compressive and tensile stress.
Due to the change of the low eld mobility induced by mechanical stress, and the resulting change in
the charge carrier distribution, a shift in the threshold voltage can be observed (Fig. 4.7). In the com-
pressive case, a negative shift of the threshold voltage of about 13% for the uniaxial longitudinal stress
scenario (Fig. 4.7 squares) and 13% in the biaxial case (Fig. 4.7 stars) was calculated. On the other hand,
the uniaxial transversal compressive stress (Fig. 4.7 circles) induces a positive shift of the threshold volt-
age of about 7%. Tensile stress results in a positive shift of 8% in the longitudinal stress case. Biaxial
tensile stress results in a negative shift of the threshold voltage of 8%, while transversal stress shifts the
threshold voltage of 10%, as well. The V
th
shift results in a slightly non-linear appearance of ().
Table 4.6 Low eld mobility enhancement and threshold voltage shift at 5 GPa stress
Compressive Tensile V
th
(compressive) V
th
(tensile)
Longitudinal
low
4.6
low
0.5 V
th
0.87 V
th
1.08
Transversal
low
0.5
low
2.9 V
th
1.07 V
th
0.9
Biaxial
low
4.1
low
2.5 V
th
0.87 V
th
0.92
Chapter 5
Parasitic Contact Resistances
The last two chapters dealt with the topic of MOSFET performance boost, by means of, rst, reduced
scattering probability in sub-50 nm scaled channels and, second, mechanical stress. This chapter, how-
ever, goes in for the effect of performance degradation due to parasitic Schottky contact resistances. Para-
sitic source/drain contact resistances result from carrier tunneling through the Schottky barrier at the met-
al/silicon interface. Due to the continuous scaling of the device dimension, they might become a serious
problem for future CMOS devices. The source/drain contact resistances follow the equation [8, 55, 67]
R
co
=

c
L
co
W
co
, (5.1)
where
c
denotes the specic resistivity of the contact interface, W
co
the contact width, and L
co
the
contact length. Hence, if the overall MOSFET layout area A is reduced, R
co
increases proportional
to 1/A. The ITRS [9] requires decreasing effective parasitic source/drain series resistances, like dis-
played in Fig. 5.1(a), for future technology nodes while the contact area should further be decreased. In
(a) (b)
Figure 5.1 (a) Contact resistances behavior recommended by the ITRS [9]; (b) Contact resistances behavior
calculated using Eq. (5.1) with constant
c
.
51
52 5 Parasitic Contact Resistances
Fig. 5.1(a), the values of R
S/D
of high performance devices were taken directly from the ITRS [9].
The contact length L
co
, on the other hand, was assumed to be four times the physical gate length of high
performance devices of the different ITRS technology nodes. The trend of R
S/D
and L
co
over the fu-
ture is comparable, like displayed in Fig. 5.1(a). If Eq. (5.1) is applied to the scaling behavior of the
MOSFET area over the next years, however, the behavior of the contact resistances looks as displayed
in Fig. 5.1(b). Here, the R
S/D
at 100 nm contact length (25 nm gate length) was assumed as initial value,
used to calculate the specic resistivity
c
in Eq. (5.1). Figure 5.1(b) clearly demonstrates the increase
of R
co
over the next years up to more than 1 k, by assuming a constant specic resistivity. Therefore,
it is important to nd solutions for reducing R
co
. Otherwise, the high contact resistances will result in a
strong degradation of the on-current of future CMOS devices.
From Eq. (5.1), two factors for efciently reduce contact resistances can be named. The rst factor is the
specic resistivity
c
of the metal/silicon contact interface. The specic resistivity is proportional to the
right hand side of [8, 67]
c
exp
_
4
B
qh
_
m
Si
N
d
_
. (5.2)
Here,
B
denotes the Schottky barrier height at the contact-to-silicon interface, q the elementary charge,
h Plancks constant, m
the effective mass,

Si
the permittivity of silicon, and N
d
the doping concen-
tration at the metal/silicon interface. The specic resistivity
c
can only be reduced by decreasing the
Schottky barrier height
B
[88] or by increasing the doping concentration N
d
in silicon at the contact.
Another possibility for an efcient reduction of the parasitic contact resistance is to increase the contact
length L
co
or the contact width W
co
. This solution, on the other hand, is not compatible to the idea of
scaling down the whole MOSFET layout for saving silicon area and reaching a higher integration den-
sity. Hence, nding a method to this problem for achieving more contact area and not increasing the
overall layout consumption of the MOSFETs is very promising.
5.1 Experimental Investigation of the Dependence of Contact Resistances
on the Contact Area
The problem of increasing contact resistances is only barely discussed in the literature. Therefore, exper-
iments were carried out in this thesis to validate the assumption presented in Fig. 5.1(b). Furthermore,
it is important to prove the validity of existing simulation models for Schottky contact resistances [55].
One of this models was already presented in Chapter 2 (Eq. (2.31)).
5.1.1 Process Flow
The experiment was performed using a phosphorus doped Si wafer with a homogenous doping concen-
tration of 1.35 10
15
cm
3
(Fig. 5.2(1)). The sheet resistance of the wafer was calculated to be 2.5 cm.
At rst, oxidation was undertaken to grow 50 nm of silicon oxide on the frontside and the backside of
the wafer. A dry oxidation process at 1000
C for 60 min was used to grow the oxide (Fig. 5.2(2)). After
that, three regions with different surface doping concentrations were formed. Photoresist was spun on
the frontside of the wafer (Fig. 5.2(3)). Then, one third of the resist was removed and the open part was
implanted with 1 10
15
cm
2
of phosphorus using an ion implantation energy of 45 keV (Fig. 5.2(4)).
The second third of the photoresist was removed afterwards, and a second implantation step with a dose
5.1 Experimental Investigation of R
co
(A
co
) Dependence 53
Figure 5.2 Process ow
of 1 10
14
cm
2
of phosphorus and energy of 35 keV was carried out (Fig. 5.2(5)). Finally, the remain-
ing resist was removed and a third implantation step with a dose of 1 10
13
cm
2
of phosphorus and
an energy of 30 keV was undertaken (Fig. 5.2(6)). After the three doping regions on the frontside were
formed, the backside was implanted with 1 10
15
cm
2
of phosphorus with an energy of 45 keV to re-
duce the series resistance of the backside contact. Following the implantation sequence, the wafer was
annealed by two steps: 800
C for 20 s and 1070
C for 10 s. The expected doping concentration proles,

simulated by ICECREM [89], are shown in Fig. 5.3. 200 nm of silicon oxide was deposited on the top of
the wafer by a LPCVD (Low Pressure Chemical Vapor Deposition) (Fig. 5.2(7)) and TEOS (Tetraethy-
loxysilan) process. Photoresist was spun on again for the following lithography step, to build the contact
holes (Fig. 5.2(8)). The contact holes were patterned by a dry etching process to remove 250 nm of sili-
con oxide (Fig. 5.2(9)). On every die on the wafer, 12 contact holes in all with sizes of 1 m
2
, 2.25 m
2
,
4 m
2
, 6.25 m
2
, 9 m
2
, 12.25 m
2
, 16 m
2
, 20.25 m
2
, 25 m
2
, 30.25 m
2
, 64 m
2
, and 100 m
2
were processed. 50 nm titanium was deposited for the direct metallization of the silicon (Fig. 5.2(10)).
The completion of the metallization was done by depositing 800 nm of AlSi (Fig. 5.2(11)). Finally, a
second lithography step was performed to pattern the deposited AlSi layer (Fig. 5.2(12)).
5.1.2 Measurement of Contact Resistances at Different Contact Areas
The measurement principle was based on a four contact point measurement approach. Thereby, two nee-
dles contacted the contact hole, while the wafer-chuck acted as the third and fourth contact point. A semi-
conductor parameter analyzer was used to ramp the current from -10 mA to 10 mA between the rst point
on the top of the wafer and the chuck. During the current sweep, the voltage between the substrate and the
(a) (b)
Figure 5.3 (a) Doping concentrations of the three regions at the frontside of the wafer; (b) Doping concentration
at the backside of the wafer
second point on the top was measured. Figure 5.4 displays the measurement results of the 1 10
20
cm
3
doped region. Figure 5.4(a) shows the I(V ) characteristics of the measured devices. It can be seen from
the I(V ) characteristics that the resistance decreases, as expected, by increasing the pad area. The direct
dependence between the pad area and the measured resistance is plotted in Fig. 5.4(b)(symbols). The
smallest resistance measured is about 40 at a pad area size of 100 m
2
. Since a saturation behavior of
the measured resistance between the pad area sizes of 64 m
2
and 100 m
2
can be observed, it can be
concluded that the series resistance of the wafer is about 40 , while the contact resistance at this pad
sizes is negligible in comparison to the spreading resistance between the frontside and backside contact.
The main aim of the measurements was to prove the validity of the Schottky contact resistances simu-
lation model used in this work [55]. Therefore, simulations with the same doping concentration and the
same sizes of area were carried out. Figure 5.4(b) shows the comparison between the measured contact
resistances and the simulation results. A very good correlation between the simulation (solid line) and
(a) (b)
Figure 5.4 Measurement and simulation results of the 1 20 cm
3
doped regions: (a) I-V characteristics for
different pad sizes; (b) R
co
(A
co
) dependence (line-symbols: experiment, line: simulation)
5.2 Improved Contact-Pad Architectures 55
the experiment (squares) was achieved by using the existing simulation model [55]. Hence, the validity
of the used simulation model was demonstrated and ensured.
5.2 Improved Contact-Pad Architectures
In the last section, the validity of the used simulation model for taking the impact of Schottky contact
resistances into account was demonstrated by comparison to measurements. Now, a solution is presented,
how contact resistances can be efciently decreased by increasing the active contact area, but without
increasing the overall MOSFET layout area consumption. Figures 5.5 (b) and (c) display two possible
ideas for achieving more contact area for the silicide-to-silicon interface at source/drain contacts [53].
Here, in Fig. 5.5 (b), a shallow trench is etched into the silicon piece. The second possibility is displayed
in Fig. 5.5 (c) where a plug is etched out of silicon. Furthermore, a shallow silicidation process can be
used for the metallization of the whole contact area. The contact area enlargement A
co
resulting from
the trench or the plug architecture can be expressed by the following equation
A
co
= A
co,0
+ 2t
etch
(L
co
+W
co
4a 4t
etch
cot()). (5.3)
A
co,0
denotes the initial contact area and t
etch
either the depth of the trench (Fig. 5.5(b)) or the height
of the plug (Fig. 5.5(c)). Due to the three dimensional layout both, the contact length L
co
sidewalls and
the contact width W
co
sidewalls contribute to the area enlargement. The planar parts a, displayed in
Fig. 5.5, however, have to be subtracted from the area enlargement. If the trench or the plug is etched
in a certain inclination angle below 90
, the impact of tapered side walls has to be considered by

cot(). Figure 5.6 displays the comparison of the resistances for the plain contact architectures and the
trench (Fig. 5.5 (b)) architectures carried out by numerical simulations. The open symbols denote the
simulations using plain contact pads. The closed symbols in Fig. 5.6 show the simulation results using
the trench architecture. Here, a decreasing angle according to
tan() =
1
5
L
co,plain
t
etch
(5.4)
Figure 5.5 Area achievement by using contact plug architectures; (a) Plain contact area;
(b) Contact trench; (c) Contact plug principle
was chosen, by scaling down the plain contact length L
co,plain
, while t
etch
and W
co
were kept on a constant
level of 25 nm and 1.0 m, respectively. Additionally, three surface doping concentrations were assumed
in the simulation experiment presented in Fig. 5.6: 1 10
20
cm
3
, 3 10
20
cm
3
, and 5 10
20
cm
3
.
Figure 5.6 shows that the overall contact resistance R
co
can be reduced for every doping concentration,
if the trench architecture is used. Especially for very small contact areas, the effect becomes larger. Due
to the surface enlargement achieved by the etched trenches, the characteristics of the trench architecture
increase less than the characteristic of the plain contact pads. In addition, a strong impact of the active
surface doping concentration on the contact resistances can be observed in Fig. 5.6. The increase of the
doping concentration by a factor of 5 leads to a signicant reduction of R
co
by one order of magnitude.
Consequently, the right combination of a highly doped surface and the trench architecture, or rather the
plug architecture, can efciently reduce the contact resistances, without increasing the MOSFET layout
area.
5.2.1 MOSFET Performance Improvement by Alternative Contact Pad Architectures
In this subsection, it is demonstrated, how the proposed contact pad modications inuence the MOS-
FET performance. Therefore, a FDSOI MOSFET with homogeneous source/drain doping proles was
considered. The gate length was set to 40 nm and the gate oxide thickness was assumed to be 1 nm.
Additionally, overall four contact congurations were used. At rst, the simulations of the transfer char-
Figure 5.6 Contact resistance behavior for different doping concentrations by scaling down the contact area;
dashed lines and open symbols: plain contact pad; solid lines and lled symbols: trench architecture
acteristic at low drain bias and output characteristic at a gate voltage of 1.1 V were performed, without
taking contact resistances into account. Secondly, the contact length was considered equal to the physical
gate length and the contact resistances were switched on in the simulation. Thirdly, the contact pad length
was increased to four times the gate length. Finally, the contact length was reduced again to L
gate
and
the trench architectures are used with an etching depth t
etch
of 20 nm. Figures 5.7(a) (NMOS) and 5.7(b)
(PMOS) display the simulated results of the transconductance at low drain voltages (V
drain
= 0.05 V) of
the four contact congurations considered. Figures. 5.7(c) and 5.7(d) display the simulated output char-
acteristics. The initial transconductance and output characteristics without taking contact resistances into
account are denoted by the squares. The triangles denote the transconductance and output characteristics
resulting from the simulation of taking contact resistances into account with a contact length L
co
similar
to L
gate
. Due to the very short contact length of L
gate
the contact resistances lead to a very strong degra-
dation of the transconductance and the on-current, for the NMOS (Fig. 5.7(a) and 5.7(c)) and for the
PMOS (Fig. 5.7(b) and 5.7(d)). If the contact pads are increased to four times the gate length (Fig. 5.7
circles), the impact of the contact resistances is not as strong as for the small contact length, but still de-
creases the static performance to half of the initial value. The same behavior is discovered in case of the
(a) (b)
(c) (d)
Figure 5.7 MOSFET behavior by using different contact realizations: (a) Transconductance of the NMOS at
low drain voltages; (b) Transconductance of the PMOS at low drain voltages; (c) Output characteristic of the
NMOS at high gate voltages; (d) Output characteristic of the PMOS at high gate voltages;
output characteristics (Fig. 5.7(c) NMOS and Fig. 5.7(d) PMOS). Using the contact trench architecture,
which is denoted in Fig. 5.7 by the solid line, leads to the same contact resistance at very small contact
areas compared to R
co
by using large areas. Thus, by using the contact trench conguration, it is pos-
sible to efciently decrease the overall MOSFET layout by keeping the contact resistances at a constant
level.
5.2.2 Doping Strategies
To use the structures proposed in Section 5.2, it is important to nd the right method of doping to achieve
a homogeneous doping concentration at the metal/semiconductor interface. Therefore, two alternative
ways of doping are presented in this subsection. The rst doping method is based on an implantation/an-
nealing scheme. Three implantation steps were used. The ion doses N
2
, implantation energies, tilts,
and rotation angles are listed in Tab. 5.1. Following the implantation steps of Tab. 5.1, a coupled spike
(T
peak
= 1070
C) followed by a ash annealing scheme with a peak temperature of approximately

1300
C (Fig. 2.3 in Chapter 2) [90] was used for activation and diffusion.
(a) (b)
(c) (d)
Figure 5.8 Doping strategies for the trench and the plug architecture: (a) Trench architecture im-
planted and annealed; (b) Plug architecture implanted and annealed; (c) Trench doped by spin-on-
dopant source; (d) Plug doped by spin-on-dopant source
Figures 5.8(a) and 5.8(b) show the resulting doping prole at the metal/silicon interface. Using con-
ventional implantation techniques for these kind of structures result in an inhomogeneous concentration
distribution along the surface of the trench and the plug. An inhomogeneous surface doping concentra-
tion leads to a quasi parallel contact resistance network and results in an increase of the overall contact
resistance. Dependent on the amount of inhomogeneity, the positive effect of the surface enlargement
can be compensated. This would lead to no signicant reduction of the overall contact resistance.
For the second doping method, a layer of a highly doped (1 10
22
cm
3
) spin-on-dopant source [37] was
assumed to be deposited on the trench and the plug. Then, ash annealing is used for diffusion and
activation again. As Figs. 5.8(c) and 5.8(d) show, this technique results in a high homogeneous doping
concentration around the surface of the trench and the plug. By this method, the advantage of contact
area enlargement can be used to full capacity with a signicant reduction of R
co
.
Table 5.1 Implantation conditions for optimizing surface
doping concentration of contact trench and contact plug
architectures
N
2
Energy Tilt Rotation angle
1 10
14
cm
2
1.0 keV 7
0.0
8 10
14
cm
2
1.0 keV 15
90.0
8 10
14
cm
2
1.0 keV 15
270.0
Another possibility for achieving a homogeneous doping concentration would be to elevate the
source/drain regions by molecular beam epitaxy (MBE) using pre-doped silicon. By this method, very
high surface doping concentrations can be achieved with good homogeneity. In principle, this tech-
nique is very promising for reducing contact resistances. The MBE process is, however, very expensive.
Therefore, the doping by means of spin-on-dopant sources was chosen to be used in the further MOSFET
investigations, presented in Chapter 6.
Chapter 6
MOSFET Architectures by Comparison
The main purpose of this thesis is the investigation of different MOSFET architectures by numerical sim-
ulation. Conventional bulk MOSFET devices and alternative SOI devices are compared in this chapter.
Additionally, the simulation models and methods presented in the previous chapters were used in the
simulation study for further demonstrating their usability in complex TCAD simulations.
6.1 Choice of Devices, Simulation Setup, and Parameter Extraction
Methodology
Four CMOS device architectures were investigated and compared in this thesis. Thereby, it is examined,
if the advantages of alternative CMOS architectures, compared to the conventional bulk architecture,
overcompensate the higher complexity and costs of producing these kind of devices. Based on the 32 nm
technology node of the ITRS (Edition 2007) [9], bulk MOSFETs (Fig. 6.1(a)), single gate fully depleted
silicon on insulator (SG FDSOI) MOSFETs (Fig. 6.1(b)), double gate FDSOI MOSFETs (Fig. 6.1(c)),
and triple gate FinFETs (Fig. 6.1(d)) were investigated, concerning their electrical behavior. Since cur-
rent ITRS technology nodes include not only specications of a single device, but a variety of three
device classes, high performance, low operating power, and low standby power, it is additionally be
assessed which device architecture is the most suitable for the different applications.
(a) (b) (c) (d)
Figure 6.1 CMOS device architectures to be investigated: (a) Bulk MOSFET [10]; (b) SG FDSOI MOS-
FET [14]; (c) DG FDSOI SOI MOSFET [22]; (d) FinFET [23]
61
62 6 MOSFET Architectures by Comparison
6.1.1 Simulation Setup
Table 6.1 displays the three sub-nodes of the 32 nm technology node of the 2007 ITRS. The specications
of high performance (HP) devices are from the processing point of view the most though ones. The
physical gate length of HP devices should be 13 nm, while the equivalent oxide thickness (EOT) of
the gate oxide amounts to 0.5 nm. The thin gate oxide already indicates the need of high-k materials
to efciently suppress gate leakage currents. Simulation models for high-k materials, however, were
not available during this thesis, well as processing options (denoted by a red eld in the ITRS table).
Therefore, the effect of gate leakage current was neglected in this work assuming that the choice of
high-k materials will help to suppress gate leakage. Low operating power (LOP) devices are, concerning
processing conditions, situated in between high performance and low standby power (LSTP) devices.
The physical gate length of these devices was noted to 16 nm and the EOT should be 0.8 nm. The last
group of devices to be investigated are low standby power devices. LSTP devices have the most relaxed
process conditions, compared to HP and LOP. Additionally, the LSTP class of the 32 nm technology node
still considers bulk MOSFETs as a possible solution for these applications. The physical gate length of
these devices was set to 20 nm and the EOT should be 1.1 nm.
Based on the geometrical specications of the 2007 ITRS, four device architectures where designed
using the process simulation models presented in Chapter 2. Although the 2007 ITRS does not see the
bulk MOSFET as a suitable solution for the HP and LOP devices anymore, they are simulated also in this
work. Therefore, they serve, rst of all, for reference and secondly, it should be explored, if they really
are not a solution for future HP and LOP applications. In the 2008 ITRS update, however, the extended
planar bulk MOSFET is considered to be used till the year of 2016, till a physical gate length of 14 nm is
reached. Therefore, the procedure of simulating bulk MOSFETs for reference goes conform with future
ITRS editions.
Table 6.1 Comparison of geometrical dimensions of the investigated
MOSFET architectures based on denitions from the 2007 ITRS for the
32 nm technology node (References can be found in the ITRS Process
Integration, Devices, and Structures chapter [9])
HP LOP LSTP
Year of Production 2013 2013 2013
Physical Lgate 13 nm 16 nm 20 nm
Equivalent Oxide Thickness
Extended Planar Bulk 1.1 nm
UTB FD 0.5 nm 0.8 nm 1.2 nm
DG 0.5 nm 0.9 nm 1.3 nm
Supply Voltage V
DD
Extended Planar Bulk 0.95V
UTB FD 0.9 V 0.6 V 0.9 V
DG 0.9 V 0.6 V 0.85 V
Saturation Threshold Voltage
Extended Planar Bulk 547 mV
UTB FD 93 mV 195 mV 399 mV
DG 103 mV 203 mV 362 mV
6.1 Devices, Simulation Setup, and Parameter Extraction 63
6.1.1.1 2D Process Simulation
The process simulation part of two dimensional device models (bulk MOSFET, SG FDSOI , DG FDSOI)
was done using the commercial process simulator SProcess [31], already discussed in Chapter 2. The
topography simulations, including etching, deposition, and chemical mechanical polishing (CMP), were
done using several standard models [31]. Starting from a substrate, whether it is a bulk silicon wafer
or a silicon on insulator (SOI) wafer, shallow trench isolations (STI) were formed. Therefore, a mask
was dened for patterning. The etching of silicon was done by anisotropic etching. Silicon oxide was
deposited followed by a CMP process to remove the oxide from the surface. After the STI were formed,
a thin lm of SiO
2
was deposited on the silicon which serves as gate oxide. Poly-silicon was deposited
on the SiO
2
lm. Subsequently, the gate electrode was etched anisotropic using a second mask for
patterning. The patterned poly-silicon serves as a hard mask to etch the remaining gate oxide which
is not situated under the poly-silicon. A thin lm of 3 nm of silicon-oxide was deposited on the whole
gate stack to serve as scattering oxide and as rst spacer for the ion implantation to control the lateral
expansion of the dopants below the gate stack. It has to be mentioned that an additional implantation
step was used during the process simulation of the bulk MOSFETs. This additional ion implantation
step forms the pocket implants to suppress short channel effects. The rst implantation step (LDD)
was performed at low energies and moderate doses to form the source/drain extensions. To prevent a
complete amorphization of the silicon surface, the implantation energies and doses of the rst step were
chosen to be in a range of to not override the damage concentration of 1 10
21
cm
3
of Frenkel pairs.
The implantation energies and doses used for the different devices are listed in Appendix A.
Following the LDD implantation, nitride (Si
3
N
4
) was isotropically deposited to cover the whole struc-
ture. Mask less anisotropic etching of the nitride layer was used to form the spacers by self alignment.
The scattering oxide was removed afterwards by anisotropic etching. Silicon was deposited to elevate
the source/drain regions. In realistic processing this would be done by a selective epitaxial growth (SEG)
process. This technique has already become very popular for SOI device engineering. This technique
was also used for the bulk MOSFET devices investigated in this thesis. After the source/drain regions
were elevated, a scattering oxide was deposited again to cover the whole device structure before the sec-
ond ion implantation step was performed. During the second implantation step, higher energies and doses
were used to form highly doped source/drain (HDD) regions and, therefore, to minimize the source/drain
series resistances R
S/D
. Furthermore, a high active surface doping concentration should be achieved to
minimize the contact resistance R
co
as already discussed in Chapter 5. An advanced annealing scheme
was applied to the devices to activate the implanted dopants. It was already discussed in the literature [90]
and in Chapter 5 that a combination of spike and ash annealing was found to result in a good electrical
behavior of sub-50 nm scaled MOSFETs. Due to the redistribution of dopants after the spike annealing, a
good conductivity of the channel was achieved, while the ash annealing results in a high active surface
doping concentration. The temperature proles used are displayed in Fig. 2.3 in Chapter 2. Advanced
diffusion and activation models of arsenic [40] and boron [41] were used (see Subsubsection 2.2.1.3),
calibrated especially for rapid thermal annealing process steps.
(a) Bulk MOSFET
(b) SG FDSOI MOSFET
(c) DG FDSOI MOSFET
Figure 6.2 2D device architectures after 2D process simulation
The scattering oxide layer was removed by an isotropic etching step after annealing. To form the
source/drain contacts, a layer of silicide was deposited. The silicide layer was etched down to a thick-
ness of 10 nm by CMP in the simulation, assuming that the remaining metal would be completely re-
moved after the silicidation is nished. In this work, the silicide layers actually only serve to form the
source/drain contacts. The nal structures of the three 2D NMOS device architectures are displayed in
Fig. 6.2. Figure 6.2(a) displays the structure of the bulk MOSFET with elevated source/drain regions
and pocket implants for short channel effect suppression. Figure 6.2(b) shows the structure of the single
gate FDSOI MOSFET and 6.2(c) the structure of the double gate FDSOI with buried gate electrode. The
process parameters used for the different MOSFET architectures are listed in Tabs. A.2, A.4, and A.6 in
Appendix A.
6.1.1.2 3D Process Simulation
To simulate three dimensional device structures such as FinFET devices, e.g., a combination of a classical
CAD software and a process simulation software was used in this thesis. The basic structure of the device
was generated by using the CAD software SentaurusStructureEditor (SDE) of Synopsys [31]. Since
three dimensional device simulations are much more complex concerning the number of grid points,
only the most interesting parts of the devices, i.e. around the channel region, were simulated in this
thesis. Therefore, the n of the triple gate FinFET was modeled on an oxide layer in the CAD software.
Here, the two different regions, buried oxide and silicon n, were dened by simple cuboids. The gate
stack, gate oxide, and poly-silicon electrode, were modeled by the same method, well as the spacer stack
of oxide and nitride. The three dimensional structure was passed to the process simulation tool SProcess
to perform ion implantation and annealing simulation of the source/drain extensions. In contrast to two
dimensional structures, ion implantation was performed using a tilt of 45
to implant into the sidewalls of

(a) (b)
Figure 6.3 (a) 3D FinFET architecture after CAD; (b) 3D FinFET architecture after process simulation
the n. The energies were chosen to set the maximum of the implanted distribution to the center of the n
(approximately 4 eV for NMOS and 1 eV for PMOS) to form a nearly homogenous dopant distribution
by using only one implantation step. The doses used to form the source/drain extensions are comparable
to the doses used in the two dimensional simulation setup. Again, the 3D structures were annealed by the
RTA and MSA combination of spike annealing followed by ash annealing. The structure resulted from
3D CAD simulation is displayed in Fig. 6.3(a), while the result after doping is displayed in Fig. 6.3(b).
Here, the gate electrode and the spacer stack was removed to exhibit the distribution of the dopants and
the gate oxide layer around the silicon n.
6.1.1.3 Device Simulation
The electrical simulations were performed assuming room temperature of 300 K. Several standard mod-
els were used in the device simulation and were already discussed in Chapter 2, but should briey be
referenced again for clarication. The Drift-Diffusion method was used for all kind of device simulations
in this chapter. The calculation of the band gap was done by using the model of Slotboom [91] including
Fermi-statistic and band gap narrowing. For generation-recombination the model of Shockley, Read, and
Hall was used [45]. The mobility calculation was done by using the Lombardi model for mobility degra-
dation due to surface roughness. The model of Masetti [46] was used to take mobility degradation due
to doping into account. Choos and Fletchers [48] model was used to simulate carrier-carrier scatter-
ing. For high-eld saturation and quasi-ballistic carrier transport, the Advanced Drift-Diffusion (ADD)
model presented in Chapter 3 was used. The calculation of the thermal resistances at each electrode was
done before in dependence on the geometrical dimensions of the different MOSFET devices. Finally,
quantum mechanical depletion at the silicon/silicon-oxide interface was simulated by using the modied
local density approximation (MLDA) [52]. First of all, the transfer characteristics at low drain voltages
(V
drain
=0.05V for all kind of devices) and at high drain voltages (V
drain
=V
DD
) were calculated. V
DD
is
differently dened by the ITRS for each kind of devices of the different technology node sub-groups (HP,
LSTP, LOP). In this work, however, the same voltages were used for all devices to ensure comparable
conditions. After the transfer characteristics were calculated, the output characteristics were simulated
at low gate voltages (V
gate
=V
DD
/2) and high gate voltages (V
gate
=V
DD
). Finally, the C-V characteristics
were computed using small signal analysis with an AC gate voltage with a frequency of 0.1 GHz.
6.1.2 Extraction of Electrical MOSFET Parameters
If different MOSFET architectures should be investigated and their performance should be compared,
different MOSFET parameters have to be extracted to make estimations about the electrical performance.
One of the most important parameter to be compared is the I
on
-I
off
relation. To draw qualitative conclu-
sions about which MOSFET architectures has the largest I
on
-I
off
relation, it is important to investigate
the on-current at xed leakage current values. These xed leakage current values have to be the same
for all CMOS device architectures considered. In this thesis, a linear interpolation of the transfer char-
acteristic was used to investigate the on-current at different xed leakage current values. The method
is similar to an assumed shift of the gate work function and, thereby, similar to a shift of the threshold
voltage. The principle is based on
y(x) = y
0
+ (x x
0
)
y
1
y
0
x
1
x
0
, (6.1)
where y
0
, y
1
, x
0
, and x
1
are available data points, e.g., of a set of measurements. The I
on
-I
off
relation has
to be calculated in two steps. At rst, the voltage shift of the original I-V transfer curve from numerical
simulation has to be calculated to obtain the xed specied values of the leakage current at zero gate
voltage. This has to be done by interpolation of the logarithmically scaled current values:
V =
(log(I
off,x
) log(I
0
))(V
1
V
0
)
log(I
1
) log(I
0
)
+V
0
. (6.2)
In Eq. (6.2), I
off,x
are xed leakage current values (13 overall in this work) for which the voltage shift
should be calculated, and I
0
, I
1
, V
0
, and V
1
are the original values of the transfer characteristic. The shift
of the voltage, calculated for the respective xed leakage current values, was used to obtain the shift of
the on-current for linear scaled I
on
:
I
on
= I
0
+
(I
1
I
0
)
(V
1
V
0
)
(V V
0
). (6.3)
For all kind of devices the same 13 xed off-currents I
off,x
were used to calculate the I
on
-I
off
relation.
Based on the I
on
-I
off
relation, the dynamic behavior of the MOSFET architectures can be calculated.
The dynamic behavior of a single device, in other words, the switching delay t
prop
without external load
capacitances, can be obtained by [92]
t
prop
=
C
gate
V
DD
I
on
. (6.4)
In Eq. (6.4), C
gate
is the gate capacitance which can be extracted from the maximum gate capacitance
value of the C-V simulations and V
DD
is the supply voltage. In case of the CV/I gure of merit, it is im-
portant to investigate t
prop
at xed leakage current values also. Therefore, the I
on
-I
off
relation calculated
before can be used to calculate the corresponding CV/I behavior, assuming a threshold voltage shift.
Additionally, several standard MOSFET parameters were extracted also. These parameters, however,
are in some case not suitable for a qualitative comparison of different MOSFET architectures to be
investigated. On the other hand, they are very useful for the extraction of SPICE parameters which is
demonstrated in Chapter 7. One of the most interesting parameters to be extracted is the carrier effective
mobility
eff
. These parameter can be obtained by a combination of Hamers method [74] and the Y-
function [75]. If the effective mobility should be extract, the threshold voltage V
th
, G
m
(see Eq. (6.6)),
and the mobility reduction above the gate-overdrive (V
gate
V
th
) have to be calculated rst. Based on
the basic equation of the drain current [8]
I
drain
=
W
L
gate
low
C
ox
(V
gate
V
th
)V
drain
1 + (V
gate
V
th
)
= G
m
(V
gate
V
th
)V
drain
1 + (V
gate
V
th
)
(6.5)
with
G
m
=
W
L
gate
C
ox
low
(6.6)
and the Y-function [75]
Y =
I
drain
g
m
=
W
L
gate
low
C
ox
V
drain
(V
gate
V
th
) (6.7)
it is easy to calculate V
th
and G
m
, since is eliminated by the Y-function, by choosing two points of
the transfer characteristic at low drain voltages, above the threshold voltage V
th
. The initial values of
the gate-overdrive (V
gate
V
th
) was estimated by a rst order approximation of the threshold voltage
calculated from the transfer characteristic [31]:
V
th,appr
= V
gate
drain
(6.8)
with
I
drain
=
1.0 10
7
A 1.0 m
L
gate
. (6.9)
After V
th
, G
m
, and were extracted, the low-eld carrier mobility
low
is calculated by
low
=
G
m
L
gate
C
ox
. (6.10)
Finally, the effective mobility can be obtained by solving
eff
=

low
1 + (V
gate
V
th
)
. (6.11)
Since the carrier mobility is strongly inuenced by the strength of the electric eld, induced by the gate
voltage, it is useful to plot
eff
over the effective eld F
eff
[8], which is can be obtained from
F
eff
=
(V
th
+ 0.5V )
3t
ox
+
(V
gate
V
th
)
6t
ox
. (6.12)
A further gure of merit to draw qualitatively conclusions about the electrostatic stability of MOSFET
devices is the DIBL. It can be calculated from
DIBL =
V
th,low
V
th,high
V
d,high
V
d,low
, (6.13)
where V
th,high
is the threshold voltage at high drain voltages and V
th,low
is the threshold voltage at low
drain voltages. The subthreshold slope (SSlope) at constant drain voltage and V
gate
below the gate over-
drive (V
gate
V
th
) was achieved by [8]
SSlope =
_
d(log(I
drain
))
dV
gate
_
1
. (6.14)
The last parameters extracted are the source/drain series resistances R
S/D
and the resistivity of the channel
R
ch
. This parameters can be calculated using the same methodology presented for the extraction of the
standard MOSFET parameters V
th
, G
m
, and .
6.2 Simulation Methodology Using the Example of High Performance Devices 69
6.2 Simulation Methodology Using the Example of High Performance De-
vices
It is not possible to discuss all devices investigated in this thesis (totally 24) in detail. Hence, only the
simulation of the high performance devices will be discussed in full length at this point. The results
for low operating power devices and low standby power devices are presented in numerical form in the
Appendix A.
6.2.1 Device Architecture Design
Four device architectures were investigated in this thesis: conventional bulk MOSFET, single gate fully
depleted silicon on insulator (SG FDSOI ) MOSFET, double gate fully depleted silicon on insulator (DG
FDSOI ) MOSFET, triple gate (TG) FinFET. The geometrical dimensions for high performance devices
were obtained from the 2007 ITRS [9]. The physical gate length is 13 nm for all devices. For the bulk
MOSFET, the SG FDSOI and the FinFET, a gate oxide thickness of 0.5 nm was used, while 0.6 nm gate
oxide thickness was used for the DG FDSOI, as proposed by the ITRS. The silicon body thickness of
the SG FDSOI was set to 3 nm, which is nearly a fourth of the physical gate length. This relation of
the silicon lm thickness to the physical gate length was obtained by observing the on-current and the
off-current at different gate lengths and body thicknesses, displayed in Fig. 6.4(a). At a body thickness
t
body
of about a fourth of the gate length the off-current is about ve orders of magnitude lower than the
on-current. At larger body thicknesses, I
off
rapidly increases (Fig 6.4(a)). This can be explained by an
efciently suppression of the short channel effect at very thin body thicknesses. Here, the gate electrode
has a better control over the channel region, while the electric eld of the drain electrode has the control
over the channel at larger body thicknesses, leading to high leakage due to the drain induced barrier
lowering effect.
Due to the fact that the device engineering community questions the applicability of simulation models
for the impact of surface roughness on the charge carrier mobility in SOI devices with ultra thin body
thicknesses, the existing traditional Lombardi model [47] was compared to a model recently developed
by Esseni [93] especially for SOI devices. Figure 6.4(b) displays the results of mobility extraction from
the literature for SOI devices with a body thickness of 3 nm [93] in comparison to simulations using the
Lombardi model. A good agreement between the results from the literature and the simulations using the
traditional Lombardi model was achieved (Fig. 6.4(b)). Therefore, the use of the conventional Lombardi
model for simulating SOI devices with very thin body thicknesses is valid as it does not underestimates
the impact of surface roughness on the charge carrier mobility. In contrast, if the scattering probability
is increased by a factor of 10, due to high electric elds, the Lombardi model slightly overestimates the
impact of surface roughness on the carrier mobility, compared to the results from the literature.
The electrostatic control of the gate over the channel is improved in DG FDSOI devices due to the second
gate electrode. Hence, it is possible to double the lm thickness compared to the SG FDSOI by keeping
the electrostatic control at a constant level. Therefore, t
body
of the DG FDSOI was set to 6 nm. In case
of the TG FinFET, the thickness of the n was set to the same of t
body
of the double gate, due to the fact
that the top gate contact has only a small impact on the electrostatic control, compared to the sidewall
gate contacts.
(a) (b)
Figure 6.4 I
on
-I
off
relation for different silicon body thicknesses and validation of the Lombardi model: (a)
I
on
(t
body
/L
gate
) and I
off
(t
body
/L
gate
); (b) Comparison between the model of Esseni for SOI MOSFETs [93] and
the conventional Lombardi model [47]
Another geometrical parameter to be engineered for fully depleted SOI devices is the buried oxide (BOX)
thickness t
BOX
. At thick buried oxide thicknesses, the drain potential at high drain voltages easily pen-
etrates under the gate stack and lowers the source barrier for the charge carriers (DIBL). This effect
reduces the control of the gate electrode over the channel region, even at small body thicknesses. If the
buried oxide is thin, the substrate electrode serves as reference potential also, which decreases the lateral
control of the drain electric eld and, therefore, leads to a suppression of the DIBL and SCE. Figure 6.5
displays the dependence of the buried oxide thickness on the DIBL and the SSlope. By minimizing the
thickness of the buried oxide, the DIBL can be efciently be reduced. On the other hand, if the buried
oxide thickness falls below the size of the physical gate length, the subthreshold slope starts to increase.
This can be explained by an increase of the off-current due to the additional ground potential seen by the
charge carriers in the silicon lm. Therefore, a buried oxide thickness of about half size of the physical
gate length was found to result in the best DIBL-SSlope relation. This rule was applied to each of the
three devices based on a buried oxide (SG FDSOI, DG FDSOI, TG FinFET), whether a ground plane
doping [21] was used or the substrate was assumed to be undoped.
The next parameter to be designed is the doping of the substrate and the silicon lm. The channel
doping of the bulk MOSFET mainly depends on the amount of the implanted ion dose, used for creating
the pocket implants to suppress short channel effects. In average, a channel doping concentration of
5 10
18
cm
3
of arsenic and boron, respectively, was used in the bulk MOSFETs investigated in this
work. The substrate and the silicon bodies of the SOI devices, on the other hand, were only lightly
doped (1 10
15
cm
3
). However, due to the lightly doped silicon bodies of the SOI devices, it is not
possible anymore to tune the threshold voltage by the channel doping concentration. In this work, a
threshold voltage tuning by gate work function adjustment was assumed. The nal structures of the high
performance nMOSFETs are displayed in Fig. 6.2 (Fig. 6.2(a) bulk MOSFET, Fig. 6.2(b) SG FDSOI,
Fig. 6.2(c) DG FDSOI), and 6.3 (TG FinFET).
Figure 6.5 DIBL and SSlope behavior for different buried oxide thicknesses
6.2.2 Electrical Behavior
First of all, the transfer characteristics and output characteristics of the four MOSFET architectures were
investigated. Figure 6.6 displays the transfer (Fig. 6.6(a)) and output (Fig. 6.6(b) ) characteristics of the
13 nm gate length bulk MOSFETs. Both devices, NMOS and PMOS, show a well controlled electrostatic
behavior. The on-current of the NMOS was calculated to be 1.3 mA/m and 0.8 mA/m for the PMOS.
The off-currents of both devices have, in spite of the very small gate length, a relatively small value of
10 nA/m. Due to the pocket implants, the DIBL effect is 80 mV/V and 75 mV/V for NMOS and PMOS,
respectively. The subthreshold slope was calculated to be 82 mV/decade for both devices, which is in a
good range.
(a) (b)
Figure 6.6 Transfer and output characteristic of the HP bulk MOSFET: (a) Transfer characteristic; (b) Output
characteristic
(a) (b)
Figure 6.7 Transfer and output characteristic of the HP SG FDSOI MOSFET: (a) Transfer characteristic;
(b) Output characteristic
Figure 6.7 displays the transfer (Fig. 6.7(a)) and output (Fig. 6.7(b)) characteristic of the single gate FD-
SOI MOSFETs. The devices show very high on-current values, which were calculated to be 1.9 mA/m
for the NMOS and 0.8 mA/m for the PMOS. An off-current value of 0.2 A/m was achieved for both
kind of devices. Due to the very thin body and thin buried oxide thickness used for this devices, the
DIBL could be reduced to 63 mV/V at a subthreshold slope of 77 mV/decade.
Figure 6.8 shows the transfer characteristic (Fig. 6.8(a)) and the output characteristic (Fig. 6.8(b)) of the
DG FDSOI devices. The on-current of the NMOS was calculated to be 1.85 mA/m and 1.1 mA/m for
the PMOS. Because all currents were calculated to 1 m of the physical device width, the drain currents
of the DG FDSOI MOSFETs have to be divided by two to obtain a normalization for 1 m effective
channel width. The off currents of the two MOSFETs were calculated to be 0.15 A/m. The DIBL of
the NMOS is 75 mV/V and 61 mV/V for the PMOS at a subthreshold slope of 73 mV/decade.
(a) (b)
Figure 6.8 Transfer and output characteristic of the HP DG FDSOI MOSFET: (a) Transfer characteristic;
(b) Output characteristic
Although two gate electrodes were used, it seems like in a rst view that the double gate has only small
advantages compared to the single gate FDSOI architecture.
By looking at Fig. 6.9, which displays the transfer characteristic (Fig. 6.9(a)) and output characteristic
(Fig. 6.9(b)) of the triple gate FinFET, the excellent electrostatic behavior of this device architecture can
already be assessed. The effective width of the FinFET was calculated by
W
eff,FinFET
= 2 H
n
+t
n
(6.15)
to be 0.1265 m. To normalize the drain currents of the HP FinFET devices to an effective width of
1 m, I
drain
had to be divided by a factor of 0.1265. The on-current of the NMOS was calculated with
a value of 1.2 mA/m and 0.64 mA/m for the PMOS. The leakage current of the NMOS devices has a
value of 0.3 nA/m, while I
off
of the PMOS was calculated to be 2 nA/m. A DIBL of 70 mV/V was
achieved with the FinFET architecture at a subthreshold slope of 70 mV/decade.
(a) (b)
Figure 6.9 Transfer and output characteristic of the HP TG FinFET: (a) Transfer characteristic; (b) Output
characteristic
6.2.2.1 Charge Carrier Mobility
If different device architectures should be compared, not only the standard transfer and output character-
istic are of interest. The improvement of the carrier mobility is an important issue for device engineers,
which can be achieved by using different MOSFET architectures. Figure 6.10 shows the effective elec-
tron and hole mobility, extracted using Eq. (6.11) and the eld effect electron and hole mobility
fef
[94]
for the bulk (Fig. 6.10(a)), the SG FDSOI (Fig. 6.10(b)), the DG FDSOI (Fig. 6.10(c)), and the TG Fin-
FET (Fig. 6.10(d)). The eld effect mobility
fef
[94] denotes the impact of the electric eld on the
charge carrier mobility. It can be calculated by
fef
=
L
gate
WC
ox
V
drain
g
m
. (6.16)
(a) (b)
(c) (d)
Figure 6.10 Effective
eff
and eld effect
fef
mobility of four MOSFET architectures investigated: (a) Bulk
MOSFET; (b) SG FDSOI ; (c) DG FDSOI ; (d) TG FinFET
From Fig. 6.10, the problem of very high electric elds, present for all of the four device architectures
investigated can be recognized. Due to the fact that the carrier mobility follows the model of Caughey
and Thomas [50] (Eq. (2.29)), the effective mobility is strongly reduced due to high electric elds, which
is typical for these small sized MOSFETs. The reason for these extremely high electric elds can be
found by looking at the impact of the gate oxide thickness (Eq. (6.12)). Due to the lightly doped channel
and the good electrostatic behavior, the DG FDSOI devices show the highest mobility followed by the
SG FDSOI. The carrier mobilities of the SOI devices are more than twice as high as the carrier mobilities
of the bulk MOSFETs, which can be explained by the missing heavily doped pocket implants used in the
bulk MOSFETs.
6.2.2.2 I
on
-I
off
and CV/I Figure of Merit
It was already mentioned in Subsection 6.1.2 that the comparison of the electrical performance of differ-
ent MOSFET architectures has to be done at the same leakage current values. Therefore, the on-current
values at xed leakage current values were extracted (see Subsection 6.1.2). The I
on
-I
off
and the CV/I
gure of merit of the 32 nm technology node of the 2007 ITRS served as a criterion for the quality of
(a) (b)
Figure 6.11 I
on
-I
off
and CV/I characteristic of the HP bulk MOSFET: (a) I
on
-I
off
characteristic; (b) CV/I char-
acteristic
the investigated MOSFET architectures. The reference MOSFET performance characteristics were sim-
ulated by MASTAR [95]. Because of all forecasts of the electrical performance presented in the 2007
ITRS were obtained from MASTAR simulations, the results from MASTAR used in this thesis are an
adequate reference and accepted by the device engineering community.
No reference values for high performance bulk MOSFETs and TG FinFETs were available in the 32 nm
technology node of the 2007 ITRS during this work. Hence, the I
on
-I
off
and CV/I MASTAR simulation
results for the single gate FDSOI were used for reference. Figure 6.11 shows the I
on
-I
off
and CV/I
relation of the conventional bulk MOSFETs compared to the MASTAR simulation results of the SG
FDSOI. It has to be noted that the ITRS handles PMOS devices to have 50 % of the NMOS on-currents
at the same leakage current values. As can be seen in Fig. 6.11(a), the bulk MOSFET is not able to meet
the performance demanded by the ITRS, due to approximately 60 % lower on-current values. On the
other hand, the slope of the I
on
-I
off
characteristic is nearly the same compared to the reference curve.
(a) (b)
Figure 6.12 I
on
-I
off
and CV/I of the HP SG FDSOI MOSFET: (a) I
on
-I
off
characteristic; (b) CV/I characteristic
(a) (b)
Figure 6.13 I
on
-I
off
and CV/I characteristic of the HP DG FDSOI MOSFET: (a) I
on
-I
off
characteristic;
(b) CV/I characteristic
Hence, the use of mechanical stress can probably shift the curve closer to the reference values. Due to
the low on-currents and the high gate-capacitance resulting from the high channel doping concentration,
the bulk MOSFET can again not fulll the switching delay requirements of the ITRS (Fig. 6.11(b)).
Figure 6.12 displays the I
on
-I
off
and CV/I characteristics of the SG FDSOI MOSFETs. Compared to
the electrical behavior of the bulk MOSFET (Fig. 6.11), the on-current of the NMOS device is much
higher. But also the SG FDSOI is not able to fulll the requirements of the ITRS, as well in case of
the I
on
-I
off
relation (Fig. 6.12(a)), as in the CV/I case (Fig. 6.12(b)). The derivation from the reference
performance still is about 23 %. Mechanical stress might help also to improve the device performance to
fulll the requirements of the ITRS.
The I
on
-I
off
and CV/I characteristics of the DG FDSOI MOSFETs are presented in Fig. 6.13. Like
already investigated for the bulk MOSFETs and the SG FDSOI MOSFETs, the DG FDSOI is not able to
(a) (b)
Figure 6.14 I
on
-I
off
and CV/I characteristic of the HP TG FinFET :(a) I
on
-I
off
characteristic; (b) CV/I char-
acteristic
6.3 Process Options for MOSFET Performance Improvement 77
meet the requirements of the ITRS also. Although the slope of the I
on
-I
off
characteristic tends to higher
on-currents at xed leakage currents, compared to the slope of the SG FDSOI, the on-current is still
below the reference values of the ITRS (Fig. 6.13(a)). Also the switching delay of the DG FDSOI is too
high, in comparison to the reference values (Fig. 6.13(b)).
Finally, the I
on
-I
off
and CV/I characteristics of the TG FinFET were compared to the ITRS reference
values of the SG FDSOI MOSFET in Fig. 6.14. The on-current is still too low in comparison to the ref-
erence values (Fig. 6.14(a)). The TG FinFET, however, shows an excellent switching behavior, which
nearly fullls the requirements of the ITRS (Fig. 6.14(b)). This results from the lower fringing capac-
itances between the gate electrode and the source/drain electrodes, as the source/drain contacts were
placed to the sides of the n (Fig. 6.1(d)).
If the electrical performance of the four MOSFET architectures is directly compared to each other
(Fig. 6.15) it becomes clear that the bulk MOSFET (circles) shows the lowest on-current (Fig. 6.15(a))
and the longest switching delay (Fig. 6.15(b)) compared to the SOI devices (SG FDSOI: squares; DG
FDSOI: triangles; TG FinFET: stars). However, the slope of the I
on
-I
off
curve of the bulk MOSFET
is comparable to slope of the I
on
-I
off
characteristic of the DG FDSOI MOSFET (Fig. 6.15(a) (trian-
gles)). The I
on
-I
off
characteristics of the SG FDSOI (squares) and the TG FinFET (stars) have the same
on-current and the same slope, although the electrostatic behavior of the FinFET is better than the electro-
static of the SG FDSOI. Furthermore, the DG FDSOI and the TG FinFET have nearly the same dynamic
performance (Fig. 6.15(b)).
(a) (b)
Figure 6.15 Comparison of the I
on
-I
off
and CV/I characteristic of the four NMOS device architectures inves-
tigated: (a) I
on
-I
off
6.3 Process Options for MOSFET Performance Improvement
The improvement of the electrical performance by using different process options is a commonly used
procedure in fabricating modern CMOS devices. Especially mechanical stress has become one of the
most common performance booster (see Chapter 4). Mechanical stress has in particular become an
option for PMOS devices to equalize the NMOS and PMOS device performance, and therefore, to use
the same layout area of the NMOS and PMOS to save silicon area.
6.3.1 Mechanical Stress
One process option, a combination of using contact etch stop layers and gate replacement technique, for
generating mechanical stress along the channel direction was presented in Chapter 4 (Fig. 6.16). The
maximum achievable stress using this method was calculated to be either 1.1 GPa tensile or 1.1 GPa
compressive stress, if a respective intrinsic stress of the CESL layer of 2.5 GPa [84] is used. A second
option for inducing mechanical stress perpendicular to the channel direction was presented in the lit-
erature [82]. Here, a modication of a standard shallow trench isolation (STI) process was used. The
modication is based on a densication annealing process after chemical mechanical polishing (CMP).
A trench is etched into the silicon, followed by a short oxidation step. After that, silicon oxide was de-
posited to ll up the trench completely. Then, CMP was used to level the oxide layer and to remove
the whole silicon oxide from the silicon surface. Finally, the lled trenches were annealed (30 min at
1000
C) to solidify the deposited oxide. This procedure results in a tensile stress of 1.4 GPa perpendicu-
lar to the channel (Fig. 6.16(b)). These options were used to improve the carrier mobility behavior of the
NMOS and PMOS devices and so, shift the I
on
-I
off
relation and the CV/I behavior to the specications
dened by the ITRS.
(a) (b)
Figure 6.16 Process options for creating mechanical stress: (a) Gate replacement technique to increase stress in
the channel region [83]; (b) Post-densication STI forming process for achieving tensile stress perpendicular to
the channel [82]
In case of the bulk NMOS and PMOS transistors, 1.1 GPa and -0.8 GPa tensile stress along the channel,
respectively, was applied to the device. In addition, the post-densication method of the STI forming
process was applied to both MOSFET architectures, which resulted in a tensile stress of 1.4 GPa per-
pendicular to the channel direction. These two values are the maximum values of mechanical stress that
were calculated by using the two process options presented in Fig. 6.16.
In spite of the large values of mechanical stress applied to the NMOS transistor, it was not possible to
fully shift the I
on
-I
off
characteristic and the CV/I behavior of conventional bulk MOSFETs to the speci-
cations of the ITRS (Fig. 6.17). Only a slight improvement was observed. The I
on
-I
off
characteristic of
(a) (b)
Figure 6.17 I
on
-I
off
and CV/I characteristic of the HP bulk MOSFET including mechanical stress: (a) I
on
-I
off
the PMOS transistor, however, could be pushed to the ITRS specications by the applied stress values.
The reason for the different reaction of the NMOS and PMOS transistor on the inuence of mechani-
cal stress can be found in the different piezo coefcients for electrons and holes for <110> channels.
The piezo coefcients for electrons and holes are presented in Tab. 4.5. As can be seen, the coefcients
for electrons are much smaller than for holes for the <110> channel direction. However, it was also
not possible to achieve the same dynamic behavior for the PMOS as required by the ITRS (Fig. 6.17(b)
circles), although the I
on
-I
off
characteristics corresponds very well (Fig. 6.17(b)).
Only a small improvement by mechanical stress was also observed in case of the NMOS SG FDSOI
transistor (Fig. 6.18(a)). Here, 1 GPa of tensile mechanical stress was applied along the channel direc-
tion to the NMOS. Using compressive stress of 800 MPa along the channel and tensile stress of 1 GPa
perpendicular to the channel pushes the I
on
-I
off
characteristic of the PMOS transistor nearly to the same
(a) (b)
Figure 6.18 I
on
-I
off
and CV/I of the HP SG FDSOI MOSFET including mechanical stress: (a) I
on
-I
off
charac-
teristic; (b) CV/I characteristic
(a) (b)
Figure 6.19 I
on
-I
off
and CV/I characteristic of the HP DG FDSOI MOSFET including mechanical stress:
(a) I
on
-I
off
behavior like the NMOS transistor (Fig. 6.18(a)). This complies with an equalization of the layout area
of the NMOS and PMOS transistor. Also in case of the dynamic behavior, an equalization of the NMOS
and PMOS performance was achieved (Fig. 6.18(b)). However, it was not possible again to reach the
static and dynamic requirements of the ITRS.
The most promising device architecture for fullling the requirements of the ITRS seems to be the DG
FDSOI. By applying tensile stress of 1 GPa and compressive stress of 800 MPa along the channel direc-
tion to the NMOS and PMOS, respectively, the I
on
-I
off
characteristics of both devices fulll the require-
ments of the ITRS (Fig. 6.19(a)). Furthermore, an equalization of the layout area of the both devices was
achieved. Looking at the dynamic behavior displayed in Fig. 6.19(b), the DG FDSOI MOSFETs is again
not corresponds with the specications, although the on-currents required were achieved.
(a) (b)
Figure 6.20 I
on
-I
off
and CV/I characteristic of the HP TG FinFET including mechanical stress: (a) I
on
-I
off
Due to the fact that the TG FinFET showed already nearly the same I
on
-I
off
relation as the SG FD-
SOI (Fig. 6.15(a)) without using mechanical stress, the I
on
-I
off
relation remains nearly the same under
mechanical stress conditions. The shift of the I
on
-I
off
relation for the NMOS is only small, while the
PMOS on-current was equalized to the NMOS. However, higher values of mechanical stress (1 GPa
in all directions) have to be applied to the FinFET to achieve the same on-currents as for the SG FD-
SOI MOSFETs (Fig. 6.20(a)). Like the other three device architectures investigated, the FinFET is also
not able to meet the ITRSs dynamic requirements (Fig. 6.20(b)).
Figure 6.21 displays the comparison between the four different device architectures including the im-
provement by mechanical stress. Again, all devices were compared to the SG FDSOI specications
by the ITRS. The bulk MOSFET have the lowest on-current compared to the SOI MOSFETs and the
FinFETs, but the same slope of the I
on
-I
off
like the DG FDSOI (Fig. 6.21(a)). Furthermore, due to me-
chanical stress, the SG FDSOI has now nearly the same I
on
-I
off
relation like the DG FDSOI. The I
on
-I
off
relation of the FinFET is now in between the bulk MOSFET and the FDSOI MOSFETs. In case of the
dynamic behavior, the FinFET still has the fastest switching speed, while the bulk still has the largest
delay (Fig. 6.21(b)). The dynamic performance of the SG FDSOI and the DG FDSOI is comparable,
although the DG has a lower delay at high leakage current values.
(a) (b)
Figure 6.21 Comparison of the I
on
-I
off
and CV/I characteristic of the four NMOS device architectures inves-
tigated including mechanical stress: (a) I
on
-I
off
6.3.2 Impact of Contact Resistances
In Subsection 6.3.1 the improvement of the device performance by mechanical stress was presented. An
efcient layout area reduction could be achieved by equalization of the on-currents of NMOS and PMOS
devices. Furthermore, the static behavior of the SOI devices and the FinFET devices could be improved
in that way, to roughly fulll the requirements of the ITRS. However, the simulations in Subsections 6.2.2
and 6.3.1 were done without taking contact resistances into account. As it was already presented in
Chapter 5, contact resistances become a great problem if the device dimensions continue to shrink. In
case of the HP devices presented above a source/drain contact length L
co
of four times the gate-length
(nearly 50 nm) was used. Therefore, the contact area was normalized to the device width 1 m, which
(a) (b)
Figure 6.22 I
on
-I
off
and CV/I characteristic of the HP bulk NMOSFET including mechanical stress and contact
resistances: (a) I
on
-I
off
results in an effective contact area of nearly 0.05 m
2
. For investigating the impact of contact resistances
on the device architectures investigated, two different simulations were performed. First of all, the same
simulation setup as presented before was used, but taking Schottky contacts at the metal/semiconductor
interfaces of source and drain into account. Secondly, the trench concept presented in Chapter 5 and the
additional doping by assuming a spin-on-dopant source [37] was used to reduce the Schottky contact
resistances. Thereby, an etch depth of the trench of 10 nm and an arsenic doping concentration of the
spin-on-dopant source of 1 10
22
cm
3
was assumed.
Figure 6.22 displays the static (Fig. 6.22(a)) and dynamic behavior (Fig. 6.22(b)) of the bulk NMOSFET.
By using plain contact areas and the same implantation and annealing conditions as presented before, the
on-current was reduced by a factor of 3.5 compared to the simulation results without taking contact re-
(a) (b)
Figure 6.23 I
on
-I
off
and CV/I of the HP SG FDSOI NMOSFET including mechanical stress and contact
resistances: (a) I
on
-I
off
(a) (b)
Figure 6.24 I
on
-I
off
and CV/I characteristic of the HP DG FDSOI NMOSFET including mechanical stress and
contact resistances: (a) I
on
-I
off
sistances into account was observed. Compared to that, the use of the contact trenches and the additional
doping results only in an on-current degradation of about a factor of 1.31.
If the contact resistances are switched on in the simulation setup of the SG FDSOI devices, planar contact
pads and the standard implantation and annealing conditions presented in Subsubsection 2.2.1.3 and [90]
result in I
on
reduction factor of 2.8 (Fig. 6.23). This can be reduced by the process options for contact
resistances reduction by a factor of 1.46.
The strongest effect of contact resistances impact was observed in case of the DG FDSOI (Fig. 6.24).
Due to the doubling of the on-current by the two channels, the voltage drop at the contact interfaces is
doubled, too. This results in a on-current degradation factor of 11.23 if the planar contact pads were
assumed. Even the use of the contact trenches and the higher surface doping concentration leads to
(a) (b)
Figure 6.25 Structures used for calculating contact resistances of the TG FinFET NMOS and PMOS devices:
(a) Plain contact pad implanted; (b) Trench contact with doping glass doping
a performance loss, which is two times higher than in case of the bulk MOSFET and the SG FDSOI
transistor (Fig. 6.24).
The full size simulation of three dimensional devices is expensive concerning the computational time.
Hence, the contact resistances of FinFETs were calculated separately by simulating only the active con-
tact pads of the FinFET architecture. Consequently, the calculated resistances were connected as series
resistances to the source and drain electrodes in a Mixed-Mode simulation. To simplify the normalization
of the on-currents to 1 m effective width, the width of the contact pads were chosen to be W
eff
of the
n. Like is was done for the planar devices in the two dimensional simulation, four times the gate length
was used for the contact pad length. Figure 6.25 shows the three dimensional structures used to calcu-
late the contact resistances of the TG FinFET. The plain pad was in a conventionally way implanted and
annealed. The trench contact pad was doped by using a highly doped spin-on-doping source, to achieve
a homogeneous doping at the sidewalls of the contact trench. An etch depth of 10 nm was assumed.
Although the current density in the TG FinFET is more than twice compared to the planar devices, the
inuence of the contact resistances on the drive current is much lower than it was observed for the DG
FDSOI. If the planar contacts are used, the drive current is reduced by a factor of 3.5. The area enlarge-
ment by the trenches and the homogeneous doping of the contact sidewalls reduce the performance loss
by a factor of 2, which results in a drive current 52 % lower than without taking contact resistances into
account.
(a) (b)
Figure 6.26 I
on
-I
off
and CV/I characteristic of the HP TG FinFET including mechanical stress and contact
resistances: (a) I
on
-I
off
6.4 Assessment of Different CMOS Device Architectures
Not only high performance devices for the 32 nm technology node of the ITRS were investigated in this
work, but also low operating power devices and low standby power devices. In this section, the electrical
performances of the four MOSFET architectures are compared to assess which architecture is the most
promising for the different 2007 ITRS requirements. The simulations of the low power and low standby
power devices were done in the same way presented in Sections 6.2 and 6.3.
6.4 Assessment of Different CMOS Device Architectures 85
Figure 6.27 Comparison of the static electrical behavior of the four
high performance NMOSFET architectures investigated
6.4.1 Static Behavior
At rst, the I
on
-I
off
relation at different gate work functions of the four high performance devices was
compared. Figure 6.27 shows the static behavior of the bulk MOSFET (circles), SG FDSOI MOSFET
(squares), DG FDSOI MOSFET (triangles), and TG FinFET (stars) including mechanical stress and
improved contact pads. As can be seen, the single gate FDSOI shows the best static behavior. The
double gate FDSOI MOSFET shows the worst static electrical behavior compared to the other three
architectures due to the strong impact of contact resistances. The conventional bulk MOSFET and the
TG FinFET are comparable. The numerical values of the electrical behavior of the HP MOSFET devices
investigated are listed in Tab. A.3 in Appendix A.1.
The I
on
-I
off
relation at different gate work functions of the four low operating power devices is displayed
in Fig. 6.28. It was already observed in case of high performance devices that the SG FDSOI MOS-
FET exceeds the static electric performance of the other three device architectures investigated. The bulk
MOSFET, on the other hand, shows the lowest performance, while the DG FDSOI MOSFET and the TG
FinFET have a comparable behavior situated between the bulk MOSFET and the SG FDSOI. The nu-
merical values of the electrical behavior of the LOP MOSFET devices investigated are listed in Tab. A.5
in Appendix A.2. Finally, Fig. 6.29 shows the I
on
-I
off
characteristics of the low standby power devices.
Differently to the results presented before, the DG FDSOI exceeds the performance of the other archi-
tectures investigated. The SG FDSOI and the TG FinFET have a comparable on-current. The static
electrical performance of the bulk MOSFET is far away from the ITRS specications, although it is still
an option for low standby power devices in the ITRS. The numerical values of the electrical behavior of
the LSTP MOSFETs investigated are listed in Tab. A.7 in Appendix A.3.
Figure 6.28 Comparison of the static electrical behavior of the four low
operating power NMOSFET architectures investigated
Figure 6.29 Comparison of the static electrical behavior of the four low
standby power NMOSFET architectures investigated
6.4.2 Dynamic Behavior
In the previous subsection, the quality of the four different device architectures was compared by the
relation of their drive currents and leakage currents. In this subsection, the switching speed of the four
device architectures is compared to the high performance, low operating power and low standby power
requirements of the 2007 ITRS. Figure 6.30 shows the CV/I characteristics of the four high performance
NMOS devices. As can be seen, the TG FinFET has the fastest switching speed at xed leakage currents.
Although the SG FDSOI MOSFET has the best I
on
-I
off
the parasitic capacitances in this planar device
are limiting the switching speed. The parasitic capacitances lead furthermore to very low switching speed
Figure 6.30 Comparison of the dynamic electrical behavior of the four
high performance NMOSFET architectures investigated
of the bulk MOSFET. The DG FDSOI MOSFET shows a switching speed, comparable to the SG FDSOI
MOSFET.
Figure 6.31 shows the CV/I characteristics of the four low operating power CMOS devices. Here
again, the switching speed of the TG FinFET exceeds the speed of the other three architectures. The SG
FDSOI MOSFET and the DG FDSOI MOSFET have a comparable delay, while the bulk MOSFET is no
option at leakage currents smaller than 1 nA. Furthermore, the TG FinFET is the only architecture nearly
fullling the requirements of the ITRS for low operating power devices.
low operating power NMOSFET architectures investigated
low standby power NMOSFET architectures investigated
Finally, the CV/I characteristics of the four low standby power MOSFET architectures is displayed in
Fig. 6.32. Like already shown, the dynamic electrical behavior of the TG FinFET meets the requirements
of the ITRS, which could not be achieved for any other device architecture discussed in this work before.
The DG FDSOI nearly fullls the requirements, while the SG FDSOI MOSFET and especially the bulk
MOSFET are no options for this kind of devices.
6.4.3 Area Consumption and Process Effort
The decision for a specic device architecture not only depends on the electrical performance. The
questions of how much layout area can be saved by using a specic CMOS device architecture and
how much additional effort has to be spent for processing these devices have to be answered. For bulk
MOSFETs the answers are already clear, because bulk MOSFETs are still the commonly used transistors
for logic and memory applications. The layout area of a device can simply be estimated by the W/L
gate
relation, which was in most of the cases set to 1 for NMOS transistors and 2 for PMOS transistors. The
same relation can probably be used if SG FDSOI MOSFETs should be used instead of bulk MOSFETs.
In principle, the layout is the same for both architectures. However, SOI devices need a SOI wafer which
is more expensive than conventional silicon substrates. On the other hand, several process steps needed
for processing bulk MOSFETs can be missed out in a SOI process, e.g. the forming of the n- and p-well
and the pocket implants. In this case, a cost versus process effort decision has to be made. Of course, the
SG FDSOI devices exceed the electrical performance of comparable bulk MOSFETs. Therefore, they
really are an option for replacing bulk MOSFETs in the future.
Double gate FDSOI MOSFETs can be used for efciently saving layout area, as the effective width of
this devices is approximately twice as high compared to single gate devices. Therefore, the relation
W/L
gate
can be set to 0.5 in case of NMOS and 1 in case of PMOS transistors. The possibility to design
more complex circuits with twice as much devices on a chip than by using single gate transistors would
be a major advantage of DG FDSOI devices. Furthermore, a more precisely switching behavior could
be achieved and the static power dissipation would be reduced, due to the better electrostatic control by
the two gate electrodes. However, the processing of double gate transistors is more complex, since the
buried gate electrode has to be formed either before bonding the silicon body on the buried oxide or,
e.g., by a special process step like the silicon on nothing (SON) process proposed in [96]. If the buried
gate electrode would be formed before bonding the silicon body on the buried oxide, one has to deal
with alignment problems during the lithography of the top gate electrode. This increases the probability
of variability of the electrical device performance. Therefore, it is doubtful if this architectures will
overbalance in the future against single gate devices, although the electrical performance is excellent and
an efcient layout area reduction can be achieved.
FinFET devices turned out during the device investigation part as some kind of multi purpose transistors,
which can be used for either high performance, low standby power, or low operating power applications.
Furthermore, the layout area can efciently be reduced due to the three dimensional architecture. The
big advantage of this devices is the W/L
gate
independent on the planar width. Furthermore, not only SOI
substrates have to be used for processing these devices [97], which is an advantage compared to planar
SOI devices. On the other hand, it was discussed in the literature [25, 26] that processing of FinFETs
still has several problems to be solved. First of all, line edge roughness (LER) is a big problem. This
effect results from lithography and etching processes and leads to a waviness of the ns. Secondly,
ion implantation is in particularly problematic for FinFETs, especially if the pitch distance between
the ns decreases. Thus, shadowing effects prevent the implantation of the whole n to the ground.
Finally, the silicon can sometimes not completely be re-crystallized during annealing, if very thin ns
were used. This leads to poly-crystalline channels and, therefore, to a negative impact on the device
performance [26]. Although the FinFET showed an excellent behavior in the device investigation section,
the problems mentioned above rst have be controlled if the FinFET should replace conventional bulk
MOSFET architectures.
Chapter 7
Compact Modeling of Different CMOS
Device Architectures and Circuit
Simulations
Chapter 6 dealt with a comparison of the electrical performance of four different CMOS device archi-
tectures. Triple gate FinFETs were found to be some kind of multi purpose devices, feasible for every
application class dened by the International Technology Roadmap for Semiconductors (ITRS) 2007 [9].
Conventional bulk MOSFETs, on the other hand, showed in particular a dynamic electrical performance
not corresponding to the requirements of the ITRS. In this chapter, the four device architectures pre-
sented in Chapter 1 are investigated under integrated circuit (IC) conditions. Four simple circuit schemes
were used in this work: inverter, ring-oscillator (including seven inverter stages), 4-bit ripple carry adder,
and 6 transistor static random access memory (6-T SRAM) cell. SPICE simulations were performed to
evaluate the performance of these circuits. Compact model parameters of the different MOSFET archi-
tectures were extracted from the TCAD transfer characteristics, transconductance characteristics, output
characteristics, and C-V characteristics of the gate capacitance. In this work, the EPFL-EKV compact
model [63] was chosen for compact modeling of the four device architectures. Because the EPFL-EKV
model was originally designed to describe the behavior of conventional single gate bulk MOSFET de-
vices, a method to extend the compact model application for multi-gate MOSFETs is presented.
7.1 SPICE Parameter Extraction Methodology
7.1.1 Extraction of Basic MOSFET Parameters
Basically, the extraction of the compact model parameters is based on the method presented in Subsec-
tion 6.1.2. By coupling Hamers method [74] and the Y-function [75], ve basic parameters, U0, THETA,
KP, VTO, and E0 were extracted to be used in the EKV model. These parameters correspond to the low-
eld mobility
low
(Eq. (6.10)), mobility reduction coefcient (Eq. (6.5)), low-eld transconductance
g
m,low
, the low-eld threshold voltage V
th,low
(Eq. (6.7)), and the critical electrical eld F
crit
(Eq. (6.12),
respectively. The critical electric eld was in this thesis dened by the effective electric eld (Eq. (6.12))
at V
gate
equal to V
th,low
, where the low-eld mobility starts to decrease. The advantage of this method
91
92 7 Compact Modeling and Circuit Simulation
is the simpleness. Only two characteristics, transfer characteristic at low drain voltages, e.g. at 50 mV,
and the complementary transconductance characteristic are needed to extract the parameters. Following
the extraction of the ve basic values, several additional parameters (VMAX, LAMBDA, DL, NSUB,
PHI, Q0, LETA, CGBO, CGSO, CGDO, RD, and RS) of the EPFL-EKV model have to be tted by hand
to reproduce the electrical behavior of MOSFET devices. Alternatively, this can be done by using opti-
mization algorithms. The complete parameter set of the EPFL-EKV compact model is listed in the EKV
manual [63]. It was found in this work that the best way for tting the remaining parameters is to start
with the adjustment of the C-V characteristic of the gate capacitance. Here, mainly CGBO, CGSO, and
CGDO have to be changed, until the maximum value of the gate capacitance is reached. After that, the
low-eld transfer characteristic has to be reproduced by changing parameters for the channel length mod-
ulation (DL mainly bulk MOSFETs, LETA, and Q0 mainly for SOI devices) and the subthreshold slope
(NSUB and PHI). If the low-eld threshold voltage is corrected by channel length modulation and the
subthreshold slope is reached, the drain induced barrier lowering (DIBL) can be set by tting LAMBDA
to achieving the right behavior of the output characteristic at low gate voltages (e.g. V
gate
= V
drain
/2).
Finally, the saturation velocity VMAX and the series resistances RD and RS are obtained by adjusting
the model to the high-eld transfer characteristic and output characteristic.
Table 7.1 Compact model parameters of the 32 nm bulk and SG FDSOI NMOS transistors. The notation of the
EKV parameter le was used to directly transfer the parameters into an EKV modelcard
Parameter Bulk SG FDSOI Description
LEVEL 55 55 Compact model selection (55=EPFL-EKV V.2.6)
TOX 1.2e-9 m 1.2e-9 m Gate oxide thickness
XJ 12e-9 m 10e-9 m Source/drain junction depth
DL -6.82e-9 m 0 m Channel length modulation
U0 93.32 cm
2
/Vs 264.9 cm
2
/Vs Low eld mobility
THETA 1.98 V
1
2.38 V
1
Mobility reduction factor
KP 2.3e-4 A/V 6.5e-4 A/V Low eld transconductance
E0 2.8e8 V/cm 2.8e8 V/cm Critical electric eld
VTO 0.507 V 0.523 V Low eld threshold voltage
VMAX 3.16e5 m/s 2e5 m/s Saturation velocity
LAMBDA 1.361 1.3 DIBL factor
NSUB 8.04e19 cm
3
1.3e19 cm
3
Substrate doping concentration
PHI 1.645 0.7 Subthreshold slope factor
Q0 0 0 Reverse charge
LETA 0.1 0.3 Additional channel length modulation
CGBO 6e-11 F/m 4e-11 F/m Gate to bulk capacitance
CGSO 6e-11 F/m 4e-11 F/m Gate to source capacitance
CGDO 6e-11 F/m 4e-11 F/m Gate to drain capacitance
RD 55 5 Drain contact resistance
RS 55 5 Source contact resistance
7.1 SPICE Parameter Extraction Methodology 93
7.1.2 Bulk MOSFETs and Single Gate FDSOI MOSFETs
Bulk MOSFETs and single gate FDSOI MOSFETs with physical gate lengths of 32 nm (presented
in [98]) and 20 nm (low standby power devices discussed in Chapter 6) were used for the SPICE param-
eter extraction and the later circuit simulations. All devices have a physical oxide thickness of 1.2 nm. A
body thickness of 10 nm and 5 nm was used for the 32 nm and 20 nm FDSOI devices, respectively. The
buried oxide thickness of the 32 nm FDSOI devices was set to 20 nm, while 10 nm of t
BOX
was used for
the 20 nm FDSOI devices. A more detailed description of the 32 nm MOSFETs can be found in the lit-
erature [98], while the description of the 20 nm gate length devices is listed in Appendix A.3. Due to
the fact that the EPFL-EKV compact model is actually a bulk MOSFET compact model, the junction
depth parameter XJ was used to dene the silicon body thickness of the FDSOI devices. The junction
depths of the bulk MOSFETs were obtained from the TCAD model. Table 7.1 includes the complete
compact model parameters for the 32 nm bulk MOSFET and the 32 nm SG FDSOI MOSFET, resulted
from extraction. These parameters are sufcient for describing the devices, which were simulated pre-
viously, using TCAD software. Compared to other classical compact models, e.g. BSIM4 [61] and
BSIMSOI4 [99], the amount of compact model parameters stays on a clear level.
(a) (b)
(c)
Figure 7.1 SPICE parameter extraction results of a 32 nm bulk MOSFET: (a) Transfer characteristic; (b) Output
characteristic; (c) Gate capacitance
The values noted in Tab. 7.1 can directly be transferred into an EKV model card to use the two devices
discussed above in SPICE simulations.
Figure 7.1 displays the extraction results for the 32 nm bulk NMOS and PMOS transistors. As can be
seen in Fig. 7.1(a), the transfer behavior of the two MOSFETs was reproduced in a good way. The
subthreshold slope and the threshold voltage agree for both devices and for the low-eld and high-eld
case very well to the results of the TCADsimulation. Figure 7.1(b) proves that also the output behavior of
the two MOSFETs was modeled in a good way, since the slopes, mainly dened by the threshold voltage,
the resistances, the DIBL, and the amount of current at V
gate
equal to V
drain
(dependent on VMAX)
were reached. Finally, the charging characteristic of the gate capacitances was perfectly reproduced
likewise (Fig. 7.1(c)). The differences of the leakage currents between the NMOS and PMOS transistors
(Fig. 7.1(a)) can easily be adjusted for the later circuit simulations by shifting the value of VTO of either
the NMOS device or the PMOS device.
Figure. 7.2 shows the extraction results for the 32 nm SG FDSOI devices. Although the EPFL-EKV
model was primary designed for compact modeling of bulk MOSFETs, the behavior of the 32 nm FDSOI
devices was reproduced in a really good way. Here again, the subthreshold slope and the threshold
(a) (b)
(c)
Figure 7.2 SPICE parameter extraction results of a 32 nm Single Gate FDSOI MOSFET: (a) Transfer charac-
teristic; (b) Output characteristic; (c) Gate capacitance
7.2 Compact Modeling of Multi-Gate MOSFETs 95
voltages were achieved, which is proven by the comparison of the transfer characteristics of the TCAD
and SPICE simulations in Fig. 7.2(a). Also the output behavior was caught for both gate voltage cases
and devices, displayed by Fig. 7.2(b). One cutback to be made if bulk MOSFET compact models are used
to model SG FDSOI devices concerns the charging behavior of the gate capacitance. It was not possible
to achieve the same good agreement between the C-V characteristics of the TCAD and the SPICE
simulations (Fig. 7.2(c)) for the SG FDSOI devices, like for the bulk devices (displayed in Fig. 7.1(c)).
The reason for this effect can be found in the lightly doped channels of the SGFDSOI devices, which lead
to a slower rise of the C-V characteristic than it would be in doped channels. In principle, it is possible to
achieve a good agreement between the TCAD and the SPICE results for the C-V characteristic, if NSUB
is set to the same values as used in the TCAD simulations. However, this would lead to a subthreshold
slope, extremely diverging from the TCAD results and to values below 40 mV/dec which is not realistic
at all. Therefore, the admission was made that the slopes of the C-V characteristics do not agree in a
perfect way, if the amount of C
gate
at high gate voltages and the threshold voltages of the SPICE model
correspond to the results of the TCAD simulations. As can be seen in Fig. 7.2(c), this criteria were
fullled by the EPFL-EKV model.
7.2 Compact Modeling of Multi-Gate MOSFETs
7.2.1 Double Gate Fully Depleted Silicon on Insulator MOSFET Compact Modeling
One problem that comes along with multi-gate MOSFET compact modeling is the asymmetrical be-
havior, resulting from non-uniform doping proles. In planar double gate MOSFETs non-uniformity of
doping proles results in a different overlaps of the source/drain extensions at the top-gate electrode and
the back-gate electrode. Due to the fact that the lateral diffusion near the surface leads to a wider lateral
redistribution than at the bottom of the silicon lm, the extension overlap under the top-gate of the planar
DG SOI MOSFET is stronger than at the back-gate electrode. This leads to a different threshold behav-
ior of the top-gate channel and back-gate channel. Because compact models for multi-gate devices were
still in development during this thesis [100] and not available in commercial SPICE software suits [60],
a method is presented in this work how to simulate multi-gate devices by using conventional bulk MOS-
FET compact models. Again, the EPFL-EKV model was used for demonstration. The method is based
on three TCAD simulation runs of a planar double gate FDSOI MOSFET. The transistor used for demon-
stration had a physical gate length of 32 nm and a gate oxide thickness of 1.2 nm. A silicon lm thickness
of 16 nm and a buried oxide thickness of 20 nm was used. A detailed description of the device can be
found in [101]. In the rst run, the back-gate electrode was grounded and only the top-gate electrode
and the drain electrode were ramped. Then, the transfer characteristics, output characteristics, and C-V
characteristic were simulated. Secondly, the top-gate electrode was grounded and only the back-gate and
the drain were ramped to calculate the characteristics mentioned above. Finally, both gate electrodes and
the drain electrode were ramped to calculate the double gate behavior of the device. Figure 7.3 displays
the resulting transfer characteristics at high drain voltages of the NMOS transistor (Fig. 7.3(a)). The
squares in Fig. 7.3(b) denote the case of ramping both gate electrodes. The solid line and the dashed line
in Fig. 7.3(b) denote the case of only ramping the top-gate and the back-gate, respectively. In a rst ap-
proach, the currents of the top-gate and the back-gate simulation runs were simply added, to gure out,
if it would be possible to simply plug two transistor models in parallel in the SPICE simulation to get
the double gate performance of the MOSFET. The result of the current addition is denoted by the circles
(a) (b)
Figure 7.3 Double gate FDSOI TCAD simulation method for SPICE modeling: (a) TCAD model with non-
uniformdoping proles; (b) Transfer characteristic of ramping single gate electrodes (solid line: top-gate; dashed
line: back-gate) and the sum of top-gate and back-gate simulation (circles)
in Fig. 7.3(b). It can be seen that the slope of the curve corresponds to the conventional mode of opera-
tion, but with a threshold voltage shift to higher values. This leads to the assumption that a simple shunt
circuit of two MOSFET models will not result in the required behavior.
After the characteristics of the three simulation setups were simulated, SPICE parameters were extracted
for the two cases of only ramping the top-gate and the back-gate electrode, respectively. Here, the same
extraction method discussed in Section 7.1 was used. That results in two different MOSFET models for
the top-gate and the back-gate, respectively. In a rst approach, the two extracted MOSFET models were
connected in a shunt circuit, shown in Fig. 7.4(a). Like already discussed before, a simple shunt circuit
of two MOSFET models would not result in the right threshold voltage. The difference in the threshold
voltages (Fig. 7.3(b)) results from the interaction of the electric elds of the respective gate electrodes
(a) (b)
Figure 7.4 Circuit scheme of the double gate FDSOI model including voltage controlled voltage source: (a) Cir-
cuit scheme; (b) Impact of the voltage controlled voltage source on transfer characteristics
on the respective opposite channel if both gates are ramped. With it, the electric eld of the top-gate
electrode has an inuence on the channel at the back-electrode and the other way round. However, this
effect is switched off, if only one gate electrode is ramped. In conventional bulk MOSFETs this effect is
well known as the so called body effect [8]. A possible solution to cope with that problem is to plug a
voltage controlled voltage source between the bulk connectors of the two EPFL-EKV MOSFET models
and ground. This voltage controlled voltage source is nally controlled by the gate voltage but with a
gain factor m. Figure 7.4(a) shows the nal scheme of the double gate model. The voltage controlled
voltage source leads to the required shift of the threshold voltage to smaller values. In case of the
demonstrator device, a gain factor m of 0.7 was found to result in the required behavior. Figure 7.4(b)
nally shows the impact of the voltage controlled voltage source with a gain factor of 0.7 on the transfer
characteristic at high drain voltages for NMOS and PMOS. In Fig. 7.4(b) the open squares and circles
denote the simulated characteristic resulting from the TCAD simulations, while the dashed lines denote
the corresponding SPICE simulation of the individual MOSFETs (top-gate or rather back-gate).
The lled squares and circle denote the TCAD simulation results for the intrinsic behavior of the dou-
ble gate MOSFET by ramping both gate electrodes simultaneously. The solid lines nally represent the
(a) (b)
(c)
Figure 7.5 SPICE parameter extraction results of a 32 nm double gate FD SOi MOSFET: (a) Transfer charac-
teristic; (b) Output characteristic; (c) Gate capacitance
results of the SPICE simulation, using the circuit scheme presented in Fig. 7.4(a) including two indepen-
dent MOSFET models for top-gate and back-gate and the voltage controlled voltage source with a gain
factor of 0.7. It can be seen in Fig. 7.4(b) that a very good agreement between the TCAD and the SPICE
simulation results of the DG FDSOI devices was achieved.
Figure 7.5 nally displays the complete characteristics of the extracted double gate compact model for
NMOS and PMOS in comparison to the corresponding TCAD results. Like already presented for the
conventional bulk MOSFET and the single gate FDSOI MOSFET, the leakage current, the subthreshold
slope, and the threshold voltage of the double gate compact model agree excellent to the TCAD results
(Fig. 7.5(a)). Furthermore, the output characteristics at high gate voltages and gate voltages just above
the gate overdrive also agree very good with the TCAD results (Fig. 7.5(b)). The same problem by
extracting the capacitances of the single gate FDSOI was found for the DG FDSOI. It was not possible to
model the capacitance load behavior in detailed using the model presented above (Fig. 7.5(c)). However,
the maximum value of the gate capacitance at V
gate
equal to V
drain
and the threshold voltage could be
achieved and the criteria dened in Section 7.1 was met.
7.2.2 Triple Gate FinFET Compact Modeling
Compact modeling of three dimensional triple gate FinFET devices using conventional bulk MOSFET
compact models works similar to the method presented for the planar double gate FDSOI MOSFET. For
demonstration, NMOS and PMOS TG FinFETs with a physical gate length of 32 nm were used. The
gate oxide thickness and buried oxide thickness was set to 1.2 nm and 20 nm, respectively, to set compa-
rable conditions to the bulk MOSFET, the SG FDSOI MOSFET, and the DG FDSOI MOSFET presented
before. Furthermore, a n height of 60 nm and a n width of 16 nm was used. The source/drain exten-
sions were implanted by arsenic and boron for NMOS and PMOS, respectively, while the channels were
kept undoped. After the process simulations, device simulations were performed to calculate the trans-
fer behavior, output behavior, and the C-V dependence using all the models presented in Chapter 2. To
reduce the simulation effort for the three dimensional device simulation, the saturation velocity correc-
tion of Bude [19] was used. The TCAD model of the NMOS device is shown in Fig. 7.6(a). Here again,
non-uniform doping proles lead to different gate overlaps and doping concentration at the respective
gate electrodes, shown in Fig. 7.6(a).
First of all, the three electrodes, front-gate, top-gate, and back-gate were separately ramped, like already
presented in case of the double gate. The transfer characteristics at high drain bias of the respective
gate electrodes are displayed in Fig. 7.6(b). A small difference between the front-channel and the back-
channel behavior was recognized. Further, the top-channel behavior results in a much smaller on-current,
due to the lower effective width. Comparable to the DG FDSOI device, discussed previously, the currents
of the three transfer characteristics were added (Fig. 7.6(b) circles) and compared to the intrinsic behavior
of the TG FinFET (Fig. 7.6(b) squares). Again, a difference between the threshold voltages of the
basic FinFET behavior and the sum of the three channels was recognized, due to the body effect. The
resulted transfer characteristics and transconductance characteristics of the three simulation runs (back-
gate, top-gate, and front-gate) were used to extract the SPICE parameters CGBO, CSBO, CDBO, U0,
THETA, KP, E0, and VTO using the same extraction method discussed in Section 7.1. Therefore, the
drain currents were normalized to A/m (I
on
/W
eff
). After the behavior of the separated channels were
extracted, the three transistor models achieved were connected via shunt circuit, like already presented
(a) (b)
Figure 7.6 TCAD simulation results of ramping single gate electrodes of the triple gate FinFET: (a) Doping
overlap at the different channels; (b) Transfer characteristic of the NMOS (line: front-gate; dashed line: back-
gate; dashed dotted line:top-gate; circles:sum of three; squares:intrinsic behavior)
in case of the DG FDSOI. The body effect was modeled again by a voltage controlled voltage source,
connected between the substrates of the three transistor models and the sources. The control of the
voltage controlled voltage source was referred to the gate voltage again. Figure 7.7 shows the circuit
scheme of the triple gate FinFET compact model. The extracted results for the TG FinFET using the
netlist shown in Fig. 7.7 are nally demonstrated in Fig. 7.8. The threshold voltage adjustment was
mainly done by adjusting the gain factor m of the voltage controlled voltage source shown in Fig. 7.4(a).
As can be seen in Fig. 7.8(a), the subthreshold slope and the threshold voltage were modeled in a really
good way. Also the DIBL and the drive currents of the TCAD model were reproduced by the compact
model (Fig. 7.8(b)). However, it was not possible to adjust the amount of gate capacitance at high gate
voltages by this method, like it was achieved for the SG FDSOI and the DG FDSOI (Fig. 7.8(c)).
Figure 7.7 Compact model scheme of the TG FinFET
(a) (b)
(c)
Figure 7.8 SPICE parameter extraction results of a 32 nmtriple gate FinFET: (a) Transfer characteristic; (b) Out-
put characteristic; (c) Gate capacitance
7.3 Circuit Simulations
Following the investigation of the electrical behavior of different MOSFET architectures (Chapter 6), the
four MOSFET architectures, conventional bulk MOSFET, SG FDSOI MOSFET, DG FDSOI MOSFET,
and TG FinFET were investigated under integrated circuit conditions. Four different circuit blocks were
used in the following: inverter, 7 stage ring oscillator, 4-bit ripple carry adder, and 6-transistor static
random access memory (6-T SRAM) cell.
7.3.1 Inverter and Ring Oscillator
The most basic CMOS circuit block is an inverter stage. An inverter consists of one NMOS and the
complementary PMOS. The source of the PMOS is connected to the supply voltage, while the source
of the NMOS is grounded. The gates of the NMOS transistor and PMOS transistor are short-circuited
and connected to the in signal V
in
. The drain regions of both transistors are connected to the output
node. Figure 7.9(a) shows the basic principle of an inverter stage. The fan-out capacitor C
fan
is used to
simulate the capacitive load of the next CMOS stages in an integrated circuit. In this work, respective
MOSFET architecture dependent fan-out capacitances, corresponding to approximately 3 inverter stages
7.3 Circuit Simulations 101
to be simultaneously driven, were assumed. Figure 7.9(b) displays the corresponding inverter netlist for
multi-gate devices. Hence, the voltage controlled voltage source of the PMOS is connected to V
DD
as it
is has to be connected between the bulk connector and the source.
The widths of the devices had to be changed to set the inverter threshold V
M
[102] to V
DD
/2. Therefore,
W
gate,NMOS
/L
gate,NMOS
of the planar single gate devices (bulk and SG FDSOI) was set to 1 to ensure
minimum layout area consumption. Then, W
gate,PMOS
/L
gate,PMOS
was set to 2 to ensure drive-current
equalization of both MOSFETs. In case of the double gate FDSOI MOSFET, W
gate,NMOS
/L
gate,NMOS
was
set to 1/2 and W
gate,PMOS
/L
gate,PMOS
was set to 1, to achieve comparable drive current conditions to the
single gate devices. The widths of the TGFinFET devices, however, were not changed, since the effective
width of a FinFET depends on the n height and width. But for all that, the enlargement of the effective
width by using three dimensional MOSFET device architectures, without changing the overall layout
consumption, is one of the big advantages of these kind of MOSFETs. Hence, this advantage should be
demonstrated by circuit simulations. For achieving drive current equalization in the TG FinFET based
inverter, the PMOS FinFETs contained two ngers, or ns in other words.
7.3.1.1 32 nm Based Circuit Blocks: Basic Operation Principles
Before starting the investigation of LSTP devices of the 32 nm ITRS technology node under circuit con-
ditions, 32 nm gate length CMOS devices (see Section 7.1) were used to demonstrate basic inverter
simulation principles. The static behavior of the inverter was simulated at rst. The input voltage V
in
,
connected to the gates, was ramped to the value of the supply voltage V
DD
. Figure 7.10(a) shows the volt-
age transfer characteristic (VTC) of the four respective inverter stages based on four different MOSFET
architectures. The inverter threshold V
M
[102] of all four inverter stages is situated near by the middle
(V
in
= V
out
). The undened region (UDR), which denes the voltage bandwidth the inverter stage needs
to interconnect both devices, NMOS and PMOS, of the different inverter stages is nearly equal. The
(a) (b)
Figure 7.9 Schematic draw of the inverter circuit: (a) Single gate devices; (b) Double gate devices
UDR itself is dened in this work by the input voltage region between two points of the VTC when the
derivative of V
out
(the gain of the inverter) becomes -1. Obviously, using different MOSFET architec-
tures makes no big difference with respect to the static inverter behavior (Fig. 7.10(a)). The results of the
calculated inverter thresholds V
M
and UDRs are listed in Tab. 7.2.
The dynamic behavior of the inverter was simulated using a pulsed voltage source serving as input signal
V
in
. The rise and fall time of the pulse signal was set to 1 ps and the hold time was set to 2 ns. Fig-
ure 7.10(b) shows the dynamic switching behavior of the four different inverter stages. Now, the impact
of the fan-out capacitor turns up. Due to the overall lower drive current of the bulk MOSFET (Fig. 7.10(b)
squares), the response time of the output voltage V
out
of the bulk based inverter is the longest, compared
to the fully depleted SOI devices. This response time can be expressed by the propagation delay. The
propagation delay t
prop
is dened by the average of the rise t
delay,rise
and the fall delay t
delay,fall
. The rise
and fall delay themselves are dened by the time distances at V
DD
/2 between the input signal V
in
and
V
out
[102]. The propagation delay is expressed by:
t
prop
=
t
delay,rise
+t
delay,fall
2
. (7.1)
The bulk MOSFET based inverter stage responses with a delay of 11.5 ps on the input signal. The two
multi-gate devices have comparable response time ranges of 5 ps, more than a factor of 0.5 lower than
the bulk MOSFET based inverter, as shown in Fig. 7.1. The SG FDSOI MOSFET (Fig. 7.10(b) circles)
showed a propagation delay of 6.18 ps. Although the physical width of the DG FDSOI MOSFET was
reduced to the half of the SG FDSOI MOSFET, the drive currents of the DG MOSFETs are still higher
and therefore, speed up the circuit. Looking at Fig. 7.10(b) (dashed line) the big advantage of the TG
FinFET MOSFET gets clear. Due to the larger effective width (136 nm), the FinFET is able to charge
and discharge the fan-out capacitor faster (t
prop
= 5.0 ps) than the planar devices, but for the same layout
area consumption.
Due to higher drive currents of the FinFET based inverter stage, compared to planar devices, the average
power consumption per cycle (Fig. 7.10(b)) of the FinFET based inverter is nearly four times higher
(a) (b)
Figure 7.10 Static and dynamic behavior of the simulated inverter stage using four different CMOS device
architectures with a physical gate length of 32 nm: (a) Static behavior; (b) Dynamic behavior
(P
av
= 16 W), compared to the planar devices (approximately 4 W). The SG FDSOI MOSFET based
inverter has the lowest power consumption of 3.34 W, but comparable to the bulk MOSFET and DG
FDSOI MOSFET. The average power consumption itself is dened by averaging the product of the
supply voltage V
DD
and the integral of the current i
DD
seen by the power source over the simulation
time t [102]:
P
av
=
V
DD
t
_
t
0
i
DD
(t)dt . (7.2)
As it was already guessed in Chapter 6 the TG FinFET also showed the best performance if it is used in
an inverter stage. However, these simulations were done without taking the effects of mechanical stress
and especially contact resistances into account. All results of the simulations are listed in Tab. 7.2.
7.3.1.2 20 nm LSTP Based Circuit Blocks: An Inverter Performance Estimation
The low standby power devices discussed in Section 6.4 and A.3 (Tab. A.6 and A.7) were now used in the
SPICE simulations. The behavior of the four device architectures with a physical gate length of 20 nm
was compact modeled the same way as it was done in case of the 32 nm devices (Section 7.1). Contrary
to the the simulation presented previously, mechanical stress was included and contact resistances were
taken into account.
The contact resistances were recalculated depending on the widths used in the inverter setups
(R
co
1 m/W). The same dependencies of width and gate length discussed in Subsection 7.3.1 were
assumed. In case of the FinFET inverter, the contact pad area sizes of the SG FDSOI were used. At
rst, the static behavior was simulated again. Figure 7.11(a) shows the VTC of the four respective in-
verter stages. Here again, no signicant difference between the four different architecture based inverter
stages was observed. A closer look to the dynamic performance of the inverters, however, uncovers the
impact of the contact resistances on the switching speed (Fig. 7.11(b)). The bulk MOSFET (Fig. 7.11(b)
squares) and SG FDSOI MOSFET (Fig. 7.11(b) circles) based inverters showed the longest switching
delay observed during the investigation. This was already shown by the CV/I characteristic in Fig. 6.32
of Section 6.4. Furthermore, the propagation delay was calculated to be even higher than in case of
the 32 nm gate length devices presented before, although the dimensions of the MOSFET were lowered.
The TG FinFET (Fig. 7.11(b) dashed line) has a delay of 8.49 ps, which is comparable to the SG FDSOI.
Again, this compares very well to the CV/I behavior observed in Fig. 6.32 of Section 6.4. The DG FD-
SOI based inverter (Fig. 7.11(b) dashed-dot line) shows in comparison to the bulk MOSFET, SG FDSOI
MOSFET, and TG FinFET the fastest t
prop
of 6.7 ps. However, also t
prop
of the DG FDSOI MOSFET is
1.7 ps higher than it was calculated in case of the 32 nm devices. The reason for a larger delay if LSTP
of 20 nm gate length were used in inverter stages presented here, is the impact of Schottky contact resis-
tances, which were neglected in the 32 nm gate length device and SPICE simulations. The average power
consumption of the switch cycle of the three inverters based on planar devices are comparable, displayed
in Fig. 7.11(b). Only P
av
of the bulk MOSFET based inverter was calculated to be slightly higher, com-
pared to the planar SOI devices (Tab. 7.2). The highest average power consumption was found for the TG
FinFET based inverter stage, while the SG FDSOI MOSFET based inverter stage showed the smallest
P
av
.
(a) (b)
Figure 7.11 Static and dynamic behavior of the simulated inverter stage using four different CMOS device
architectures with a physical gate length of 20 nm including mechanical stress and contact resistances: (a) Static
behavior; (b) Dynamic behavior
7.3.1.3 20 nm LSTP Based Circuit Blocks: A Ring Oscillator Performance Estimation
Based on the inverter simulations presented before, the performance of the four device architectures was
investigated in a ring oscillator of seven inverter stages. Figure 7.12 shows a schematic draw of the ring
oscillator circuit. In this case, seven inverter stages were connected in series. Two signals were tapped
at the input and output of the rst inverter stage. Finally, the propagation delay of a single inverter
stage was computed. Therefore, the propagation delay of the whole inverter chain was calculated the
same way already presented for the single pulsed inverter, and nally divided by the number of inverter
stages [102]. The fan-out capacitor was removed, while interconnect capacitances were neglected.
Figure 7.13 shows the results of the ring oscillator simulations. The rst signal ow was calculated for
the bulk MOSFET based ring oscillator. As can be seen, the signal speed is slow, compared to the SOI
MOSFET based ring oscillators. The propagation delay of one inverter stage was calculated to be 0.75 ps.
The second graph in Fig. 7.13 shows the signal ow of the SG FDSOI MOSFET based ring oscillator.
Compared to the bulk MOSFET based ring oscillator, the SG FDSOI based circuit is twice as fast. This
Table 7.2 Static and dynamic behavior of the inverter stage using four different
MOSFET architectures and two different physical gate lengths
Device V
M
(V) UDR (V) t
prop
(ps) P
av
(W/cycle)
32 nm Bulk 0.557 0.107 11.5 3.6
32 nm SG FDSOI 0.550 0.139 6.18 3.34
32 nm DG FDSOI 0.558 0.129 5.17 3.79
32 nm TG FinFET 0.541 0.138 5.00 16.0
20 nm Bulk 0.447 0.111 13.6 1.37
20 nm SG FDSOI 0.450 0.091 9.23 0.92
20 nm DG FDSOI 0.456 0.078 6.7 0.94
20 nm TG FinFET 0.459 0.099 8.49 4.7
Figure 7.12 Schematic draw of the seven stage ring oscillator used in this work
is also conrmed by the calculated propagation delay of one inverter stage: t
prop
= 0.43 ps. The TG
FinFET based ring oscillator resulted in a propagation delay t
prop
of 0.36 ps. The ring oscillator circuit
based on DG FDSOI MOSFET was found to have in the fastest oscillation signal (t
prop
= 0.28 ps), which
corresponds to the results of the single inverter stage. However, comparing the propagation delay results
of the SPICE simulations, so far, to the CV/I results of the corresponding TCAD models (Fig. 6.32), a
difference of the TG FinFET behavior was recognized. The LSTP TG FinFET was found to result in the
lowest CV/I value and, therefore, in the lowest switching delay, presented in Fig. 6.32. This behavior
was not reproduced by the SPICE simulations, as the LSTP DG FDSOI based circuits resulted in faster
switching speeds, compared to the LSTP TG FinFET based circuits. This can be explained by slightly
higher gate capacitances in the compact model of the TG FinFET. It was shown in Fig. 7.8(c) that it was
not possible to reproduced the gate capacitance behavior of the TCAD model by the TG FinFET compact
model. The maximum capacitance at V
gate
equal to V
DD
was slightly overestimated by the TG FinFET
compact model. The propagation delay t
prop
, switching frequency and the average power consumption of
the investigated ring oscillators are listed in Tab. 7.3. The best overall performance was calculated for the
DG FDSOI based ring oscillator, with a propagation delay of 0.28 ps, 42.8 GHz switching frequency, and
6.03 W average power consumption. However, the TG FinFET maybe would reach the same switching
performance like the DG FDSOI, if it would be possible to reduce the gate capacitance in the SPICE
Figure 7.13 Input and output signal of the rst inverter stage i1 of the seven stage ring oscillator
model. The use of other compact models would maybe more benecial for these kind of simulations.
But, even if the same switching speed of the DG FDSOI was assumed for the TG FinFET, the DG FDSOI
based inverter and ring oscillator still have the best overall performance, because the lower average power
consumption. Furthermore, if the switching speed would increase, also the average power consumption
of the TG FinFET would increase.
Table 7.3 Results of the ring oscillator simulation using four different
CMOS device architectures
Device t
prop
(ps) Frequency (GHz) P
av
(W)
20 nm Bulk 0.75 13.5 4.44
20 nm SG FDSOI 0.43 23.6 4.24
20 nm DG FDSOI 0.28 42.8 6.03
20 nm TG FinFET 0.36 28.4 24.4
7.3.2 4-Bit Ripple Carry Adder
Based on the simulations of a single inverter stage and the ring oscillator, the 20 nm LSTP devices are
now investigated in a more complex logic circuit. Here, a 4-bit ripple carry adder was chosen. This
circuit is based on four full adder stages with a pass through carry signal. One full adder stage itself
consists of 28 MOSFETs. Basically, the sum output signal S is calculated by two XOR operations ()
of the two input signals A and B and the carry ag C
in
. The binary calculation of the sum signal S is
given by [102]:
S = (AB) C
in
= A

B

C
in
+

AB

C
in
+

A

BC
in
+ABC
in
. (7.3)
The carry-out signal C
out
, which is needed to calculate the overhead of the addition is calculated as an
OR of three AND operations of the input signals A, B, and the carry ag C
in
[102]
C
out
= AB +BC
in
+AC
in
. (7.4)
Figure 7.14 shows the circuit of one full adder (FA) stage, used in this work [102]. Here, the same
widths of NMOS and PMOS that were already used for the inverter and ring oscillator simulations were
assumed. The impact of interconnects on the circuit performance was neglected again. The scheme of
the nal 4-bit ripple carry adder circuit is shown in Fig. 7.15. Basically, the aim of the simulations again
is to investigate the speed of the circuit if different MOSFET architectures are used. Because the ripple
carry adder concept is critical, due to the pass through carry signal, concerning switching speed it is well
suited for investigating the advantages of different MOSFET architectures in more complex circuits. The
whole time the adder needs to nish the addition of the two 4-bit signals A and B is expressed by [102]
t
adder
= 3t
carry
+t
sum
. (7.5)
In Eq. (7.5), t
carry
is the time the carry-out signal of one stage needs to response on the carry-in signal.
Since the carry signal is passed through three additional full adder stages, it is multiplied by 3 [102]. t
sum
is the delay of the sum signal S to react on a change of the carry-ag signal.
Figure 7.14 Circuit diagram of one full adder stage used in this work
Figure 7.16 shows the results achieved by the simulations of the 4-bit ripple carry adder using four
different LSTP CMOS device architectures. The carry ag signal was simulated by a pulsed voltage
source with a rise and fall time of 1.0 ps and a frequency of 8 GHz. To force all MOSFETs to switch,
the 4-bit input signals A and B were set on a constant level of 1111. First of all, the pass through time
of the carry signal was investigated for the different CMOS device architectures. Figure 7.16(a) shows
the response of the carry out signal C
out
on the carry ag C
in
. If conventional bulk MOSFETs are used,
the carry signal needs 109.6 ps to pass the complete 4-bit ripple carry adder circuit. The use of SG
FDSOI MOSFETs speeds up the circuit by 33.4 % and results in a response time of 65.8 ps. DG FDSOI
MOSFETs lead again to a lower switching delay of 40.5 ps. The best performance was achieved by using
TG FinFET devices. Here, the carry signal only needs 36 ps to be passed through the whole circuit block.
Figure 7.15 Schematic of the 4-bit ripple carry adder circuit
(a) (b)
Figure 7.16 4-bit ripple carry adder simulation results using four different CMOS device architectures:
(a) Carry-ag signal results; (b) S
3
signal results
The whole time the adder needs to nish the addition is displayed in Fig. 7.16(b) and given by the sum
signal S
3
, which is the last sum signal in the time diagram presented in Fig. 7.16(b). Due to the very long
pass through time of the carry signal, if bulk MOSFET were used to simulate the 4-bit ripple carry adder
circuit, the adder needs 127.2 ps to nish the addition. If SG FDSOI MOSFETs are used, the addition
time is reduced to 75.8 ps. The multi-gate devices, DG FDSOI and TG FinFET, only need 47.0 ps and
41.4 ps, respectively, to add the two 4-bit signals A and B. The simulation results of all CMOS device
architectures are listed in Tab. 7.4.
Table 7.4 4-bit ripple carry adder simulation results
Device t
carry
(ps) t
sum
(ps) 3t
carry
(ps) t
adder
(ps)
20 nm Bulk 36.4 17.6 109.6 127.2
20 nm SG FDSOI 21.9 10.0 65.8 75.8
20 nm DG FDSOI 13.5 6.5 40.5 47.0
20 nm TG FinFET 12.0 5.4 36.0 41.4
7.3.3 6 Transistor Static Random Access Memory Cell
The last circuit block to be discussed in this work is a classical 6-transistor static random access mem-
ory (6-T SRAM) cell. This memory cell is often used in the literature to gauge the quality of either new
CMOS device architectures or simply scaled MOSFET devices for future technology nodes. Further-
more, the 6-T SRAM cell is well qualied for the investigation of how uctuations during processing
affect the CMOS circuit performance. Figure 7.17 shows the schematic draw of the standard 6-T SRAM
cell. The inner ip-op (M1, M2, M3, M4) is connected by the nodes Q and

Q with the access transis-
tors M5 and M6. The access transistors nally are connected to the word-line WL, which controls the
READ and WRITE operations of the cell, and to the bit-lines BL and BL for the input and output data.
The load capacitors C
load,BL
and C
load,BL
, connected to BL and BL, serve for simulating interconnect
capacitances and capacitances of additional SRAM cells connected at the bit-lines, during the read oper-
Figure 7.17 Schematic of a 6-T SRAM cell circuit
ation [102]. The capacitance of C
load
was set to 6 fF [102] in this work. Three states are distinguished:
HOLD, READ, WRITE. The cell is rst set in HOLD mode. The word-line WL is, therefore, set to zero.
In this mode, no data is written to or read out from the memory cell. Figure 7.18 shows the static behav-
ior of the inner ip-op if WL is at zero. Here, the node Q was set on a xed potential, in this case 0.9 V.
Then, the voltage at node

Q was ramped and the voltage at Q was observed and the other way round.
Again, the four different LSTP device architectures were used to investigate their behavior in memory
cells. The layout of the SRAM cell was taken from the literature [10] for 32 nm gate length devices, and
scaled down by the gate length difference factor of 0.6. Thus, the widths of the PMOS transistors M2
and M4 and of the NMOS access transistors M5 and M6 was amounted to 50 nm, while the widths of the
NMOS transistors M1 and M3 were set to 80 nm. In case of the DG FDSOI MOSFETs, the widths were
set to half of the widths of planar single gate MOSFETs again. For the TG FinFET, one n was assumed
for M2, M4, M5, and M6, while two ns were used for M1 and M3. As can be seen in Fig. 7.18, no sig-
nicant difference of the inner ip-op behavior was found if four different CMOS device architectures
were used, accept a small difference in the inverter threshold V
M
, which differs slightly from V
Q
= V
Q
.
Figure 7.18 6-T SRAM cell HOLD operation mode
Secondly, the SRAM cell was set into the READ operation mode. Therefore, the word-line and both
bit-lines were biased by a constant voltage of 0.9 V to observe the static behavior of ip-op transition, if
the voltage at node

Q is ramped and the voltage at Q is observed and the other way round. Figure 7.19(a)
shows the classical buttery characteristic of the SRAM cell in READ operation mode. In Fig. 7.19(a),
the bulk MOSFET based SRAM cell is given by the solid line, the SG FDSOI based SRAM cell by
the dashed line, the DG FDSOI based SRAM cell by the dashed-point line, and the TG FinFET based
SRAM cell by the dashed-point-point line. It clearly can be seen that the bulk MOSFET based SRAM
cell shows the most unstable behavior of the four SRAM cells investigated. This behavior is expressed
by the static noise margin (SNM) of the SRAM cell. The SNM itself is dened by the side length of the
largest possible square to t in between the buttery curve of the inner ip-op. The greater the value
of the SNM, the more stable the switching behavior of the SRAM cell is against voltage uctuations
caused by noise. Consequently, the operation of the memory cell becomes more accurate for large values
of the SNM. The SNM can be calculated by searching at rst the point at one curve of the buttery
characteristic, where the derivation becomes -1. After that, a line, parallel to the bisecting line of the
angle of the coordinate system is drawn through the calculated point. Finally, the point of intersection
between the drawn up line and the second curve of the buttery characteristic is calculated. Thus, two
respective x-axis and y-axis points are calculated to dene the SNM. In case of the bulk MOSFET based
SRAM cell a SNM of 144 mV was calculated for the READ SNM. Compared to the SNMs calculated
from the simulations of the SOI based SRAM cells the bulk SNM was the smallest. This calculated low
SNM of the bulk MOSFET based SRAM cell further corresponds very well to measured results of 45 nm
bulk MOSFET based SRAM cells, presented in the literature [10]. The highest value and, therefore, the
most stable SRAM cell, was calculated for the TG FinFET based SRAM cell (SNM =228 mV). However,
as well the SG FDSOI based SRAM cell, as the DG FDSOI based SRAM showed a comparable behavior
with SNMs of 210 mV and 221 mV, respectively.
Thirdly, the dynamic READ operation of the SRAM cells based on four different MOSFET architec-
tures was investigated. Here, WL was assumed to be a pulsed signal with a rise and fall time of 1 ps.
Furthermore, the bit-lines were both set on the supply voltage of 0.9 V. The state of node Q was set on
0.0 V, which represents a 0 to be stored in the memory cell. Respectively,

Q was set to 0.9 V. If WL
(a) (b)
Figure 7.19 6-T SRAM cell READ operation mode: (a) Static behavior; (b) Dynamic behavior
(a) (b)
Figure 7.20 6-T SRAM cell WRITE operation mode: (a) Static behavior; (b) Dynamic behavior
rises to 0.9 V, the voltage of the bit-line BL drops to zero. Figure 7.19 shows the results of the dynamic
READ operation. As can be seen, the bulk MOSFET based SRAM cell (solid line) shows the longest
delay until the bit was read (t
read
= 372 ps). In this work, the READ operation was assumed to be n-
ished at V
DD
/2, here 0.45 V. The SG FDSOI (dashed line) and DG FDSOI (dashed-point line) nearly
showed the same speed (t
read
170 ps). The TG FinFET exceeded the performance of the other MOS-
FET architectures investigated, again, due to its larger effective width. Using this device architecture, the
READ delay could be reduced to a value of 52.5 ps. Due to the large effective width of the TG FinFETs,
the average power consumption during the read cycle is more than three times higher (P
av,read
=65.1 nW)
than, e.g., the average power consumption of the SG FDSOI based SRAM cell (P
av,read
=17.0 nW) or the
DG FDSOI based SRAM cell (P
av,read
=18.5 nW). The bulk MOSFET based SRAM cell showed, on the
other hand, the lowest average power consumption of 3.23 nW, which is nearly a sixth part of the SOI
MOSFETs and a twentieth part of the TG FinFET. All values are listed again in Tab. 7.5.
Fourthly, the four SRAM cells were investigated in relation to static WRITE noise margin. The word-
line was set again on a xed value of 0.9 V. Differently to the READ operation mode, BL was set to zero
and BL was set to 0.9 V. Complementary, Q was set to zero and

Q was set to 0.9 V. Then, the voltage at
node Q was ramped to 0.9 V and the voltage at

Q was observed and the other way round. Figure 7.20(a)
shows the behavior of the inner ip-op in WRITE mode. Here again, the bulk based MOSFET (solid
line) showed the smallest write static noise margin (WSNM=364.0 mV), but not deviating that strong
from the other three devices like in READ mode. The only SRAM cell with a slightly higher WSNM is
the DG FDSOI based SRAM cell (dashed-point line) with a WSNM of 412 mV. The SG FDSOI based
SRAM cell (dashed line) and the TG FinFET based SRAM cell (dashed-point-point line) showed a
comparable behavior to the bulk based SRAM cell with a slightly higher WSNM.
Finally, the dynamic WRITE operation was applied to the four SRAM cells investigated. The same
setup for the bit-lines like for the static WRITE mode was used. The state of the nodes Q and

Q was
switched to 0.9 V and 0.0 V, respectively. The word-line was pulsed again with a rise and fall time of
1 ps. If the world-line reaches the high state, the zero state of the BL is written to Q and the high state
of BL is written to

Q. Figure 7.20(b) shows the dynamic write behavior of the four different SRAM
cells. It has to be noted that the write operation is nished, if the 0 to1 and the 1 to 0 curves, plotted
in Fig. 7.20, reached a steady state. The solid line denotes the behavior of the bulk MOSFET based
SRAM cell for both cases of writing a 0 and a 1. The bulk MOSFET based SRAM cell needs the longest
time t
write
of 6.85 ps for completing the write operation, compared to the SOI MOSFET based SRAM
cells. Differently to the READ operation, the DG FDSOI based SRAM cell was outperformed by the SG
FDSOI based SRAM cell in WRITE operation by 1.27 ps. The DG FDSOI based SRAM cell nished the
WRITE operation after 5.75 ps, while the SG FDSOI based SRAM cell only needed 4.48 ps to nish the
WRITE operation. As already observed in case of the READ operation, the TG FinFET based SRAM
cell resulted in the fastest WRITE operation t
write
of 2.6 ps. Furthermore, the average power consumption
during the WRITE cycle of the TG FinFET based SRAM cell was calculated to be nearly equal to P
av
of
the DG FDSOI based SRAM cell. The SG FDSOI based SRAM cell, however, only generated a P
av
of
2.4 W/cycle (Tab. 7.5).
Table 7.5 Performance of the 6-T SRAM cell using four different CMOS architecuters
Device SNM
read
t
read
P
av,read
SNM
write
t
write
P
av,write
(mV) (ps) (nW/cycle) (mV) (ps) (W/cycle)
20 nm Bulk 144 231.9 4.75 363.6 6.85 2.59
20 nm SG FDSOI 210.0 188.2 17.0 375.6 4.48 2.4
20 nm DG FDSOI 221.0 162.5 18.5 413.0 5.75 4.3
20 nm TG FinFET 228.0 52.5 65.1 387.8 2.6 4.7
Summing up, it could be demonstrated that multi-gate devices, DG FDSOI and TG FinFET, clearly
exceeded the performances of planar single gate devices, bulk MOSFET and SGFDSOI, under integrated
circuit conditions. DG FDSOI MOSFETs were found to be benecial in simple inverter stages and ring
oscillator circuits, based on inverter chains, as these devices have the best relation between switching
speed and power consumption. TG FinFETs are benecial to be used in more complex logic circuit,
like demonstrated by the example of the 4-bit ripple carry adder. However, due to the higher effective
width, the average power consumption of TG FinFET based logic circuit blocks was high, compared to
planar device based logic circuit blocks. In memory cells, FinFETs overall exceeded the performance
of planar devices. TG FinFET based SRAM cells resulted in the most stable static behavior and fastest
switching behavior. However, the average power consumption was high again, due to the larger effective
width. Another advantage of using multi-gate devices in integrated circuit would be the reduction of
the static power dissipation. As the leakage currents of the single bulk MOSFETs were calculated to
be 150 times higher, compared to the DG FDSOI devices, the static power dissipation could efciently
be reduced by using multi-gate devices in integrated circuits. Furthermore, the layout area consumption
can be efciently be reduced, if multi-gate MOSFETs were used in integrated circuits. Due to double
gate architecture, the planar layout area can be set to half the layout area of planar single gate devices, at
better performance, if DG FDSOI MOSFETs were used in integrated circuits.
Chapter 8
Process Variations
Evaluating different CMOS device architectures on their suitability for future CMOS technology nodes
implies not only the investigation of the single device performance and circuit performance, but also the
examination of the stability of the different CMOS device architectures against technology process varia-
tions. Technology process variations result from small uctuations of process parameters during CMOS
processing, e.g. temperature uctuations during annealing or oxidation, lm thickness uctuations of
the photo resist, or defocus variations between two exposure steps. These small uctuation actually have
been present since the beginning of the CMOS processing era. Due to the ever shrinking CMOS de-
vice dimensions and supply voltage, the impact of the uctuations on the device performance and, in
the end, chip performance is continuously increasing. Figure 8.1 already denotes that the reduction of
variability is besides the development of new CMOS device architectures one of the most important
problems the device engineering community has to deal with in the future [103], as the production yield
is inuenced by process variations all-out. Process variations can be classied into two major classes:
Die-to-Die (DtD) variations and Within-Die (WiD) variations. Die-to-Die variations are caused by, e.g.,
lithography, oxidation, deposition, and etching process variations. Within-Die variations are more criti-
cal to regard, than Die-to-Die variations, because they directly inuence single devices in a circuit block
and, in the worst case, cause non-reliability performance of the die. Random dopants and line width
roughness can be named to be the most discussed WiD process variations.
This chapter deals with the investigation of how lithography process variations, silicon lm thickness
variations, annealing temperature uctuations, and doping variations inuence the device performance
of the four different CMOS device architectures discussed in the previous Chapters 6 and 7. Further-
more, the impact of process variations on the circuit performance of the four circuit blocks discussed in
Chapter 7 is examined by using different CMOS device architectures. Therefore, lithography simula-
tions were done by varying two critical process parameters. Subsequent to the lithography simulations,
the resulted critical dimension (CD) values of the physical gate length were used in TCAD process and
device simulations, to observe the impact of lithography variations on CMOS device performances. Sec-
ondly, compact modeling of the threshold voltage dependency on gate length and body thickness of the
silicon lm, in case of silicon on insulator devices, was done, to perform SPICE simulations includ-
ing process variations. Then, the impact of ion dose uctuations and annealing temperature uctuations
on source/drain Schottky contact resistances was prospected by TCAD simulations. The dependency of
113
114 8 Process Variations
Figure 8.1 Challegenes for future CMOS devices: variability is one of the most
important issue to be solved [103]
contact resistances on ion dose uctuations and annealing temperature uctuations was compact mod-
eled. Finally, circuit simulations, including process variations, were undertaken, to exhibit the pros and
cons of different MOSFET architectures.
8.1 Lithography Induced Gate Length Variations
Lithography is one of the most critical process steps for causing variability of the nal MOSFET behav-
ior. Due to ever shrinking device dimensions, small uctuations of, e.g., the exposure dose and especially
the defocus are in particular responsible for uctuations of the physical gate length. However, these gate
length uctuations can only be observed by comparing the performance of different dies, because uctu-
ations of lithography parameters affect equally on the whole circuit layout of a die. Line width roughness
(LWR), on the other hand, which can be understand as a waviness of the poly-gate line, e.g., resulting
from the molecular structure of photo resist [104], can inuence every single device on a die and even can
cause failures of complete circuit blocks. Different to lithography process parameter uctuations, line
width roughness cannot be controlled or even eliminated by using stricter lithography process conditions.
8.1.1 Lithography Process Setup
A 193 nm water immersion lithography process was examined for the lithography process. Thus, a
numerical aperture NA of 1.2 was assumed. An attenuated phase shifting mask (AttPSM) with a MoSi
absorber (n: 2.442, k: -0.586) on a glass substrate (Fig. 8.2) was used. The absorber dimensions of
62 nm (wafer scale) width and 68 nm thickness were obtained by a coarse pre-optimization. Due to the
sub-wavelength dimension of 45 nm aspired for the nal CD, electromagnetic eld (EMF) effects were
taken into account, and mask near eld computations were performed using the Waveguide Method [105]
of Dr.LiTHO [106], without Hopkins approximation. A dipole quasar setup with an inner radius (r
i
) of
0.8 and an outer radius (r
o
) of 0.96 (normalized to the NA) was used as illumination source for the
lithography simulation (Fig. 8.2). The opening angle of the poles is set to 40
, while y-polarized light

8.1 Lithography Induced Gate Length Variations 115
Figure 8.2 Lithography simulation process setup
with an intensity of preferred state (IPS) of 1 was considered. Furthermore, no full resist development
model was used. Instead, a threshold model was employed to indirectly render the exposure dose [107].
The lithography process window analysis (allowing up to 10 % CD variations) yielded a depth of focus
of 52 nm and a threshold latitude of 8.5 %. In order to study the impact of lithography variations not
only under feasible conditions, the variation range was dilated to 40 nm around the best focus and to
a threshold range of 0.25 to 0.4 (Fig. 8.2). After the CD was calculated, a xed etch bias of 13 nm was
assumed to achieve the required physical gate length of 32 nm [107].
8.1.2 Coupled Lithography and Device Simulation
The coupled lithography and device simulation (CoLiDe) principle presented in this work is based on
a simulation framework which can be used to include and combine different simulation tools [107].
The framework is based on the scripting language Python and makes use of the Python network toolkit
Twisted. By employing this software architecture, independent simulations can be performed concur-
rently, e.g., on different nodes of a high performance computing cluster. This leads to a signicant
reduction of the overall computation time. A detailed discussion can be found elsewhere [107]. In this
work, the framework was used to couple the rigorous lithography simulation tool Dr.LiTHO [106] to the
Sentaurus TCAD suite of Synopsys [31] for a full TCAD-based process variation simulation study.
Figure 8.3 Simulation ow chart for coupled lithography and device simulation (CoLiDe) [107]
To examine how lithography process parameters inuence the nal critical dimension (CD) of the poly-
gate line, the probability density function (PDF) of the defocus was assumed to be Gaussian distributed
(Fig. 8.4(a)), while an uniform PDF was chosen for the threshold. First of all, the resulted critical
dimension at a xed threshold value of 0.32 was observed after a simulation run using nearly 1000
variations of the defocus. An asymmetric probability density function (PDF) was found for the CD,
shown in Fig. 8.4(b). The best tting function was found to be a generalized extreme values (GEV)
probability density function. The GEV distribution function results from the nature of the lithography
process. This is demonstrated by Fig. 8.4(c). Figure 8.4(c) shows the common Bossung plot of the CD
distribution over projector defocus range of -40 nm to 40 nm at a xed threshold of 0.32. As can be seen
in Fig. 8.4(c) most of the CD values are distributed around a maximum value of 33.8 nm at the best point
of focus and tend to smaller values if the projector defocus shifts from the best point of focus. This is the
reason for the asymmetrical PDF of the resulting CD shown in Fig. 8.4(b).
The CoLiDe method was applied to three device architectures with a nominal physical gate length of
32 nm: planar bulk MOSFET, planar SG FDSOI MOSFET, and planar DG FDSOI MOSFET. The spec-
ications of these devices were already discussed in Chapter 7 and in [98, 101]. Nearly 8750 coupled
lithography, process, and device simulations were performed on a high performance computing (HPC)
cluster using 40 processor cores. The overall simulation time was 1.5 days for one single device. Due to
the fact that NMOS and PMOS transistors were simulated, the whole experiment lasted 9 days. It has to
be mentioned that only two dimensional simulations were performed.
First of all, a closer look to the PDF of the threshold voltage of the different device architectures was
done. Normally, a Gaussian PDF would be expected for the threshold voltage, like discussed in several
works [108, 109, 110]. However, thinking about an asymmetrical PDF of the CD might also result in
a different threshold voltage PDF. Figure 8.5(a) shows the PDF of the threshold voltage resulted from
the NMOS bulk transistor simulation run. As expected, the threshold voltage shows some kind of a
Gaussian probability distribution. This was conrmed by a Gaussian PDF t function resulting in the
best correlation with numerical results. Things change, if the threshold voltage distribution of NMOS SG
FDSOI MOSFETs and NMOS DG FDSOI MOSFETs, are observed (Fig. 8.5(b) and 8.5(c)). Here, the
threshold voltage shows a very asymmetrical behavior, like already observed in case of the CD. A GEV
PDF t function resulted for both devices, SG FDSOI and DG FDSOI MOSFETs, in the best correlation.
It seems that the PDF of the CD is directly mirrored by the threshold voltage of the SOI devices. The
reason for this effect is the lightly channel doping of the SOI devices. Due to the lightly doped channel,
(a) (b)
(c)
Figure 8.4 Impact of lithography parameter uctuations on the critical dimension: (a) Gaussian PDF of the
projector defocus; (b) Generalized extreme values PDF of the CD; (c) Bossung plot at 0.32 threshold
the threshold voltage is not inuenced by potential uctuations of the channel doping and is, therefore,
only dependent on short channel effects due to the changing physical gate length. The threshold voltage
of the bulk MOSFET, on the other hand, is inuenced by the pocket implants, changing the channel
doping concentration at decreasing or increasing gate lengths. Thus, a self adjusting of the threshold
voltage is performed by the pocket implants of the bulk MOSFET at decreasing gate lengths, resulting in
a Gaussian PDF. The results rose the question, if standard 3 specications [9] of the threshold voltage
and the CD are still valid, due to the asymmetrical behavior of the CD under defocus variations and the
threshold voltage of SOI MOSFETs.
8.1.3 Compact Modeling of Threshold Voltage Dependence on Gate Length and Body
Thickness Variability
In the previous section, the coupled lithography, process, and device simulation results were presented,
by using a fully TCAD setup for process and device simulations. Consequently, only two dimensional
simulations were performed to reduce computational effort. Even though, the overall simulation time of
1.5 days on 40 cores of a HPC cluster is still long for a relatively small amount of 8750 results. If three
(a) (b)
(c)
Figure 8.5 PDF of the threshold voltages under lithography variations: (a) Bulk MOSFET: normal PDF;
(b) SG FDSOI: GEV PDF; (c) DG FDSOI: GEV PDF
dimensional structures as TG FinFETs are investigated by this method, the computation time would be
extended to approximately 30 days for a single device. Thus, it would be benecial to have an alternative
method, leading to comparable results in a fraction of simulation time. SPICE simulations are a good
alternative to do huge amounts of simulations in a comparatively small period of time. Chapter 7 already
presented the extraction and compact modeling methods for four different device architectures, including
multi-gate SOI MOSFETs. Now, it is be investigated, if it is possible to do the same simulation amount,
presented previously, by using the extracted compact models of Chapter 7.
The compact model of the SG FDSOI NMOSFET with a physical gate length of 32 nm was used to
compare SPICE simulation results to the results achieved by the CoLiDe simulation. The same CDvalues
of the lithography simulations were used in the SPICE simulation, to ensure comparability. Figure 8.6(a)
shows the I
on
-I
off
simulation results of the CoLiDe simulations (squares) and the SPICE simulations
using the CD distribution of CoLiDe (triangles). As can be seen in Fig. 8.6(a), the SPICE model strongly
overestimates the variations of I
on
, compared to the results of CoLiDe, although the values of leakage
current I
off
were already nearly reproduced by the EPFL-EKV model. The results presented in Fig. 8.6(a)
indicate that the compact model has to be adjusted, to reproduce the behavior of the TCAD model with
respect to gate length variations. Furthermore, the asymmetrical behavior of the threshold voltage has
to be taken into account by the compact model. Thinking of SOI devices leads to the conclusion that a
sensitivity of the compact model on body thickness variations is necessary. Due to the fact that the EPFL-
EKV model is actually a compact model for bulk MOSFETs, the sensitivity on body thickness variations
of SOI devices is not included in the model. To take the asymmetrical behavior of the threshold voltage
and the body thickness dependency of the threshold voltage into account, a compact modeling of the
variation dependencies for basic model parameters was done. Therefore, a variety of TCAD simulations
at several physical gate lengths and lm thicknesses of the SOI body were performed in combination,
keeping the computational effort low. Then, the values for the low-eld threshold voltage were plotted
over the values of L
gate
and t
body
, shown in Fig. 8.6(b). After that, a surface tting by using a two
dimensional polynomial function of second order was done:
V
th
(L
gate
, t
body
) = z +aL
gate
+bt
body
+cL
2
gate
+dt
2
body
+eL
gate
t
body
. (8.1)
(a) (b)
Figure 8.6 Compact modeling analysis for V
th
(L
gate
,t
body
) dependence: (a) I
on
-I
off
characteristic;
(b) V
th
(L
gate
,t
body
) dependence
The t parameters a, b, c, d, e, z, and Eq. (8.1) were nally applied to change the low-eld threshold volt-
age VTO in the EPFL-EKV model in dependency on the CD and the body thickness. Additionally, the
doping concentration NSUB of the EPFL-EKV model was adjusted. The value of NSUB is responsible
for the subthreshold slope of transfer characteristics in the compact model. To account for the impact
of silicon lm thickness variations in SOI transistors, NSUB was multiplied by the relation t
body
/L
gate
.
Thus, NSUB increases if the silicon lm thickness does or the gate length decreases and the other way
round. The subthreshold slope nally reacts the same way, depending on t
body
/L
gate
. The DIBL , which
is dened by the parameter LAMBDA in the EPFL-EKV model, was set into dependence of the body
thickness by the relation of t
body
/t
body,nominal
. Finally, the saturation velocity VMAX was changed in
dependence on the physical gate length:
VMAX = VMAXinit (1.0 L
gate
/L
gate,nominal
) vFactor, (8.2)
where L
gate,nominal
is the nominal physical gate length of the device and vFactor is a t parameter den-
ing the impact on the nominal saturation velocity VMAXinit. Using the modications done for the
threshold voltage, the subthreshold slope, the DIBL and the saturation velocity, SPICE simulations were
performed again, applying the variety of the CD values resulted from lithography simulations to the de-
vice. The results are displayed in Fig. 8.6(a) and denoted by the circles. Using the process variability
compact modeling (PVCM), presented above, forces the EPFL-EKV model to reproduce the behavior of
the TCAD model of the 32 nm gate length SG FDSOI under gate length variations very well (Fig. 8.6(a)).
Furthermore, the computational effort is reduced to 30 minutes on one processor core (compare CoL-
iDe: 1.5 days on 40 CPU cores). Due to the fact that it was not possible to simulate three dimensional
devices with the CoLiDe method the investigations for FinFET devices were done by the PVCM method
and the multi-gate compact model presented in Chapter 7. For comparison, the values of the CD cal-
culated from the lithography simulation were used again for the simulation of the TG FinFET with an
nominal physical gate length of 32 nm (Chapter 7). Figure 8.7(a) displays the PDF of V
th
calculated by
the SPICE simulation. The distribution is strongly asymmetric and GEV like, due to the lightly doped
channel of the TG FinFET again. This is also conrmed by Fig. 8.7(b) where the threshold voltage be-
havior of the bulk MOSFET (squares), SG FDSOI MOSFET (circles), DG FDSOI MOSFET (crosses),
and the TG FinFET (stars) are plotted over the physical gate length resulted from the lithography sim-
ulations. The threshold voltage of the three SOI devices (SG, DG, TG) show nearly the same roll-off
behavior. It has to be mentioned that the kink in the TG FinFET characteristics results from the process
variability compact modeling (PVCM) method. Maybe, using other compact models for these kind of
devices would lead to a more stable and qualitatively better reproducing of the FinFET behavior. How-
ever, the basic behavior of the FinFET was reected by the PVCM method. The bulk MOSFET shows
a more stable behavior against the uctuations of the physical gate length, due to the pocket implants.
Even the reverse short channel effect (RSCE) slightly increases the threshold voltage at decreasing gate
lengths was observed for bulk MOSFETs. The threshold voltage adjustment caused by the source/drain
pocket implants of the bulk also lead to less uctuations of the leakage current, seen in Fig. 8.7(c), which
displays the I
on
-I
off
relation of the four different MOSFET architectures under lithography induced gate
length variations. The bulk MOSFETs (NMOS and PMOS), denoted by the squares, show the most sta-
ble behavior compared to the three SOI devices again the gate length uctuations. The uctuation rate
of the three SOI devices, SG FDSOI (circles), DG FDSOI (crosses), and TG FinFET (stars) nearly have
a comparable sensitivity on the uctuations.
8.2 Compact modeling of R
co
(T
peak
, N
2
) Dependence 121
(a) (b)
(c)
Figure 8.7 Electrical behavior of four different CMOS device architectures with an nominal physical gate length
of 32 nm under lithography induced gate length variability: (a) PDF of V
th
of the TG FinFET; (b) V
th
behavior
under lithography induced gate length variations; (c) I
on
-I
off
clouds under lithography induced gate length vari-
ations
8.2 Compact Modeling of Contact Resistance Dependence on Annealing
Temperature and Ion Dose Variability
One of the major problems discussed in this work is the impact of contact resistances on the electrical
behavior of nano-scaled CMOS devices. Thus, the impact of process variations on contact resistances
is discussed and investigated in this chapter, too. It has to be mentioned that uctuations of the met-
allization layers, grain boundary uctuations and the like, were neglected in this work. The impact of
annealing temperature uctuations and ion dose uctuations were rather discussed and investigated, be-
cause these parameters directly inuence the surface doping concentration at the metal/semiconductor
interface. Therefore, a closer look on the ash annealing step, used in the coupled spike-ash annealing
discussed in Chapter 2 and [90] was taken.
The effect of local temperature uctuations during ash annealing effecting single devices if the pattern
density increases was already reported in the literature by Kubo [111]. Kubo et al. measured temperature
uctuations during ash annealing of about 100
C within a die. To take the impact of temperature

uctuations on the amount of contact resistances into account, the measured temperature prole of a
ash annealing process used in this work was tted by an extreme values function (Eq. (8.3)), seen in
Fig. 8.8(a). It has to be mentioned that only the temperature peak, lasting some milliseconds (T
peak
=
1300
C, t
peak
= 2.5 ms), was varied:
T = T
pre
+T
exp(exp(z) z + 1), z =
(t x
c
)
w
. (8.3)
In Eq. (8.3), x
c
and w are t parameters, t is the annealing time, and T
represents the difference of

the maximum temperature and the nominal pre-temperature T
pre
. The only parameter to be varied for
changing the whole temperature prole is nally parameter T
. Figure 8.8(b) shows an exampled of a

band of temperature proles, using a Gaussian distributed factor T
.
Equation (8.3) was nally used in process simulations to investigate how the contact resistances behave
at several peak temperatures T
peak
of the ash annealing. Therefore, the same 32 nm gate length devices
presented previously were used. Additionally, the implantation dose of the source/drain contact regions
was varied to observe the contact resistances concurrently at different peak temperatures and implantation
doses. After that, the contact resistances of NMOS and PMOS transistors were extracted and plotted over
the ion dose N
2
and peak temperature (Fig. 8.9). Finally, a two dimensional polynomial function was
assumed for modeling the dependence of R
co
(T
peak
,N
2
). The process variability compact model PVCM
of the contact resistances in dependence on the peak temperature T
peak
and the ion dose N
2
is described
by
R
co
(T
peak
, N
2
) =
z +aT
peak
+bN
2
+cT
2
peak
+dN
2
2
+eT
peak
N
2
W
device
. (8.4)
Here again, a, b, c, d, e, z are t parameters, while W
device
is the width of the contact area. The results of
numerical TCAD simulations are shown by a continuous surface in Fig. 8.9(a).
(a) (b)
Figure 8.8 (a) Fit function for ash temperature prole; (b) Simulated peak temperature variations
8.3 Low Standby Power CMOS Devices Under the Impact of Process Variations 123
(a) (b)
Figure 8.9 (a) Compact modeling analysis for R
co
(T
peak
,N
2
) dependency compact modeling; (b) SPICE sim-
ulation results compared to TCAD simulation results for I
on
-I
off
At last, the I
on
-I
off
relation of the TCAD model of the 32 nm gate length SG FDSOI were compared to
the respective variational compact model including the PVCM of R
co
. Figure 8.9(b) shows the results
of the TCAD (squares) and SPICE (circles) simulations. As can be seen, the on-current values of the
variational SPICE model correspond very well to the results of the TCAD simulations. Figure 8.9(b) also
shows that uctuations of the annealing temperature only have a slight impact on the leakage current.
Thus, the impact of peak temperature variability on the threshold voltage in the PVCM SPICE model
used for variability analysis was neglected in this work, to keep a minimum modeling effort.
8.3 Low Standby Power CMOS Devices Under the Impact of Process
Variations
In Chapters 6 and 7, four HP, LOP, and LSTP CMOS device architectures were investigated under dif-
ferent operation conditions. It could be shown, how the charge carrier mobility of the different MOSFET
architectures can be improved by mechanical stress. Contact resistances were found to limit the perfor-
mance of all MOSFET architectures more or less. The four CMOS device architectures were also used
in integrated circuit simulations to discuss advantages and disadvantages of the four MOSFET architec-
tures if they are used in different circuit applications. Triple gate FinFET transistors were found to result,
on average, in the best performances. But for a nal statement, which device architectures seems to be
the most suitable for future CMOS technology nodes, the four different device architectures have to be
investigated under the impact of process variations.
Four different process uctuations were applied to the four different CMOS device architectures: gate
length uctuations, body thickness uctuations for SOI devices, ash annealing temperature uctuations,
and uctuations of the source/drain contact area doping. Here again, the LSTP devices with a physical
gate length of 20 nm were used. These investigations were done using compact models to reduce the
computational effort. The compact models presented in Chapter 7 were upgraded by the process vari-
ability compact models (PVCM) presented in Subsection 8.1.3 and Section 8.2. To simulate the impact
of gate length variability, the same distribution of the critical dimension resulted from the lithography
simulations (Subsection 8.1.1) was used, but with a larger etch bias of 25 nm. Actually, an additional
(a) (b)
Figure 8.10 Impact of gate length variations on the electrical performance of four different CMOS device
architectures: (a) Threshold voltage behavior; (b) I
on
-I
off
relation
lithography simulation setup should be done, optimized for the nominal physical gate length of 20 nm.
However, the question of which lithography technique (extreme ultra violet (EUV) lithography, or double
patterning) will be used for the 32 nm technology node was not answered during this thesis. Therefore,
the assumption of a larger etch bias was used. In this manner, the asymmetric PDF of the CD obtained
by lithography simulations was applied for lower feature scales.
To take body thickness uctuations of the SOI devices into account, a Gaussian distribution of t
body
was assumed. The median was set to the nominal body thickness, while a standard deviation of 1.67 %
of the nominal lm thickness was set [9]. The uctuations of the peak temperature T
peak
of the ash
annealing were assumed to be Gaussian distributed, too. Again, the nominal temperature of 1282
C was
used as median and a standard deviation of 1 % of the nominal temperature was applied. The standard
deviation of the temperature was estimated by comparing measured ash temperature proles, which
were, however, not published in the literature. Finally, the doping concentration of the spin-on-dopant
source, used to form a homogenous active doping concentration at the side walls of the contact trenches
was varied by a Gaussian distribution with median equal to the nominal doping concentration and 3.3 %
of the nominal doping concentration as standard deviation. In case of the bulk MOSFET, the impact of
so called random discrete dopants (RDD) in the channel region was taken into account as well. Random
discrete dopants are statistically distributed dopants, which cause threshold voltage uctuations [110].
The threshold voltage uctuation was taken into account by using a Gaussian PDF for the nal low eld
threshold voltage VTO in the EPFL-EKV model. The mean value of the Gaussian PDF was set to the low
eld threshold voltage calculated in dependence on the physical gate length, rst of all. From threshold
voltage distributions of 42 nm gate length bulk MOSFETs, presented in the literature [112], a standard
deviation of 3.3 % of the mean value was assessed. Due to the fact that the channels of SOI devices are
mainly undoped, RDD were neglected in case of FDSOI CMOS devices.
8750 variations of the physical gate length, body thickness, temperature, and doping concentration were
simulated, respectively. Figure 8.10 shows the impact of process variations on the electrical performance
of the four CMOS architectures discussed in this work. The impact of gate length variations on the
threshold voltage behavior of NMOS and PMOS devices is shown in Fig. 8.10(a). In principle, all
device architectures show nearly the same stability against the gate length variations. The only device
showing a stronger threshold voltage roll-off is the NMOS bulk MOSFET. This device is already in
a normally on state at a physical gate length of 10 nm. Contrary to the 32 nm bulk devices discussed
in Subsection 8.1.2, the self-alignment of the threshold voltage, due to the pocket implants, did not
help to hold the threshold voltage on a constant level for the smaller 20 nm devices. However, this
example shows that device engineering can not only be done by adjusting the threshold voltage, leakage,
and drive current. Compared to the SOI devices, a stronger uctuations of the threshold voltage was
calculated for the bulk MOSFET transistors. As can be seen in Fig. 8.10(a), the threshold voltage of
the bulk MOSFET over the whole simulation experiment is wider distributed than the threshold voltage
of the three SOI devices. The wider range of distribution results from the impact of RDD assumed
for the bulk MOSFET transistors. Here, the SOI devices denitely have an advantage compared with
the bulk MOSFETs. However, if the relative standard deviations ( 100/) of the threshold voltages
of the four CMOS device architectures are compared to each other, the difference is not that great.
A relative standard deviation of 25.5 % was calculated for the threshold voltage of the NMOS bulk
MOSFET, relative = 23.2 % was calculated for V
th
of the SG FDSOI NMOS, 18.4 % in case of the
DG FDSOI NMOS, and nally 17.0 % relative standard deviation was found for the threshold voltage
of the TG FinFET. The difference between the lowest relative standard deviation, calculated for the TG
FinFET NMOS and the highest relative , calculated for the bulk NMOS transistor, is only 8 % (20 mV
in absolute value). In case of the PMOS transistors, the bulk MOSFET even shows the lowest relative
standard deviation of approximately 9 %. The mean values , standard deviations and relative for
NMOS and PMOS devices are listed in Tabs. 8.1 and 8.2, respectively.
Figure 8.10(b) shows the I
on
-I
off
values of the whole simulation experiment, including all variations
assumed (L
gate
, t
body
, T
peak
, N
d,a
). As already observed in Fig. 8.7(c), the bulk MOSFETs
(Fig. 8.10(b) squares) show a better I
off
stability against the process variations, compared to the SOI
transistors with lightly doped channels. The relative standard deviation of I
off
was calculated to be
approximately half of the value for the SG FDSOI devices and TG FinFET devices (Tabs. 8.1 and 8.2)
and even more than four times lower compared to the DG FDSOI devices. Due to the lightly doped
channels, the SOI devices (SG FDSOI (circles), DG FDSOI (crosses), and TG FinFET (stars)) show a
wide leakage current distribution with a maximum relative standard deviation of more than a factor of 29,
calculated for the DG FDSOI devices. Here, the bulk MOSFET has denitively an advantages compared
to the SOI devices, due to the self adjusting effect resulting from the source/drain pocket implants. If the
drive current uctuations of the four CMOS device architectures are compared, the multi-gate devices
show the highest stability against process variations. Here, the TG FinFET was found to have the most
stable on-current behavior. The relative standard deviation of I
on
was calculated to be only 5 % for both,
the NMOS transistor and the PMOS transistor. Furthermore, it can be seen in Tabs. 8.1 and 8.2 that the
on-current uctuation becomes better by replacing the bulk MOSFETs by SG FDSOI MOSFETs. The
better on-current stability of the SOI devices is therefore favorable for the use in integrated circuits, as
the charging and discharging of integrated capacitances becomes more stable.
Tables 8.1 and 8.2 also include the values for the simulation experiments of varying the body thickness,
ash annealing peak temperature T
peak
, and doping concentration of the spin-on-dopant source used
for the source/drain contacts, respectively. Obviously, the uctuations of the doping concentration has
more or less no effect on the drive currents of the transistors, although 3.3 % standard deviation of
the doping concentration was assumed. This might be different, if standard ion implantation is used
for the doping of the source/drain regions. The uctuation of the temperature also has only a small
impact on the drive currents, which might result from the small temperature range used to vary the peak
temperature of the ash prole. The effect of the body thickness uctuations results only in relative
standard deviation of the threshold voltage of below 2 %. This is also shown in by Fig. 8.11. Here, the
threshold voltage of the whole simulation experiment is drawn over the gate length and the body thickness
change (t
body
/t
body,nominal
) for NMOS and PMOS devices. As can be seen in Fig. 8.11, the impact of the
body thickness on the threshold voltage is very small, while gate length uctuations are dominating the
variability of the threshold voltage. Apparently, gate length variations still have the highest impact on
the electrical performance of CMOS devices. However, opposite to temperature uctuations, resulting
from pattern density [111] and affecting every single device on a die, or random discrete dopants, gate
length variations resulting from the lithography can be reduced by dening strict lithography process
conditions [98].
Figure 8.11 Threshold voltage behavior under process variations ((L
gate
, t
body
, T
peak
, N
d,a
)
Table 8.1 Mean values, standard deviations and relatively standard deviations of electri-
cal performance parameters of four different CMOS NMOS device architectures
Bulk SG FDSOI DG FDSOI TG FinFET
V
th
,Lgate
(mV) 321.8 326.0 337.0 337.0
V
th
,Lgate
(mV) 82.2 75.5 62.1 59.9
relative
V
th
,Lgate
(%) 25.5 23.2 18.4 17.1
Ion,Lgate
(A/m) 413.5 593.3 401.3 675.0
Ion,Lgate
(A/m) 58.7 78.6 29.0 33.6
relative
Ion,Lgate
(%) 14.2 13.3 7.23 4.98
I
off
,Lgate
(nA/m) 201.0 36.4 0.059 0.0711
I
off
,Lgate
(nA/m) 1382.1 532.0 1.6 1.09
relative
I
off
,Lgate
(dec) 0.83 1.16 1.44 1.19
V
th
,t
body
(mV) - 349.0 349.0 356.0
V
th
,t
body
(mV) - 3.74 2.3 2.6
relative
V
th
,t
body
(%) - 1.07 0.67 0.72
Ion,t
body
(A/m) - 591.7 440.3 721.0
Ion,t
body
(A/m) - 5.34 1.77 5.84
relative
Ion,t
body
(%) - 0.90 0.4 0.81
I
off
,t
body
(nA/m) - 0.584 0.0632 0.085
I
off
,t
body
(nA/m) - 0.07 0.0065 0.00078
relative
I
off
,t
body
(dec) - 0.05 0.042 0.004
Ion,T
peak
(A/m) 430.6 591.7 440.1 720.4
Ion,T
peak
(A/m) 4.24 5.51 1.04 3.21
relative
Ion,T
peak
(%) 0.98 0.93 0.23 0.44
Ion,N
d
(A/m) 430.0 590.0 440.0 720.0
Ion,N
d
(A/m) 0.0 0.0 0.0 0.0
relative
Ion,N
d
(%) 0.0 0.0 0.0 0.0
V
th
,complete
(mV) 322.0 326.0 337.0 337.0
V
th
,complete
(mV) 82.4 75.6 62.1 60.0
relative
V
th
,complete
(%) 25.6 23.2 18.4 17.8
Ion,complete
(A/m) 413.3 593.2 401.4 674.9
Ion,complete
(A/m) 58.9 78.7 29.3 34.0
relative
Ion,complete
(%) 14.3 13.2 7.28 5.0
I
off
,complete
(nA/m) 203.0 35.2 0.056 0.071
I
off
,complete
(nA/m) 1395.0 521.0 1.53 1.08
relative
I
off
,complete
(dec) 0.83 1.17 1.43 1.17
Table 8.2 Mean values, standard deviations, and relatively standard deviations of electri-
cal performance parameters of four different CMOS PMOS device architectures
V
th
,Lgate
(mV) 338.0 329.0 339.0 331.0
V
th
,Lgate
(mV) 31.6 62.5 67.1 56.3
relative
V
th
,Lgate
(%) 9.36 19.0 19.8 17.0
Ion,Lgate
(A/m) 260.5 606.6 390.9 584.9
Ion,Lgate
(A/m) 46.6 85.0 40.7 46.4
relative
Ion,Lgate
(%) 17.9 14.0 10.4 7.94
I
off
,Lgate
(nA/m) 37.2 11.7 0.062 0.034
I
off
,Lgate
(nA/m) 1053.7 158.3 1.87 0.50
relative
I
off
,Lgate
(dec) 1.45 1.13 1.47 1.17
V
th
,t
body
(mV) - 352.0 353.0 351.0
V
th
,t
body
(mV) - 4.52 2.77 1.8
relative
V
th
,t
body
(%) - 1.28 0.78 0.5
Ion,t
body
(A/m) - 606.2 448.0 649.8
Ion,t
body
(A/m) - 7.8 4.08 3.28
relative
Ion,t
body
(%) - 1.28 0.91 0.5
I
off
,t
body
(nA/m) - 0.28 0.059 0.036
I
off
,t
body
(nA/m) - 0.042 0.0069 0.0026
relative
I
off
,t
body
(dec) - 0.06 0.048 0.03
Ion,T
peak
(A/m) 253.0 604.2 446.6 648.7
Ion,T
peak
(A/m) 4.89 15.4 9.39 8.13
relative
Ion,T
peak
(%) 1.9 2.55 2.1 1.25
Ion,Na
(A/m) 250.0 606.6 449.9 650.0
Ion,Na
(A/m) 0.0 85.1 0.6 0.0
relative
Ion,Na
(%) 0.0 14.0 0.1 0.0
V
th
,complete
(mV) 338.0 329.0 339.0 331.0
V
th
,complete
(mV) 31.6 62.7 67.2 56.2
relative
V
th
,complete
(%) 9.37 19.1 19.8 17.0
Ion,complete
(A/m) 260.1 604.7 390.2 583.9
Ion,complete
(A/m) 46.5 86.7 41.3 46.7
relative
Ion,complete
(%) 17.8 10.6 16.7 8.0
I
off
,complete
(nA/m) 28.9 11.8 0.062 0.033
I
off
,complete
(nA/m) 649.1 158.3 1.79 0.47
relative
I
off
,complete
(dec) 1.35 1.13 1.46 1.15
8.4 Circuit Behavior 129
8.4 Circuit Behavior
Besides the investigation of the electrical behavior of different MOSFET architectures inuenced by pro-
cess variations, the stablilty of integrated circuit blocks inuenced by variability was investigated in this
work. Therefore, the same four circuit blocks discussed in Section 7.3 were used. Again, four different
variations were assumed to inuence the different circuit blocks: L
gate
, t
body
, T
peak
, N
d,a
. It has
to be mentioned that the same asymmetric PDF of the critical dimension that resulted from the lithog-
raphy simulations were used in the circuit simulation. However, the PDF of the CD was calculated for
periodically ranged lines on the mask in the lithography simulation setup [107]. In case of the single
inverter stage and ring oscillator, the assumption of a periodically ranged lines layout might be appropri-
ately. But, for taking into account realistic PDFs of the CD in circuit simulations, the lithography process
actually has to be adapted by a real layout of the respective circuit blocks. Especially in case of the 4-bit
ripple carry adder and the 6-T SRAM cell it is necessary to use realistic mask layouts, as the assumption
of periodically ranged lines is not valid anymore. However, because of no mask layouts for the differ-
ent circuit blocks were available during this work, the PDF of the CD achieved for periodically ranged
lines was also used for investigating the stability of the 4-bit ripple carry adder and 6-T SRAM cell under
lithography induced gate length variations.
8.4.1 Logic Gates
8.4.1.1 Inverter
First of all, a single inverter stage was impacted by process variations. The inverter threshold V
M
was
investigated by only taking into account gate length variations. Figure 8.12(a) shows the behavior of V
M
at decreasing gate lengths. For the bulk MOSFET based inverter stage (squares), a decreasing inverter
threshold was observed at decreasing gate lengths, with a wide distribution of V
M
, due to random discrete
dopants. Looking back to the single device observation under gate length variations, the falling trend of
the bulk MOSFET based inverter stage can be explained by the worse stability of V
th
of the NMOS
transistor. Due to the faster roll-off of the NMOS threshold voltage, the NMOS transistor switches on
earlier and effect a faster grounding of the output node [102]. Compared to the SOI MOSFETs the
relative standard deviation of the inverter threshold of the bulk MOSFET based inverter stage is the
highest (5 %). All mean values, standard deviations, and relative standard deviations of the inverter
stage simulation experiment are listed in Tab. 8.3. The lowest uctuation of the inverter threshold was
calculated for the SG FDSOI device, which is illustrated by looking at Fig 8.12(a). Additionally to
the inverter threshold, the bandwidth of the propagation delay (t
prop
) was calculated at decreasing gate
lengths. The behavior of t
prop
of the four inverter stages based on different MOSFET architectures
is shown in Fig. 8.12(b). At rst glance, the bulk MOSFET based inverter again shows the strongest
uctuation of the propagation delay, again due to the RDD. This is proven, by calculating the relative
standard deviation from the mean value. The propagation of the bulk MOSFET based inverter is the most
unstable (relative = 55 %), compared to SOI based inverter stages. If the bulk MOSFET is replaced
by the SG FDSOI MOSFET, the relative standard deviation of t
prop
is reduced by more than a half to
18 %. The use of multi-gate devices further improves the stability of the dynamic inverter performance
against gate length uctuations. The DG FDSOI MOSFET based inverter stages result in a relative
standard deviation of t
prop
of 16 %. The overall best stability of t
prop
was achieved by using TG FinFET
transistors (relative = 10 %). The mean values, standard deviations, and relative standard deviations of
(a) (b)
Figure 8.12 Inuence of variability on inverter performance using four different device architectures:
(a) Gate length, body thickness, temperature and doping concentration variability impact on inverter thresh-
old V
M
; (b) Gate length variability impact on propagation delay
the whole inverter variability simulation experiment are listed in Tab. 8.3. Figure 8.13 nally shows the
behavior of the inverter threshold V
M
if the four variations discussed previously were taken into account
concurrently. As already discussed, the SOI device based inverter stages show, compared to the bulk
MOSFET based inverter stage, a relatively stable behavior under the inuence of process variations.
Differently to the single device investigations, the inverter stage based on SG FDSOI MOSFETs showed
the best stability against process variations. Only in the TG FinFET and the bulk MOSFET were found
to have a better stability of the propagation delay (Tab. 8.3). Furthermore, it can be seen in Fig. 8.13
Figure 8.13 Inverter threshold behavior under process variations using
four different CMOS device architectures (bulk transistors are shown at
t
body
/t
body,nominal
= 1)
Table 8.3 Mean values, standard deviations, and relatively standard deviations of inverter
stage performance parameters based on four different CMOS device architectures
V
M
,Lgate
(mV) 429.3 449.7 449.5 438.2
V
M
,Lgate
(mV) 24.6 4.4 9.2 10.4
relative
V
M
,Lgate
(%) 5.75 0.99 2.1 2.38
V
M
,t
body
(mV) - 449.9 447.7 435.5
V
M
,t
body
(mV) - 0.35 0.7 0.28
relative
V
M
,t
body
(%) - 0.07 0.02 0.06
V
M
,complete
(mV) 429.3 449.8 409.5 438.1
V
M
,complete
(mV) 24.4 4.5 9.4 10.4
relative
V
M
,complete
(%) 5.69 1.01 2.3 2.39
UDR ,Lgate
(mV) 106.0 117.0 88.2 11.6
UDR ,Lgate
(mV) 55.5 63.8 51.3 64.7
relative
UDR ,Lgate
(%) 52.6 54.7 58.1 56.0
UDR ,t
body
(mV) - 90.6 71.9 95.8
UDR ,t
body
(mV) - 1.6 1.2 1.2
relative
UDR ,t
body
(%) - 1.86 1.8 1.28
UDR ,complete
(mV) 106.0 117.0 88.3 116.0
UDR ,complete
(mV) 55.5 63.9 51.2 64.6
relative
UDR ,complete
(%) 52.6 54.8 58.4 55.9
tprop,Lgate
(ps) 19.2 9.4 8.4 7.58
tprop,Lgate
(ps) 9.9 1.72 1.36 0.75
relative
tprop,Lgate
(%) 52.0 18.1 16.2 9.9
tprop,t
body
(ps) - 9.33 8.17 7.5
tprop,t
body
(ps) - 0.11 0.053 0.037
relative
tprop,t
body
(%) - 1.22 0.64 0.5
tprop,T
peak
(ps) 18.7 9.33 8.14 7.51
tprop,T
peak
(ps) 0.09 0.04 0.095 0.16
relative
tprop,T
peak
(%) 0.5 0.42 1.17 2.22
tprop,N
d,a
(ps) 18.7 9.32 8.17 7.5
tprop,N
d,a
(ps) 0.038 0.012 0.019 0.022
relative
tprop,N
d,a
(%) 0.2 0.13 0.2 0.3
tprop,complete
(ps) 19.2 9.45 8.41 7.6
tprop,complete
(ps) 10.4 1.73 1.35 0.75
relative
tprop,complete
(%) 54.2 18.3 16.1 9.9
that the gate length variations have the greatest impact on the electrical performances of SOI MOSFET
transistors.
Figure 8.14 Inuence of variability on ring oscillator frequency
8.4.1.2 Ringoscillator
The next point of interest was the frequency behavior of the seven inverter stage ring oscillator under
the inuence of process variations. Figure 8.14 shows the distribution of the ring oscillator frequencies
over the gate length and body thickness resulted from process variations. It was already observed in
case of one inverter stage that the bulk MOSFET based ring oscillator surprisingly seems to be the most
stable device. The relative standard deviation of the bulk MOSFET based ring oscillator was calculated
to be 22 % from the mean value. The most unstable behavior was calculated for the SG FDSOI device
(relative = 41 % from ). Although the threshold voltage shift, due to RDD, was calculated for each
of the bulk MOSFETs in the ring oscillator separately, a self adjusting of the frequency can be observed.
The stability of the two multi-gate MOSFETs, DG FDSOI, and TG FinFET, based ring oscillators was
calculated to be equal (relative = 32 %). All mean values, standard deviations, and relative standard
deviations of the ring oscillator frequency are listed in Tab. 8.4.
Table 8.4 Mean values, standard deviations, and relatively standard deviations of seven
stage ring oscillator frequency based on four different CMOS device architectures
Frequency,Lgate
(GHz) 11.6 25.6 35.9 34.4
Frequency,Lgate
(GHz) 2.5 10.5 11.5 11.2
relative
Frequency,Lgate
(%) 21.6 40.9 32.1 32.5
Frequency,t
body
(GHz) - 23.7 35.7 32.8
Frequency,t
body
(GHz) - 0.22 0.83 0.99
relative
Frequency,t
body
(%) - 0.96 0.23 0.3
Frequency,complete
(GHz) 11.6 25.6 35.8 34.4
Frequency,complete
(GHz) 2.6 10.5 11.4 11.1
relative
Frequency,complete
(%) 22.3 41.0 31.9 32.3
8.4.1.3 Ripple Carry Adder
The last logic gate observed in this work under the impact of process variations is the 4-bit ripple carry
adder, already discussed in Subsection 7.3.2. First of all, the carry-ag delay t
carry
was investigated. It
has to be mentioned that the threshold voltages of every single MOSFET device of the bulk MOSFET
based 4-bit ripple carry adder were separately (112 devices) be impacted with the impact of RDD, to
ensure realistic WiD variability conditions. Figure 8.15(a) shows the behavior of t
carry
under the impact
of lithography resulted gate length variations. Although the bulk MOSFET adder (Fig. 8.15(a) squares)
was inuenced additionally by RDD, the carry-ag delay stays more constant, oppositely to the SOI
devices (Fig. 8.15(a) SG FDSOI circles, DG FDSOI crosses, TG FinFET stars). This is proven by
looking at Tab. 8.5, which includes all mean values, standard deviations, and relative standard deviations
of the carry-ag delay and the sum signal delay t
sum
. The SOI devices show a strong roll-off of the
carry-ag delay. A comparable behavior was found in case of the sum signal delay t
sum
, which is shown
in Fig. 8.15(b). Here, the bulk MOSFET based adder resulted in the lowest relative standard deviation
around the mean value (Tab. 8.5). The TG FinFET based adder, which was assumed to be the most
stable device, due to the results presented in Section 8.3, however, was found to be the less stable circuit
investigated. A relative standard deviation of 36 % and 41 % around the mean value was calculated for
the carry-ag delay and the sum signal delay, respectively. This proves the assumption that single device
behavior investigation under process variability is not enough for a qualitatively characterization.
(a) (b)
Figure 8.15 Impact of gate length uctuations on 4-bit ripple carry adder performance: (a) Impact of gate length
uctuations on carry ag delay; (b) Impact of gate length uctuations on sum signal delay
8.4.2 Memory: Static Random Access Memory Cell
6-transistor SRAM cells are a very common integrated circuit for MOSFET architecture characteriza-
tion under integrated circuit conditions. In Subsection 7.3.3, TG FinFETs were found to be the most
suitable devices for these kind of integrated circuit. Now, the impact of process variability on the static
noise margin (SNM) and the read delay is investigated by using again four MOSFET architectures. Fig-
ure 8.16(a) shows the SNM of the 6-T SRAM cell under the impact of lithography resulted gate length
variations. As already mentioned, the impact of RDD in the bulk MOSFET devices was taken into ac-
count separately for every single device of the bulk MOSFET based SRAM cell to take the effect of
Table 8.5 Mean values, standard deviations, and relatively standard deviations of 4-bit
ripple carry adder performance parameters based on four different CMOS device archi-
tectures
tcarry,Lgate
(ps) 159.4 68.4 52.0 31.6
tcarry,Lgate
(ps) 48.8 23.8 16.5 11.7
relative
tcarry,Lgate
(%) 30.64 33.9 31.8 36.9
tcarry,t
body
(ps) - 65.7 48.8 30.4
tcarry,t
body
(ps) - 0.7 0.15 0.2
relative
tcarry,t
body
(%) - 1.06 0.32 0.53
tcarry,complete
(ps) 159.7 68.5 52.1 31.7
tcarry,complete
(ps) 48.8 23.2 16.6 11.6
relative
tcarry,complete
(%) 30.6 33.9 31.9 36.5
tsum,Lgate
(ps) 47.3 20.3 16.0 9.5
tsum,Lgate
(ps) 4.8 6.7 5.0 3.9
relative
tsum,Lgate
(%) 10.3 33.3 31.1 41.8
tsum,t
body
(ps) - 19.4 15.0 9.2
tsum,t
body
(ps) - 0.22 0.09 0.2
relative
tsum,t
body
(%) - 1.18 0.66 1.9
tsum,complete
(ps) 45.2 20.3 16.0 9.56
tsum,complete
(ps) 6.55 6.78 5.0 4.0
relative
tsum,complete
(%) 14.5 33.3 31.3 41.8
WiD variations into account. In Fig. 8.16(a) a strong roll-off of the SNM is observed for each device ar-
chitecture. Especially at a physical gate length of 15 nm, the 6-T SRAM cell becomes totally unstable,
independent from the used CMOS device architecture. Again, RDD in the bulk MOSFET based SRAM
cell (Fig. 8.16(a) squares) causes a wide distribution of the SNM. Although the bulk MOSFET was char-
acterized as to result in the most stable behavior in the 4-bit ripple carry adder circuit, the disadvantages
of this architecture further become clear if the device is used in memory cells. A relative standard devia-
tion of 50 % was calculated for the SNM of the bulk MOSFET based SRAM cell. It can be observed that
the stability of the SRAM cell against gate length variations can be increased by switching to SOI MOS-
FETs and especially multi-gate devices (Tab. 8.6). Thereby, the TG FinFET based SRAM cell was found
to be the most stable setup (relative = 5 %), followed by the DG FDSOI based SRAM cell (relative
= 13.5 %). The same behavior was observed by looking at the read delay t
read
(at C
load
= 6 fF) un-
der the inuence of gate length variations (Fig. 8.16(b)). An effect observed, is the fact that the relative
standard deviations calculated for the SNM seemed to be directly mirrored to the read delay behavior.
In Tab. 8.6, which includes the mean values, standard deviations, and relative standard deviations of the
SNM and t
read
, the values for relative of t
read
under the impact of gate length variations are more or less
equal to relative of the SNM. One disadvantage of the TG FinFET, not recognized before, was found
for the stability against lm thickness variations, if the device is used in 6-T SRAM cells. The SNM as
t
read
were stronger inuenced by n thickness variations than it was observed for planar devices, listed
in Tab. 8.6. Due to the fact that the DG FDSOI MOSFET based SRAM cell showed a more or less im-
mune behavior against body thickness variations, the relative standard deviation of the SNM is smaller
for the DG SRAM cell if the four process variations assumed were used simultaneously.
Table 8.6 Mean values, standard deviations, and relatively standard deviations of
6-T SRAM cell performance parameters for four different CMOS device architectures
SNM ,Lgate
(V) 65.9 191.6 191.0 215.0
SNM ,Lgate
(V) 32.9 45.4 25.8 11.1
relative
SNM ,Lgate
(%) 50.1 23.7 13.5 5.17
SNM ,t
body
(V) - 206.0 197.0 206.0
SNM ,t
body
(V) - 0.8 0.8 1.2
relative
SNM ,t
body
(%) - 0.39 0.4 0.612
SNM ,complete
(V) 66.0 192.0 191.0 194.0
SNM ,complete
(V) 32.9 45.3 26.1 40.2
relative
SNM ,complete
(%) 49.9 23.6 13.7 20.8
t
read
,Lgate
(ps) 421.0 145.0 172.0 74.2
t
read
,Lgate
(ps) 211.1 27.7 18. 3.26
relative
t
read
,Lgate
(%) 50.0 19.1 10.5 4.4
t
read
,t
body
(ps) - 141.0 170.0 69.6
t
read
,t
body
(ps) - 1.4 0.78 1.13
relative
t
read
,t
body
(%) - 0.99 0.46 1.63
t
read
,complete
(ps) 420.0 145.0 172.0 72.7
t
read
,complete
(ps) 208.8 27.3 18.2 5.11
relative
t
read
,complete
(%) 49.6 18.8 10.6 7.0
8.4.2.1 Impact of Line Width Roughness
In addition from the investigations done previously, the point of interest was set on the impact of line
width roughness on the behavior of 6-T SRAM cells. LWR already is a big problem device engineers
have to deal with. LWR can be classied as Within-Die variations. They differently inuence every sin-
gle transistor on a die [104, 113]. In the previous section, the electrical stability of 6-T SRAM against
(a) (b)
Figure 8.16 Static noise margin and read delay behavior under the impact of lithography resulted gate length
variations: (a) Static noise margin behavior at uctuating gate length; (b) Read delay behavior at uctuating gate
length
(a) (b)
Figure 8.17 Modeling line width roughness for 6-T SRAM cells: (a) LWR of poly gate lines in 6-T SRAM
cells [10]; (b) Modeled LWR used in this work
variations of the physical gate length could be demonstrated to be very low. Therefore, it was investi-
gated, how LWR might inuence the electrical behavior of 6-T SRAM cells. Therefore, the SG FDSOI
based SRAM cell was impinged with line width roughness. Figure 8.17(a) shows a typical example of
LWR of poly gate lines in a 6-T SRAM cell. The picture was taken from the literature [10]. The LWR
cause a statistically change of the physical gate length over the whole active regions of the device. To
model the effect, sine functions were used for modeling low frequency LWR . The period, amplitude
and wave length were statistically generated by using random numbers from Gaussian distributions. Fig-
ure 8.17(b) shows the layout of a 6-T SRAM cell including LWR of the poly gate lines, modeled in
this work. After the calculation of the LWR of the poly gate line, the MOSFET widths were separated
into 10 nm parts. For each part, a new physical gate length was calculated by averaging the length of
the poly line within the respective part. Finally, the MOSFETs of the SRAM cell in the SPICE netlist
were separated the same way, by connecting MOSFETs models with an effective width of 10 nm in par-
allel until the original width was reached. After that, the gate length of every single MOSFET device
(a) (b)
Figure 8.18 Impact of LWR on the SNM of a 6-T SRAM cell: (a) Buttery characteristic under the inuence
of LWR; (b) SNM under the inuence of process variations and LWR
was changed by the respective CD calculated from the LWR . Additionally, the process variability com-
pact modeling was separated for every single MOSFET to take the effect of the changing physical gate
length due to LWR for every respective width segment of the layout into account. First of all, thou-
sand variations of LWR at a xed nominal gate length of 20 nm were simulated. Figure 8.18(a) shows
the buttery characteristics of the inner SRAM ip-op, resulted from the LWR simulations. As can be
seen, a slight fan-out of the buttery characteristic can be observed, due to LWR. Furthermore, a small
shift of the intersection from the line through origin can be observed, which indicates asymmetrical be-
havior of the LWR . However, for the xed nominal physical gate length of 20 nm, the shift can more
or less be neglected. This might only become a serious problem, if stronger gate length variations are
assumed. Figure 8.18(b) shows the behavior of the SNM under the inuence of process variations and
LWR. The squares in Fig. 8.18(b) denote the SNM behavior by only taking process variations (L
gate
,
t
body
, T
peak
, N
d,a
) variations into account. The circles in Fig. 8.18(b) denote the SNM behavior,
if process variations and LWR were coupled. Due to the LWR, causes a shift of the roll-off behavior
of the SNM to greater gate lengths was caused, which reduces the SNM value. In other words, the 6-T
SRAM became more unstable against noise due to the impact of LWR. Comparing the relative standard
deviations of the simulation run without LWR and with LWR shows the increase of the standard devia-
tion from 23 % to 24 %, which is not of great amount. However, the most critical effect LWR has on the
SNM denitely is the decrease of the SNM. The mean value of the SNM was decreased from 192.0 mV
to 165.0 mV by LWR (Tab. 8.7) and, therefore, leads to less stability of the SRAM cell.
Table 8.7 Mean values, standard deviations, and rel-
atively standard deviations of the SNM of 6-T SRAM
SNM taking into account LWR
SNM w/o LWR w/ LWR
SNM ,complete
(V) 192.0 165.0
SNM ,complete
(V) 45.3 40.0
relative
SNM ,complete
(%) 23.6 24.2
test
Chapter 9
Conclusions and Outlook
Four CMOS device architectures below 50 nm gate length were evaluated in this thesis by means of
numerical TCAD simulations and compact model SPICE simulations. Conventional planar bulk MOS-
FETs, single gate fully depleted silicon on insulator MOSFETs, double gate fully depleted silicon on
insulator MOSFETs, and three dimensional triple gate FinFETs were compared concerning their poten-
tial use in future CMOS applications. Numerical process simulations were performed to assess process
options for improving the electrical device performance. Numerical device simulations were carried out
to calculate the static and the dynamic electrical performance of CMOS device architectures. SPICE sim-
ulations were used to observe different CMOS device architectures in integrated circuit environments.
The impact of process variations on the electrical performance of CMOS devices was studied using cou-
pled lithography, process, device, and SPICE simulations.
An Advanced Drift-Diffusion (ADD) model to take the effect of quasi-ballistic charge carrier transport
in sub-50 nm gate length MOSFETs into account was presented and was successfully used in numerical
device simulations. A eld dependent description for the saturation velocity was proposed and included
into the device simulation software using a Physical Model Interface. Scattering of charge carriers at
the heavily doped source/drain regions was taken into account by means of self heating. A comparison
of the Advanced Drift-Diffusion model to commercially available Monte Carlo device simulators and
non-commercial multi-subband Monte Carlo device simulators was done. A very good drive current
correlation of CMOS devices with physical gate lengths down to 10 nm calculated by the ADD model
and Monte Carlo simulations was achieved. The electrical behavior of 40 nm gate length and 25 nm gate
length SOI single gate MOSFETs presented in the literature could successfully be reproduced by using
the ADD model in numerical device simulations.
Process options for emerging MOSFET channels with mechanical stress to improve the charge carrier
mobility were assessed. A combination of a so called gate replacement technique, presented in the liter-
ature, and a shallow trench isolation forming process, using densication annealing of the silicon oxide
after chemical mechanical polishing, was found to be very efcient for applying mechanical stress, es-
pecially for silicon on insulator MOSFET devices. A maximum mechanical stress along the channel di-
rection of 1.1 GPa, either tensile or compressive, was simulated by using the gate replacement technique.
The modied STI forming process resulted in tensile stress perpendicular to the channel of 1.4 GPa. Fur-
139
140 9 Conclusions and Outlook
thermore, it was demonstrated in this thesis that a full silicidation of the gate electrode has a negative
impact on the MOSFET performance, as well for NMOS transistors as for PMOS transistors. Simplied
methods for simulating the nal stress distributions resulting from silicidation process steps were devel-
oped for three types of silicides. Thermal expansion coefcients and density change coefcients of nickel
mono-silicide (NiSi), cobalt di-silicide (CoSi
2
), and titanium di-silicide (TiSi
2
) were taken from the lit-
erature and calculated from molecular volume differences, respectively, and included into the process
simulator. Temperature ramps starting from the respective stress relaxation temperatures of the different
silicides were modeled to calculate the nal stress distribution in the silicon after the silicidation process.
A modication of the linear piezo coefcient based model for calculating the impact of high mechanical
stress values above 500 MPa on the hole mobility in <110> silicon channels was presented. A satu-
ration of the mobility enhancement due to high mechanical stress values, which was presented in the
literature, was rendered by using Bolzmanns function to describe the stress dependence of piezo coef-
cients. Device simulations at different mechanical stress values in the range from 5 GPa compressive to
5 GPa tensile mechanical stress were performed using the modied piezo model. A good conformity to
measured and simulated results presented in the literature was achieved using the modied piezo model.
The impact of source/drain Schottky contact resistances will become a serious problem if the CMOS
device dimensions continue to shrink. This was demonstrated by experiments and simulations in this
thesis. Decreasing contact areas, due to decreasing MOSFET dimensions, were found to be primarily
responsible for increasing Schottky contact resistances. The assumption was proven by numerical sim-
ulations and measurements of plain contact pads at decreasing contact areas. Furthermore, the quality
of the simulation model for Schottky contacts used was validated by comparing measurement and sim-
ulation results. It was shown that the contact area can efciently be enlarged, without increasing the
overall MOSFET layout area, by etching trenches into the source/drain regions, followed by a silicida-
tion of the trenches. Additional contact area can be achieved by elevating the source/drain regions, to
increase the etching depth of the trenches and, therefore, the contact area. Furthermore, rapid thermal
annealing (RTA) and millisecond annealing (MSA) schemes can be used to efciently reduce contact
resistances. Due to higher active doping concentration at the Schottky contacts, the contact resistances
can further be reduced by MSA. RTA, MSA, and combinations of both were investigated. A combina-
tion of a spike annealing followed by a ash annealing resulted in the best relation of high active surface
doping concentration at the Schottky contacts and a limited lateral redistribution of the dopants in the
channel of sub-50 nm gate length MOSFETs. To further improve the active doping concentration at the
metal/silicon interface and in particular at the side wall of the contact trenches, spin-on-dopant source or
pre-doped deposited silicon can be used to achieve a homogenous high active doping concentration.
Four CMOS device architectures, conventional bulk MOSFETs, single gate fully depleted silicon on in-
sulator MOSFETs, double gate fully depleted silicon on insulator MOSFETs, and triple gate FinFETs,
were investigated for fullling the requirements of high performance (HP), low operating power (LOP),
and low standby power devices (LSTP) of the 32 nm technology node of the international technology
roadmap for semiconductor ITRS (version 2007). Design rules for SOI devices were drawn, concerning
the relation of the physical gate length to the silicon body thickness and buried oxide thickness, respec-
tively. A relation of 4/1 for L
gate
/t
body
was found to result in the highest I
on
-I
off
relation of single gate
fully depleted SOI devices. The lowest drain induced barrier lowering (DIBL) and subthreshold slope
conditions were simulated by a gate length to buried oxide relation of 2/1. It was shown in this thesis
using the example of high performance devices that the requirements of the ITRS could not be fullled
by any CMOS device architecture investigated in this work, without using channel engineering by me-
chanical stress. Mechanical stress was applied on the transistors by the gate replacement technique and
the post-CMP STI densication process to improve the electron and hole mobility. Particular attention
was set on on-current equalization of NMOS and PMOS transistors to reduce MOSFET layout area. It
was demonstrated that it is possible to achieve the required performance demanded by the ITRS for any
transistor architecture investigated in this work by using mechanical stress, without taking Schottky con-
tact resistances into account. A strong impact of Schottky contact resistances on the overall electrical
MOSFET behavior was observed in case of any CMOS device architecture investigated. Even the use of
contact trenches and spin-on-doping sources to increase the overall contact area and active doping con-
centration at the metal/silicon interface did not lead to the required contact resistance reduction needed to
meet the requirements demanded by the ITRS. No device architecture was fullling all the requirements
of the ITRS if contact resistances for realistic circuit layouts were taken into account, even if mechanical
stress is applied, like demonstrated.
An efcient method for compact modeling of multi-gate transistors by using classical bulk MOSFET
compact models was presented. Asymmetrical behavior of multi-gate MOSFETs was investigated and
extracted from separated gate electrode ramping of the reference TCAD devices and reproduced by
a shunt circuit of the respective MOSFET channel models in SPICE netlists. The interaction of gate
electrodes on the neighboring channels of multi-gate MOSFETs was regarded by a voltage controlled
voltage source connected between the substrates of the MOSFET channel models and the sources. The
voltage controlled voltage source was driven by the gate voltage with a certain gain factor m. The
electrical behavior of multi-gate MOSFETs was reproduced in a very good way using the separated gate
ramping method.
SPICE simulations of four integrated circuit blocks, inverter, seven inverter stages based ring oscillator,
4-bit ripple carry adder, and 6-transistor static random access memory (SRAM) cell were performed
using the four different LSTP CMOS device architectures of the 32 nm technology node of the ITRS.
SPICE parameters of NMOS and PMOS transistors were extracted from TCAD models. The EPFL-EKV
compact model was used for compact modeling of bulk MOSFETs, single gate fully depleted silicon on
insulator MOSFETs, double gate fully depleted silicon on insulator MOSFETs, and triple gate FinFETs.
Static and dynamic circuit SPICE simulations were done to investigate the performance of four CMOS
devices under integrated circuit conditions. Multi-gate SOI MOSFETs showed up several advantages
over single gate SOI and bulk MOSFETs concerning circuit performance and layout area consumption.
Especially triple gate FinFETs based circuit blocks outperformed the switching speed performance and
electrostatic stability of planar devices due to larger effective widths at same layout area consumption of
planar single gate devices, but at high average power consumption. On the other hand, single gate fully
depleted SOI devices based circuit blocks resulted in lowaverage power consumption at high electrostatic
stability, but at low switching speed.
The impact of four different process variations on the electrical performance of the single CMOS devices
and the integrated circuit blocks investigated was studied in this thesis. Coupled lithography, process,
and device simulations were used to observe the impact of lithography parameter uctuations on the
electrical performance of planar CMOS devices. A strong asymmetric probability density function for
the critical dimension of the physical gate length resulting from parameter uctuations of the lithography
process was observed. The asymmetrical CD PDF was directly mirrored on the threshold voltage of
fully depleted single gate and double gate SOI MOSFETs. Lightly doped channels of fully depleted
SOI devices were found to be responsible for direct transmission of the CD behavior under the impact of
lithography parameter uctuations on the threshold voltage. The threshold voltage of bulk MOSFETs, on
the other hand, resulted in a Gaussian distribution under the impact of asymmetrical distributed physical
gate length uctuations. Heavily doped pocket implants in bulk MOSFETs led to a self adjustment of the
threshold voltage at changing gate lengths and, therefore, to a better threshold voltage stability, compared
to fully depleted SOI devices. SPICE simulations were used to investigate the impact of lithography
resulted gate length variations on the electrical behavior of triple gate FinFET transistors. Compact model
parameters were set into dependence on process variations using two dimensional polynomial functions
of second order, linear expressions, and 1/x dependencies. Asymmetrical PDFs of the threshold voltage
under the impact of lithography parameter uctuations were observed in case of triple gate FinFETs,
again due to lightly doped channels.
Four kinds of process variations, uctuations of the physical gate length, body thickness, ash anneal-
ing peak temperature, and surface doping concentration uctuations at the metal/silicon interface, were
applied to the four LSTP CMOS devices of the 32 nm technology node of the ITRS discussed in this the-
sis. The impact of random discrete dopants in the channels of bulk MOSFETs was taken into account
by random Gaussian distributed threshold voltage uctuations. Overall 350000 SPICE simulations were
performed to assess the stability of different CMOS device architectures under the impact of process
variations. Due to threshold voltage self adjusting by heavily pocket implants, bulk MOSFETs resulted
in the most stable threshold voltage and leakage current behavior, compared to SOI devices. On the other
hand, it was shown that a more stable drive current behavior under the impact of process variations can
be achieved if SOI architectures were used, triple gate FinFETs in particular.
The impact of process variations on the performance of four integrated circuit blocks, by using the four
LSTP CMOS devices investigated of the 32 nm technology node of the ITRS, was discussed in this
thesis. Overall 1575000 SPICE simulations were performed to assess the stability of different integrated
circuit blocks based on different CMOS device architectures. The impact of random discrete dopants
in the channel of bulk MOSFETs was taken into account for every single device in bulk MOSFET
based circuit blocks. Single gate fully depleted silicon on insulator MOSFET based inverters showed the
overall highest static performance stability against process variations, whereas triple gate FinFET based
inverters resulted in the most stable dynamic behavior. The seven inverter stages based ring oscillator
was found to be the most stable against process variations if bulk MOSFETs were used, even under the
impact of random discrete dopants, but at low switching frequency. The carry-ag delay and sum signal
delay of 4-bit ripple carry adder again resulted in the highest stability against process variations, if bulk
MOSFETs were used in this circuit scheme, but again at low speed. The only option for achieving high
switching speed at medium process variations stability is the use of triple gate FinFETs in ring oscillator
and 4-bit ripple carry adder circuit blocks. Finally, it was demonstrated that the use of triple gate FinFET
devices in static random access memory cells is benecial for improving the stability of the static and
dynamic behavior against process variations.
The impact of line width roughness on the static behavior of static random access memory cells was in-
vestigated in this work using single gate fully depleted silicon on insulator MOSFETs. Low frequency
line width roughness was modeled using sine functions with random periods, frequencies, and ampli-
tudes. The average physical gate length was calculated over 10 nm wide ranges of the active MOSFET
regions in the circuit. 36 MOSFET models were used in the SPICE netlist of the SRAM cell using in-
dividual model cards to take the impact of line width roughness into account. It was demonstrated that
LWR only has a small impact on the static behavior of the inner SRAM ip-op, if a xed initial gate
length is assumed. At decreasing gate lengths, LWR causes a shift of the roll-off behavior of the static
noise margin to larger physical gate lengths which leads to less stability of the SRAM cell against further
process variations.
Summing up, it was demonstrated in this thesis that triple gate FinFET MOSFETs exceed the overall
performance of conventional bulk MOSFET, single gate fully depleted silicon on insulator MOSFETs,
and double gate fully depleted silicon on insulator devices in general. Due to larger effective widths,
higher switching speeds of integrated circuits were achieved if triple gate FinFET transistors were used
at high stable static electrical behavior and minimum layout area consumption compared to conventional
bulk MOSFETs and planar SOI transistors. But, higher average power consumption, compared to planar
SOI devices, and less stability against process variability, compared to conventional bulk MOSFETs,
have to be accepted by using triple gate FinFET MOSFETs in integrated circuits. Furthermore, it was
demonstrated that triple gate FinFET transistors are an option for static random access memory cells to
replace bulk MOSFETs. However, only the experiment will prove the results presented in this thesis.
To access several trade-offs, which have to be done in experimental implementations, the impact of
circuit design and interconnect parasitics has to be analyzed carefully for certain technological options
to draw qualitative conclusions about the optimum choice of nano-scaled CMOS devices for certain next
generation CMOS applications.
Chapter 10
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Appendix A
MOSFET Architectures by Comparison:
List of Results
Table A.1 ITRS (version 2007) specications of the 32 nm technology node [9]
HP LOP LSTP
Year of Production 2013 2013 2013
Physical Lgate 13 nm 16 nm 20 nm
Equivalent Oxide Thickness
Extended Planar Bulk 1.1 nm
UTB FD 0.5 nm 0.8 nm 1.2 nm
DG 0.5 nm 0.9 nm 1.3 nm
Supply Voltage V
DD
Extended Planar Bulk 0.95V
UTB FD 0.9 V 0.6 V 0.9 V
DG 0.9 V 0.6 V 0.85 V
Saturation Threshold Voltage
Extended Planar Bulk 547 mV
UTB FD 93 mV 195 mV 399 mV
DG 103 mV 203 mV 362 mV
Source/Drain Subthreshold Off-State Leakage Current
Extended Planar Bulk 3.03E-05 A/m
UTB FD 0.56 A/m 2.02E-02 A/m 3.09E-05 A/m
DG 0.37 A/m 8.61E-03 A/m 2.44E-05 A/m
NMOS Drive Current
Extended Planar Bulk 519 A/m
UTB FD 2109 A/m 747 A/m 669 A/m
DG 2204 A/m 754 A/m 612 A/m
=CV/I: NMOSFET intrinsic delay
Extended Planar Bulk 1.23 ps
UTB FD 0.28 ps 0.53 ps 0.9 ps
DG 0.26 ps 0.53 ps 0.9 ps
155
156 A MOSFET Architectures by Comparison: List of Results
A.1 High Performance Devices
Table A.2 Geometrical dimensions, doping parameters and mechanical stress values of HP devices
Device L
gate
t
ox
t
body
t
BOX
N
2ext
E
ext

XX

YY
Bulk NMOS 13 nm 0.5 nm - - 4 10
14
cm
2
1.0 keV 1.0 GPa 1.0 GPa
Bulk PMOS 13 nm 0.5 nm - - 1 10
15
cm
2
0.4 keV -0.6 GPa 1.0 GPa
SG FDSOI NMOS 13 nm 0.5 nm 3 nm 6.5 nm 4 10
14
cm
2
1.0 keV 1.2 MPa 0.0 GPa
SG FDSOI PMOS 13 nm 0.5 nm 3 nm 6.5 nm 1 10
14
cm
2
0.2 keV -0.9 GPa 1.0 GPa
DG FDSOI 13 nm 0.6 nm 6.5 nm 13 nm 4 10
14
cm
2
2.0 keV 1.1 GPa 0.0 GPa
DG FDSOI 13 nm 0.6 nm 6.5 nm 13 nm 4 10
14
cm
2
0.3 keV -0.8 GPa 0.0 GPa
TG FinFET NMOS 13 nm 0.5 nm 6.5 nm 13 nm 4 10
14
cm
2
3.5 keV 1 GPa 1 GPa
TG FinFET PMOS 13 nm 0.5 nm 6.5 nm 13 nm 1 10
14
cm
2
0.6 keV -0.8 GPa 1.0 GPa
Table A.3 High performance (HP) MOSFET parameters
Device V
th,high
(mV) DIBL (mV/V) SSlope (mV/dec) I
on
(mA/m) I
off
(nA/m)
w/o mechanical stress and contact resistances
Bulk NMOS 119.0 90.5 90.7 1.57 14.1
Bulk PMOS 235.0 80.0 81.6 0.81 15.1
SG FDSOI NMOS 121.0 63.5 77.0 1.88 237.0
SG FDSOI PMOS 131.0 52.9 74.3 0.80 177.9
DG FDSOI NMOS 136.0 75.3 73.7 1.88 65.8
DG FDSOI PMOS 110.0 61.2 73.3 1.08 147.9
TG FinFET NMOS 153.0 70.6 75.5 1.79 97.2
TG FinFET PMOS 185.0 55.3 72.0 0.772 34.07
including mechanical stress; w/o contact resistances
Bulk NMOS 0.74 88.2 93.7 1.9 45.4
Bulk PMOS 195.0 74.11 81.6 2.06 38.1
SG FDSOI NMOS 88.0 65.8 79.3 2.34 650.4
SG FDSOI PMOS 110.0 49.4 72.9 2.0 266.7
DG FDSOI NMOS 104.0 72.9 74.8 2.21 177.8
DG FDSOI PMOS 81.0 60.0 73.4 2.37 443.8
TG FinFET NMOS 115.0 69.4 77.5 2.2 316.2
TG FinFET PMOS 148.0 52.9 72.0 1.94 86.2
including mechanical stress and contact resistances
Bulk NMOS 0.74 88.2 93.7 1.15 45.4
Bulk PMOS 195.0 74.11 81.6 1.3 38.1
SG FDSOI NMOS 88.0 65.8 79.3 1.47 650.4
SG FDSOI PMOS 110.0 49.4 72.9 1.19 266.4
DG FDSOI NMOS 104.0 72.9 74.8 1.10 177.8
DG FDSOI PMOS 81.0 60.0 73.4 1.175 443.8
TG FinFET NMOS 115.0 69.4 77.5 1.36 316.2
TG FinFET PMOS 148.0 52.9 72.0 0.58 86.2
A.2 Low Operating Power Devices 157
A.2 Low Operating Power Devices
Table A.4 Geometrical dimensions, doping parameters and mechanical stress values of LOP devices
Device L
gate
t
ox
t
body
t
BOX
N
2ext
E
ext

XX

YY
Bulk NMOS 16 nm 0.8 nm - - 4 10
14
cm
2
1.2 keV 1.0 GPa 0.0 GPa
Bulk PMOS 16 nm 0.8 nm - - 1 10
15
cm
2
0.4 keV -0.8 GPa 1.0 GPa
SG FDSOI NMOS 16 nm 0.8 nm 4 nm 8 nm 1 10
14
cm
2
1.0 keV 1.1 GPa 1.4 GPa
SG FDSOI PMOS 16 nm 0.8 nm 4 nm 8 nm 1 10
14
cm
2
0.2 keV -1.0 GPa 1.4 GPa
DG FDSOI 16 nm 0.9 nm 8 nm 16 nm 4 10
14
cm
2
2.0 keV 1.2 GPa 0.0 GPa
14
cm
2
0.3 keV -0.8 GPa 0.0 GPa
TG FinFET NMOS 16 nm 0.8 nm 8 nm 16 nm 5 10
14
cm
2
4.5 keV 1.0 GPa 1.0 GPa
TG FinFET PMOS 16 nm 0.8 nm 8 nm 16 nm 5 10
13
cm
2
0.5 keV -1.0 GPa 1.0 GPa
Table A.5 Low operating power (LOP) MOSFET parameters
Device V
th,high
on
(mA/m) I
off
(nA/m)
Bulk NMOS 228.0 130.9 93.5 0.378 28.3
Bulk PMOS 291.0 121.8 87.3 0.17 4.5
SG FDSOI NMOS 266.0 80.0 76.1 0.38 2.59
SG FDSOI PMOS 249.0 83.6 74.8 0.21 5.05
DG FDSOI NMOS 216.0 118.2 79.4 0.414 8.32
DG FDSOI PMOS 215.0 89.1 71.8 0.205 6.4
TG FinFET NMOS 292.0 143.6 77.3 0.281 1.93
TG FinFET PMOS 299.0 67.3 70.0 0.163 0.76
Bulk NMOS 206.0 130.9 93.5 0.47 47.3
Bulk PMOS 265.0 107.3 87.0 0.41 7.17
SG FDSOI NMOS 174.0 81.8 77.3 0.643 7.35
SG FDSOI PMOS 227.0 72.7 74.1 0.643 6.85
DG FDSOI NMOS 187.0 116.4 79.6 0.525 18.04
DG FDSOI PMOS 205.0 80.0 70.8 0.48 6.4
TG FinFET NMOS 252.0 140.0 78.2 0.41 6.10
TG FinFET PMOS 256.0 63.6 70.0 0.475 2.21
Bulk NMOS 206.0 130.9 93.5 0.399 47.3
Bulk PMOS 265.0 107.3 87.0 0.31 7.17
SG FDSOI NMOS 174.0 81.9 77.3 0.37 7.35
SG FDSOI PMOS 227.0 72.7 74.1 0.46 6.85
DG FDSOI NMOS 187.0 116.4 79.6 0.37 18.04
DG FDSOI PMOS 205.0 80.0 70.8 0.37 6.4
TG FinFET NMOS 252.0 140.0 78.2 0.30 6.10
TG FinFET PMOS 256.0 63.6 70.0 0.135 6.8
158 A MOSFET Architectures by Comparison: List of Results
A.3 Low Standby Power Devices
Table A.6 Geometrical dimensions, doping parameters and mechanical stress values of LSTP devices
Device L
gate
t
ox
t
body
t
BOX
N
2ext
E
ext

XX

YY
Bulk NMOS 20 nm 1.2 nm - - 5 10
14
cm
2
1.8 keV 1.0 GPa 0.0 GPa
Bulk PMOS 20 nm 1.2 nm - - 1 10
15
cm
2
0.7 keV -1.0 GPa 1.0 GPa
SG FDSOI NMOS 20 nm 1.2 nm 5 nm 10 nm 4 10
14
cm
2
1.0 keV 1.1 GPa 0.0 GPa
SG FDSOI PMOS 20 nm 1.2 nm 5 nm 10 nm 1 10
14
cm
2
0.5 keV -1.0 GPa 1.0 GPa
14
cm
2
2.4 keV 1.0 GPa 0.0 GPa
14
cm
2
0.4 keV -1.1 GPa 1.3 GPa
TG FinFET NMOS 20 nm 1.2 nm 10 nm 20 nm 4 10
14
cm
2
5 keV 1.0 GPa 1.0 GPa
TG FinFET PMOS 20 nm 1.2 nm 10 nm 20 nm 1 10
14
cm
2
0.7 keV -1.0 GPa 1.0 GPa
Table A.7 Low standby power (LSTP) MOSFET parameters
Device V
th,high
on
(mA/m) I
off
(nA/m)
Bulk NMOS 263.0 129.4 110.1 0.48 23.9
Bulk PMOS 273.0 160.0 106.1 0.382 17.5
SG FDSOI NMOS 385.0 88.2 82.0 0.622 0.0097
SG FDSOI PMOS 404.0 85.8 76.7 0.264 0.0059
DG FDSOI NMOS 358.0 60.7 70.0 0.91 0.0066
DG FDSOI PMOS 368.0 53.7 70.0 0.36 0.0044
TG FinFET NMOS 348.0 71.8 74.7 0.66 0.22
TG FinFET PMOS 391.0 50.5 70.0 0.23 0.035
Bulk NMOS 215.0 131.7 113.6 0.612 72.1
Bulk PMOS 239.0 147.0 102.7 1.03 23.0
SG FDSOI NMOS 363.0 88.2 82.0 0.68 0.030
SG FDSOI PMOS 394.0 74.1 75.9 0.67 0.0055
DG FDSOI NMOS 306.0 62.5 70.0 1.2 0.040
DG FDSOI PMOS 315.0 55.0 70.0 1.4 0.013
TG FinFET NMOS 306.0 72.9 74.9 0.846 0.72
TG FinFET PMOS 346.0 50.0 70.0 0.66 0.10
Bulk NMOS 215.0 131.7 0.612 0.512 72.1
Bulk PMOS 239.0 147.0 102.7 630.2 23.0
SG FDSOI NMOS 363.0 88.2 82.0 0.56 0.030
SG FDSOI PMOS 394.0 74.1 75.9 0.50 0.0055
DG FDSOI NMOS 306.0 62.5 70.0 0.97 0.04
DG FDSOI PMOS 315.0 55.0 70.0 0.51 0.013
TG FinFET NMOS 306.0 72.9 74.9 0.62 0.72
TG FinFET PMOS 346.0 50.0 70.0 0.611 0.10
Appendix B
Own Publications
C. Kampen, A. Burenkov, and J. Lorenz. "On the Inuence of Flash Peak Temperature Variations
on Schottky Contact Resistances of 6-T SRAM cells". In ESSDERC, IEEE, September 2010, pages
289292.
C. Kampen, P. Evanschitzky, A. Burenkov, and J. Lorenz. "Lithography Induced Layout Variations in
6-T SRAM Cells". In SISPAD, IEEE, September 2010, pages 149152.
C. Kampen, A. Burenkov, D. Kunder, E. Br, and J. Lorenz. "Determination of Across-Wafer Varia-
tions of Transistor Characteristics by Coupling Equipment Simulation with Technology Computer-Aided
Design (TCAD)." In 1st International Conference on Multiphysics Simulation, 2010.
C. Kampen, A. Burenkov, J. Lorenz, and H. Ryssel. "FD SOI MOSFET Compact Modeling Including
Process Variations." In ULIS Conference, IEEE, March 2010, pages 273276.
C. Kampen and A. Burenkov. "Elektrische Kontaktierung von Halbleiter-Bauelementen mit geringem
Kontaktwiderstand." Announcement of an invention, Application number PCT/DE2008/000331, June
2009.
C. Kampen, A. Burenkov, J. Lorenz, and H. Ryssel. "Simulation assessment of process options for
advanced CMOS devices". In ULIS Conference, IEEE, March 2009, pages 273276.
C. Kampen, A. Burenkov, J. Lorenz, H. Ryssel, V. Aubry-Fortuna, and A. Bournel. "An application
driven improvement of the drift diffusion model for carrier transport in decanano-scaled CMOS devices."
In IEEE Transactions on Electron Devices, Vol. 55, No. 11, pages 32273235, November 2008.
C. Kampen, T. Fhner, A. Burenkov, A. Erdmann, J. Lorenz, and H. Ryssel. "On the stability of fully
depleted SOI MOSFETs under lithography process variations." In ESSDERC, IEEE, September 2008,
pages 194197.
C. Kampen, A. Martinez-Limia, P. Pichler, A. Burenkov, J. Lorenz, and H. Ryssel. "Advanced annealing
strategies for the 32nm node." In SISPAD, IEEE, September 2008, pages 317320.
159
160 B Own Publications
C. Kampen, A. Burenkov, J. Lorenz, and H. Ryssel. Alternative source/drain contact-pad architectures
for contact resistance improvement in decanano-scaled CMOS devices. In ULIS Conference, IEEE,
March 2008, pages 179182.
A. Burenkov, C. Kampen, E. Br, and J. Lorenz. "Impact of Technological Options for 22 nm SOI
CMOS Transistors on IC Performance." In EuroSOI Workshop, January 2010.
R. Jancke, C. Kampen, O. Kilic, J. Lorenz. "Hierachischer Ansatz fr die Monte-Carlo-Simulation
komplexer Mixed-Signal-Schaltungen." Accepted for Analog 2010 Conference
P. Pichler, A. Burenkov, J. Lorenz, C. Kampen, and L. Frey. "Future Challenges in CMOS Process
Modelling." to be published in Journal of Thin Solid Films
J. Lorenz, C. Kampen, A. Burenkov, and T. Fhner. "Impact of lithography variations on advanced
CMOS devices." In VLSI Technology, Systems, and Applications, VLSI-TSA, IEEE, April 2009,
pages 1718.
A. Burenkov, C. Kampen, J. Lorenz, and H. Ryssel. "Pre-silicon SPICE modeling of nano-scaled SOI
MOSFETs." In ULIS Conference, IEEE, March 2008, pages 215218.
A. Burenkov, C. Kampen, E. Br, J. Lorenz, and H. Ryssel. "Application-driven simulation of nanoscaled
CMOS transistors and circuits." In Journal of computational and theoretical nanoscience, Vol. 5, No. 6,
pages 1170-1182, 2008
T. Fhner, C. Kampen, I. Kodrasi, A. Burenkov, and A. Erdmann. "A Simulation Study on the Im-
pact of Lithographic Process Variations on CMOS Device Performance." In Society of Photo-Optical
Instrumentation Engineers SPIE, paper 692453, February 2008
A. Burenkov, C. Kampen, J. Lorenz, and H. Ryssel. "Physical based simulation of fully depleted SOI
MOS transistors at nanometer gate lengths." In ICMNE, October 2007.
P. Pichler, A. Martinez-Limia, C. Kampen, A. Burenkov, J. Schermer, S. Paul, W. Lerch, J. Gelpey,
S. McCoy, H. Kheyrandish, A. Pakfar, C. Tavernier, and D. Bolze. "Process models for advanced anneal-
ing schemes and their use in device simulation." In 8th International Workshop on Junction Technology,
IWJT 2008, pages 120-125, May 2008
Appendix C
Copyright Agreements
Figure 1.1(b) was taken from [3] (Fig.2) considering the copyright agreements of IEEE.
Figure 1.2(a) was taken from Intel ofcial webpage considering the educational copyright agreements of
Intel Corporation.
Figure 2.1(a) was taken from [10] (Fig.1) considering the copyright agreements of IEEE.
Figure 2.1(c) was taken from [22] (Fig.1) considering the copyright agreements of IEEE.
Figure 2.1(d) was taken from [23] (Fig.1) considering the copyright agreements of IEEE.
Figure 6.1(c) was taken from [22] (Fig.1) considering the copyright agreements of IEEE.
Figure 6.1(d) was taken from [23] (Fig.1) considering the copyright agreements of IEEE.
Figure 8.1 was taken from [103] (Fig.2) considering the copyright agreements of IEEE.
161
162 C Copyright Agreements
List of Figures
1.1 Transistor evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Integrated circuit evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 CMOS device architectures to be investigated: (a) Bulk MOSFET [10]; (b) SG FDSOI
MOSFET [14]; (c) DG SOI MOSFET [22]; (d) FinFET [23] . . . . . . . . . . . . . . . 6
2.2 Simulation ow used in this work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Temperature proles vs. the annealing time of a spike annealing (dashed lines) and a
ash annealing (solid line) [42] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Comparison between HD, MC, DD simulations, and experimental results . . . . . . . . 22
3.2 Thermal resistance network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Comparison between the default DD model (dashed lines), MC simulations (circles) and
the ADD model suggested in this work (stars): (a) Constant scaling scenario: NMOS; (b)
Constant scaling scenario: PMOS; (c) Constant V
DD
scenario: NMOS; (d) Constant V
DD
scenario: PMOS; (e) ITRS scaling scenario: NMOS; (f) ITRS scaling scenario: PMOS . 29
3.4 Comparison of the ADD model to experimental results: 40 nm gate length FDSOI [3];
squares: experiment at V
drain
=0.1 V and 1.25 V; solid lines: simulation; (a) Transfer
characteristic linearly scaled; (b) Transfer characteristic semi-logarithmic scaled . . . . . 30
3.5 Comparison of the ADD model to the measured output characteristic: 40 nm gate length
FDSOI [3]; squares: experiment at V
drain
=0.1 V and 1.25 V; solid lines: simulation . . . 31
3.6 Mechanical stress in the channel region of the SOI MOSFET [18] after silicidation, cal-
culated by process simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
163
164 List of Figures
3.7 Comparison of the ADD model to experimental results: 25 nm gate length FDSOI [18];
squares: experiment at V
drain
=0.05 V and 1.1 V; solid lines: simulation; (a) Transfer
characteristic linearly scaled; (b) Transfer characteristic semi-logarithmic scaled . . . . . 32
3.8 Decreasing low eld mobility at decreasing channel lengths . . . . . . . . . . . . . . . . 33
3.9 Effect of increasing lateral electric eld at decreasing channel lengths: (a) Average lat-
eral eld over the physical channel length; (b) Low eld average apparent mobility as a
function of the lateral electric eld . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Silicidation resulted lm stress by using the density change method and material specic
parameters listed in Tab. 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 Simulated silicidation resulted stress distribution in FDSOI MOSFETs for different sili-
cides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3 Distribution of mechanical stress along the channel direction induced by tensile and com-
pressive CESL: (a) Tensile CESL with intrinsic stress of 800 MPa; (b) Tensile CESL with
intrinsic stress of 2500 MPa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4 Mechanical stress along the channel direction induced by tensile and compressive CESL
and the gate replacement technique [83]: (a) Tensile CESL with intrinsic stress of
800 MPa, (b) Tensile CESL with intrinsic stress of 2500 MPa . . . . . . . . . . . . . . . 44
4.5 Comparison of the low eld mobility enhancement calculated by the modied piezo
coefcient based model to results from the literature and the Intel model: (a) Stress
along the xx direction (high stress values); (b) Stress along the xx-direction (low stress
values); (c) Stress along the yy-direction (low stress values); (d) Biaxial stress (low stress
values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6 Mobility enhancement at high stress values for uniaxial longitudinal, transversal and
biaxial stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7 Threshold voltage shift due to applied stress calculated by the modied piezo model . . . 49
5.1 (a) Contact resistances behavior recommended by the ITRS [9]; (b) Contact resistances
behavior calculated using Eq. (5.1) with constant
c
. . . . . . . . . . . . . . . . . . . . 51
5.2 Process ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3 (a) Doping concentrations of the three regions at the frontside of the wafer; (b) Doping
concentration at the backside of the wafer . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.4 Measurement and simulation results of the 1 20 cm
3
doped regions: (a) I-V character-
istics for different pad sizes; (b) R
co
(A
co
) dependence (line-symbols: experiment, line:
simulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
List of Figures 165
5.5 Area achievement by using contact plug architectures; (a) Plain contact area; (b) Contact
trench; (c) Contact plug principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.6 Contact resistance behavior for different doping concentrations by scaling down the con-
tact area; dashed lines and open symbols: plain contact pad; solid lines and lled sym-
bols: trench architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.7 MOSFET behavior by using different contact realizations: (a) Transconductance of the
NMOS at low drain voltages; (b) Transconductance of the PMOS at low drain voltages;
(c) Output characteristic of the NMOS at high gate voltages; (d) Output characteristic of
the PMOS at high gate voltages; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.8 Doping strategies for the trench and the plug architecture: (a) Trench architecture im-
planted and annealed; (b) Plug architecture implanted and annealed; (c) Trench doped
by spin-on-dopant source; (d) Plug doped by spin-on-dopant source . . . . . . . . . . . 58
6.1 CMOS device architectures to be investigated: (a) Bulk MOSFET [10]; (b) SG FDSOI
MOSFET [14]; (c) DG FDSOI SOI MOSFET [22]; (d) FinFET [23] . . . . . . . . . . . 61
6.2 2D device architectures after 2D process simulation . . . . . . . . . . . . . . . . . . . . 64
6.3 (a) 3D FinFET architecture after CAD; (b) 3D FinFET architecture after process simulation 65
6.4 I
on
-I
off
relation for different silicon body thicknesses and validation of the Lombardi
model: (a) I
on
(t
body
/L
gate
) and I
off
(t
body
/L
gate
); (b) Comparison between the model of
Esseni for SOI MOSFETs [93] and the conventional Lombardi model [47] . . . . . . . . 70
6.5 DIBL and SSlope behavior for different buried oxide thicknesses . . . . . . . . . . . . . 71
6.6 Transfer and output characteristic of the HP bulk MOSFET: (a) Transfer characteristic;
(b) Output characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.7 Transfer and output characteristic of the HP SG FDSOI MOSFET: (a) Transfer charac-
teristic; (b) Output characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.8 Transfer and output characteristic of the HP DG FDSOI MOSFET: (a) Transfer charac-
teristic; (b) Output characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.9 Transfer and output characteristic of the HP TG FinFET: (a) Transfer characteristic; (b)
Output characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.10 Effective
eff
and eld effect
fef
mobility of four MOSFET architectures investigated:
(a) Bulk MOSFET; (b) SG FDSOI ; (c) DG FDSOI ; (d) TG FinFET . . . . . . . . . . . 74
6.11 I
on
-I
off
and CV/I characteristic of the HP bulk MOSFET: (a) I
on
-I
off
characteristic; (b)
CV/I characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.12 I
on
-I
off
and CV/I of the HP SG FDSOI MOSFET: (a) I
on
-I
off
characteristic; (b) CV/I
characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
166 List of Figures
6.13 I
on
-I
off
and CV/I characteristic of the HP DG FDSOI MOSFET: (a) I
on
-I
off
character-
istic; (b) CV/I characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.14 I
on
-I
off
and CV/I characteristic of the HP TG FinFET :(a) I
on
-I
off
characteristic; (b)
CV/I characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.15 Comparison of the I
on
-I
off
and CV/I characteristic of the four NMOS device architec-
tures investigated: (a) I
on
-I
off
characteristic; (b) CV/I characteristic . . . . . . . . . . . 77
6.16 Process options for creating mechanical stress: (a) Gate replacement technique to in-
crease stress in the channel region [83]; (b) Post-densication STI forming process for
achieving tensile stress perpendicular to the channel [82] . . . . . . . . . . . . . . . . . 78
6.17 I
on
-I
off
and CV/I characteristic of the HP bulk MOSFET including mechanical stress:
(a) I
on
-I
off
characteristic; (b) CV/I characteristic . . . . . . . . . . . . . . . . . . . . . 79
6.18 I
on
-I
off
and CV/I of the HP SG FDSOI MOSFET including mechanical stress: (a) I
on
-
I
off
characteristic; (b) CV/I characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.19 I
on
-I
off
and CV/I characteristic of the HP DG FDSOI MOSFET including mechanical
stress: (a) I
on
-I
off
characteristic; (b) CV/I characteristic . . . . . . . . . . . . . . . . . 80
6.20 I
on
-I
off
and CV/I characteristic of the HP TG FinFET including mechanical stress: (a)
I
on
-I
off
characteristic; (b) CV/I characteristic . . . . . . . . . . . . . . . . . . . . . . . 80
6.21 Comparison of the I
on
-I
off
and CV/I characteristic of the four NMOS device archi-
tectures investigated including mechanical stress: (a) I
on
-I
off
characteristic; (b) CV/I
characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.22 I
on
-I
off
and CV/I characteristic of the HP bulk NMOSFET including mechanical stress
and contact resistances: (a) I
on
-I
off
characteristic; (b) CV/I characteristic . . . . . . . . 82
6.23 I
on
-I
off
and CV/I of the HP SG FDSOI NMOSFET including mechanical stress and
on
-I
off
characteristic; (b) CV/I characteristic . . . . . . . . . . 82
6.24 I
on
-I
off
and CV/I characteristic of the HP DG FDSOI NMOSFET including mechanical
stress and contact resistances: (a) I
on
-I
off
characteristic; (b) CV/I characteristic . . . . . 83
6.25 Structures used for calculating contact resistances of the TG FinFET NMOS and PMOS
devices: (a) Plain contact pad implanted; (b) Trench contact with doping glass doping . . 83
6.26 I
on
-I
off
and CV/I characteristic of the HP TG FinFET including mechanical stress and
on
-I
off
characteristic; (b) CV/I characteristic . . . . . . . . . . 84
6.27 Comparison of the static electrical behavior of the four high performance NMOSFET
architectures investigated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.28 Comparison of the static electrical behavior of the four low operating power NMOSFET
List of Figures 167
6.29 Comparison of the static electrical behavior of the four low standby power NMOSFET
6.30 Comparison of the dynamic electrical behavior of the four high performance NMOSFET
6.31 Comparison of the dynamic electrical behavior of the four low operating power NMOS-
FET architectures investigated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.32 Comparison of the dynamic electrical behavior of the four low standby power NMOS-
FET architectures investigated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.1 SPICE parameter extraction results of a 32 nmbulk MOSFET: (a) Transfer characteristic;
(b) Output characteristic; (c) Gate capacitance . . . . . . . . . . . . . . . . . . . . . . . 93
7.2 SPICE parameter extraction results of a 32 nm Single Gate FDSOI MOSFET: (a) Trans-
fer characteristic; (b) Output characteristic; (c) Gate capacitance . . . . . . . . . . . . . 94
7.3 Double gate FDSOI TCAD simulation method for SPICE modeling: (a) TCAD model
with non-uniform doping proles; (b) Transfer characteristic of ramping single gate elec-
trodes (solid line: top-gate; dashed line: back-gate) and the sum of top-gate and back-
gate simulation (circles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.4 Circuit scheme of the double gate FDSOI model including voltage controlled voltage
source: (a) Circuit scheme; (b) Impact of the voltage controlled voltage source on transfer
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.5 SPICE parameter extraction results of a 32 nm double gate FD SOi MOSFET: (a) Trans-
fer characteristic; (b) Output characteristic; (c) Gate capacitance . . . . . . . . . . . . . 97
7.6 TCAD simulation results of ramping single gate electrodes of the triple gate FinFET: (a)
Doping overlap at the different channels; (b) Transfer characteristic of the NMOS (line:
front-gate; dashed line: back-gate; dashed dotted line:top-gate; circles:sum of three;
squares:intrinsic behavior) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.7 Compact model scheme of the TG FinFET . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.8 SPICE parameter extraction results of a 32 nm triple gate FinFET: (a) Transfer charac-
teristic; (b) Output characteristic; (c) Gate capacitance . . . . . . . . . . . . . . . . . . 100
7.9 Schematic draw of the inverter circuit: (a) Single gate devices; (b) Double gate devices . 101
7.10 Static and dynamic behavior of the simulated inverter stage using four different CMOS
device architectures with a physical gate length of 32 nm: (a) Static behavior; (b) Dy-
namic behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
168 List of Figures
7.11 Static and dynamic behavior of the simulated inverter stage using four different CMOS
device architectures with a physical gate length of 20 nm including mechanical stress and
contact resistances: (a) Static behavior; (b) Dynamic behavior . . . . . . . . . . . . . . 104
7.12 Schematic draw of the seven stage ring oscillator used in this work . . . . . . . . . . . . 105
7.13 Input and output signal of the rst inverter stage i1 of the seven stage ring oscillator . . . 105
7.14 Circuit diagram of one full adder stage used in this work . . . . . . . . . . . . . . . . . 107
7.15 Schematic of the 4-bit ripple carry adder circuit . . . . . . . . . . . . . . . . . . . . . . 107
7.16 4-bit ripple carry adder simulation results using four different CMOS device architec-
tures: (a) Carry-ag signal results; (b) S
3
signal results . . . . . . . . . . . . . . . . . . 108
7.17 Schematic of a 6-T SRAM cell circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.18 6-T SRAM cell HOLD operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.19 6-T SRAM cell READ operation mode: (a) Static behavior; (b) Dynamic behavior . . . 110
7.20 6-T SRAM cell WRITE operation mode: (a) Static behavior; (b) Dynamic behavior . . . 111
8.1 Challegenes for future CMOS devices: variability is one of the most important issue to
be solved [103] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.2 Lithography simulation process setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.3 Simulation ow chart for coupled lithography and device simulation (CoLiDe) [107] . . 116
8.4 Impact of lithography parameter uctuations on the critical dimension: (a) Gaussian PDF
of the projector defocus; (b) Generalized extreme values PDF of the CD; (c) Bossung plot
at 0.32 threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8.5 PDF of the threshold voltages under lithography variations: (a) Bulk MOSFET: normal
PDF; (b) SG FDSOI: GEV PDF; (c) DG FDSOI: GEV PDF . . . . . . . . . . . . . . . 118
8.6 Compact modeling analysis for V
th
(L
gate
,t
body
) dependence: (a) I
on
-I
off
characteristic;
(b) V
th
(L
gate
,t
body
) dependence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
8.7 Electrical behavior of four different CMOS device architectures with an nominal physical
gate length of 32 nm under lithography induced gate length variability: (a) PDF of V
th
of the TG FinFET; (b) V
th
behavior under lithography induced gate length variations; (c)
I
on
-I
off
clouds under lithography induced gate length variations . . . . . . . . . . . . . . 121
8.8 (a) Fit function for ash temperature prole; (b) Simulated peak temperature variations . 122
8.9 (a) Compact modeling analysis for R
co
(T
peak
,N
2
) dependency compact modeling; (b)
SPICE simulation results compared to TCAD simulation results for I
on
-I
off
. . . . . . . 123
List of Figures 169
8.10 Impact of gate length variations on the electrical performance of four different CMOS
device architectures: (a) Threshold voltage behavior; (b) I
on
-I
off
relation . . . . . . . . . 124
8.11 Threshold voltage behavior under process variations ((L
gate
, t
body
, T
peak
, N
d,a
) . 126
8.12 Inuence of variability on inverter performance using four different device architectures:
(a) Gate length, body thickness, temperature and doping concentration variability impact
on inverter threshold V
M
; (b) Gate length variability impact on propagation delay . . . . 130
8.13 Inverter threshold behavior under process variations using four different CMOS device
architectures (bulk transistors are shown at t
body
/t
body,nominal
= 1) . . . . . . . . . . . . 130
8.14 Inuence of variability on ring oscillator frequency . . . . . . . . . . . . . . . . . . . . 132
8.15 Impact of gate length uctuations on 4-bit ripple carry adder performance: (a) Impact of
gate length uctuations on carry ag delay; (b) Impact of gate length uctuations on sum
signal delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8.16 Static noise margin and read delay behavior under the impact of lithography resulted gate
length variations: (a) Static noise margin behavior at uctuating gate length; (b) Read
delay behavior at uctuating gate length . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.17 Modeling line width roughness for 6-T SRAM cells: (a) LWR of poly gate lines in 6-T
SRAM cells [10]; (b) Modeled LWR used in this work . . . . . . . . . . . . . . . . . . 136
8.18 Impact of LWR on the SNM of a 6-T SRAM cell: (a) Buttery characteristic under the
inuence of LWR; (b) SNM under the inuence of process variations and LWR . . . . . 136
170 List of Figures
List of Tables
3.1 Device dimensions for different scaling scenarios . . . . . . . . . . . . . . . . . . . . . 28
4.1 Lattice constants (a, b, c), lattice types, number of atoms in one crystalline cell A,
atomic volumes V
x
(single materials), and molecular volumes (compounds) [78] . . . . . 39
4.2 Material parameters for NiSi, CoSi
2
, and TiSi
2
[80] . . . . . . . . . . . . . . . . . . . . 40
4.3 Impact of silicidation induced stress on the on-currents of NMOS and PMOS single gate
fully depleted silicon on insulator transistors;
X(V
DD
= 1.1 V ) = I
on,silicide
/I
on,default
. . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4 Average mechanical stress along the channel direction induced by contact etch stop lay-
ers and the additional gate replacement technique [83] . . . . . . . . . . . . . . . . . . . 42
4.5 Piezo coefcients [30, 77] and model parameters for the uniaxial and biaxial mechan-
ical stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6 Low eld mobility enhancement and threshold voltage shift at 5 GPa stress . . . . . . . . 49
5.1 Implantation conditions for optimizing surface doping concentration of contact trench
and contact plug architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1 Comparison of geometrical dimensions of the investigated MOSFET architectures based
on denitions from the 2007 ITRS for the 32 nm technology node (References can be
found in the ITRS Process Integration, Devices, and Structures chapter [9]) . . . . . . . 62
7.1 Compact model parameters of the 32 nm bulk and SG FDSOI NMOS transistors. The
notation of the EKV parameter le was used to directly transfer the parameters into an
EKV modelcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.2 Static and dynamic behavior of the inverter stage using four different MOSFET architec-
tures and two different physical gate lengths . . . . . . . . . . . . . . . . . . . . . . . . 104
7.3 Results of the ring oscillator simulation using four different CMOS device architectures . 106
171
172 List of Tables
7.4 4-bit ripple carry adder simulation results . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.5 Performance of the 6-T SRAM cell using four different CMOS architecuters . . . . . . . 112
8.1 Mean values, standard deviations and relatively standard deviations of electrical perfor-
mance parameters of four different CMOS NMOS device architectures . . . . . . . . . . 127
8.2 Mean values, standard deviations, and relatively standard deviations of electrical perfor-
mance parameters of four different CMOS PMOS device architectures . . . . . . . . . . 128
8.3 Mean values, standard deviations, and relatively standard deviations of inverter stage
performance parameters based on four different CMOS device architectures . . . . . . . 131
8.4 Mean values, standard deviations, and relatively standard deviations of seven stage ring
oscillator frequency based on four different CMOS device architectures . . . . . . . . . 132
8.5 Mean values, standard deviations, and relatively standard deviations of 4-bit ripple carry
adder performance parameters based on four different CMOS device architectures . . . . 134
8.6 Mean values, standard deviations, and relatively standard deviations of 6-T SRAM cell
performance parameters for four different CMOS device architectures . . . . . . . . . . 135
8.7 Mean values, standard deviations, and relatively standard deviations of the SNM of 6-T
SRAM SNM taking into account LWR . . . . . . . . . . . . . . . . . . . . . . . . . . 137
A.1 ITRS (version 2007) specications of the 32 nm technology node [9] . . . . . . . . . . . 155
A.2 Geometrical dimensions, doping parameters and mechanical stress values of HP devices 156
A.3 High performance (HP) MOSFET parameters . . . . . . . . . . . . . . . . . . . . . . . 156
A.4 Geometrical dimensions, doping parameters and mechanical stress values of LOP devices 157
A.5 Low operating power (LOP) MOSFET parameters . . . . . . . . . . . . . . . . . . . . . 157
A.6 Geometrical dimensions, doping parameters and mechanical stress values of LSTP devices158
A.7 Low standby power (LSTP) MOSFET parameters . . . . . . . . . . . . . . . . . . . . . 158
List of Symbols
Symbol Description Unit
A Area m
2
A
co
Contact area m
2
C
fan
Inverter fan-out capacitance F
C
gate
Gate capacitance F
C
load
Load capacitance connected to BL F
C
ox
Gate oxide capacitance F
D Diffusion coefcient cm
2
/s
D
0
First Arrhenius coefcient cm
2
/s
E Energy eV
Dielectricity constant F/cm
E
a
Activation energy eV
E
c
Conduction band energy eV
E
g
Band gap energy eV
E
Ph
Optical phonon energy eV
E
pot
Potential energy eV
E
kin
Kinetic energy eV
E
trap
Difference between quasi-Fermi-level and trap energy eV
E
T
Trap energy eV
E
qF
Quasi-Fermi energy eV
E
v
Valence band energy eV
E
ijkl
Elasticity modulus dyn/cm
2
kl
Strain tensor cm
2
/dyn
F Electric eld V/cm
F Force N
F
eff
Effective electric eld V/cm
F
Normal electric eld V/cm

G Shear modulus dyn/cm
2
g
m
Transconductance A/V
h Plancks constant Js
h Dirac constant (h/2) Js
I Current A
I
drain
Drain current A/m
173
174 List of Symbols
I
off
Leakage current A/m
I
on
Drive current A/m
J Current density A/cm
2
J
D
Diffusion current A/cm
2
J
n
Electron current density A/cm
2
J
p
Hole current density A/cm
2
k Bolzmanns constant J/K
m
Thermal conductivity W/cmK
K Shear modulus dyn/cm
2
L
gate
Physical gate length m
L
co
Contact length m
n
De Broglie wavelength nm
Charge carrier mobility cm
2
/Vs
or mean value
ac
Acoustic phonon dependent mobility cm
2
/Vs
cc
Carrier-Carrier scattering dependent mobility cm
2
/Vs
bal
Ballistic mobility cm
2
/Vs
const
Bulk silicon mobility cm
2
/Vs
dop
Doping dependent mobility cm
2
/Vs
eff
Effective mobility cm
2
/Vs
eh
Carrier-Carrier scattering dependent mobility cm
2
/Vs
fef
Field effective mobility cm
2
/Vs
high
High eld mobility cm
2
/Vs
low
Low eld mobility cm
2
/Vs
n
Electron mobility cm
2
/Vs
p
Hole mobility cm
2
/Vs
sr
Surface roughness dependent mobility cm
2
/Vs
m
0
Free electron mass kg
m
Effective mass kg
m
t
Tunneling mass kg
N Doping concentration cm
3
N
a
Acceptor concentration cm
3
N
d
Donor concentration cm
3
n Electron concentration cm
3
p Hole concentration cm
3
n
i
Intrinsic charge carrier concentration cm
3
N
2
Ion dose cm
2
Electrostatic potential V
Fermi potential V
B
Schottky barrier height eV
b
Built in potential V
n
Electron quasi-Fermi potential V
p
Hole quasi-Fermi potential V
Piezo coefcient perpendicular to the channel -

List of Symbols 175
Piezo coefcient parallel to the channel -

Piezo coefcient Pa
1
P Poisson ratio -
P Power W
P
av
Average power consumption W
P
th,diss
Thermal power dissipation W
q Elementary charge C
R Resistance
R
co
Schottky contact resistance
R
p
Projected range m
R
S/D
Source/Drain series resistances
R
th
Thermal resistance m
2
K/W
Density cm
3
trap
Defect traps and xed charge density cm
3
c
Specic contact resistance cm
2
Mechanical stress tensor Pa
or standard deviation
Mechanical stress along the channel direction Pa
Mechanical stress perpendicular to the channel direction Pa
XX
Uniaxial stress along the channel Pa
YY
Uniaxial stress perpendicular to the channel Pa
ij
Stress tensor Pa
Carrier life time s
n
Electron life time s
p
Hole life time s
t
adder
Adder delay s
t
body
Body thickness m
t
BOX
Buried oxide thickness m
t
carry
Carry-ag delay s
t
etch
Etching depth m
t
m
Material thickness m
t
ox
Gate oxide thickness m
t
peak
RTA peak temperature time s
t
prop
Propagation delay s
t
read
Read delay s
t
sum
Sum signal delay s
t
write
Write delay s
T Temperature

C
Mobility reduction coefcient 1/V
T
0
Room temperature

C
T
peak
RTA peak temperature

C
v
drift
Drift velocity m/s
v
g
Group velocity m/s
v
sat
Saturation velocity m/s
176 List of Symbols
v
th
Thermal velocity m/s
V Voltage V
V
DD
Supply voltage V
V
drain
Drain voltage V
V
gate
Gate voltage V
V
in
Circuit input voltage V
V
M
Inverter threshold voltage V
V
out
Circuit output voltage V
V
th
Threshold voltage V
V
th,low
Low eld threshold voltage V
V
th,high
High eld threshold voltage V
V
x
Atomic volume m
3
W Physical gate width m
W
co
Contact width m
W
eff
Effective channel width m
Y Youngs Modulus dyn/cm
2
List of Acronyms
Acronym Description
ADD Advanced Drift-Diffusion
BICs Boron intersticial clusters
BL Bit-Line
BOX Buried oxide
CAD Computer aided design
CD Critical dimension
CESL Contact etch stop layer
CMOS Complementary metal oxide semiconductor
CMP Chemical mechanical polishing
CNT Carbon nano-tube
CoLiDe Coupled lithography and device simulation
CVD Chemical vapor deposition
DD Drift-Diffusion
DG FDSOI Double gate fully depleted silicon on insulator
DIBL Drain induced barrier lowering
DtD Die-to-Die
EOT Equivalent oxide thickness
FA Full adder
FDSOI Fully depleted silicon on insulator
GEV Generalized extreme values
GIDL Gate induced drain leakage
HD Hydrodynamic
HP High performance
HPC High performance computing cluster
ITRS International Technology Roadmap for Semiconductors
LOP Low operating power
LSTP Low standby power
LWR Line width roughness
MBE Molecular beam epitaxy
MC Monte Carlo
MOSFET Metal oxide semiconductor eld effect transistor
MSA Millisecond annealing
177
178 List of Acronyms
PDF Probability density function
PVCM Process variations compact modeling
RDD Random discrete dopants
RTA Rapid thermal annealing
SCE Short channel effect
SEG Selective epitaxial growth
SG FDSOI Single gate fully depleted silicon on insulator
SNM Static noise margin
SOI Silicon on insulator
SPER Solid phase expitaxial re-growth
SPICE Simulation program with integrated circuit emphasis
SRAM Static random access memory
SSlope Subthreshold slope
STI Shallow trench isolation
TCAD Technology computer aided design
TG FinFET Triple gate FinFET
UDR Undened region
UTB Ultra thin body
VTC Voltage transfer characteristic
WL Word-line
WiD Within-Die
Index
0-9
4-Bit ripple carry adder . . . . . . . . . . . . . . . . 100, 133
6-T SRAM cell . . . . . . . . . . . . . . . . . . . 100, 108, 133
A
Advanced Drift-Diffusion model (ADD) 27, 34, 66
Average power consumption . . . . . . . . . . . . . . . . 103
B
Ballisticity correction factor . . . . . . . . . . . . . . . . . . 33
Bulk MOSFET. . . . . . . . . . . . . . . . 5, 61, 69, 93, 117
C
Carry ag signal . . . . . . . . . . . . . . . . . . . . . . . 106, 133
Carry out signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 100
Cobalt di-silicide (CoSi
2
) . . . . . . . . . . . . . . . . . 37, 39
CoLiDe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Compact model . . . . . . . . . . . . . . . . . . . . . . 19, 91, 98
Contact etch stop layer (CESL) . . . . . . . . 37, 43, 78
Contact trench/plug architecture . . . . . . . . . . . 55, 81
Critical dimension (CD) . . . . . . . . . . . . . . . . . . . . 113
CV/I . . . . . . . . . . . . . . . . . . . . . . . . 67, 75, 78, 82, 87
D
Defocus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Density change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Device simulation . . . . . . . . . . . . . . . . . . . . . 7, 13, 66
DG FDSOI . . . . . . . . . . . . . . . . . . . 6, 61, 69, 95, 117
DIBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 68, 70, 92
Die-to-Die variations (DtD) . . . . . . . . . . . . . . . . . 113
Drift-Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . 13, 22
E
Effective mobility. . . . . . . . . . . . . . . . . . . . . . . . 67, 74
EPFL-EKV . . . . . . . . . . . . . . . . . . . . . 19, 91, 92, 119
F
Field effect mobility . . . . . . . . . . . . . . . . . . . . . . . . . 73
Flash annealing. . . . . . . . . . . . . . . . . . 10, 58, 63, 122
G
Gate replacement technique. . . . . . . . . . . . . . . 45, 78
Generalized extreme values (GEV) . . . . . . 116, 117
H
Hamers method. . . . . . . . . . . . . . . . . . . . . . 34, 67, 91
Hole mobility enhancement . . . . . . . . . . . . . . . 37, 45
Hydrodynamic . . . . . . . . . . . . . . . . . . . . . . . . . . 13, 22
I
Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100, 129
Inverter threshold (VM) . . . . . . . . . . . 102, 109, 129
I
on
-I
off
relation . . . . . . . . . . . 66, 74, 78, 82, 84, 120
ITRS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
High performance (HP) . . . . . . . . . . . . . . 62, 84
Low operating power (LOP) . . . . . . . . . . 62, 85
Low standby power (LSTP) . . 62, 85, 93, 101,
123
L
Line width roughness (LWR) . . . . . . . . . . . 113, 135
Lithography simulation . . . . . . . . . . . . . . . . . . . . . 114
Low eld mobility. . . . . . . . . . . . . . . . . . . . 34, 68, 91
179
180 Index
M
MASTAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Mechanical stress . . . . . . . . . . . . . . . . . 12, 18, 37, 78
Millisecond annealing (MSA) . . . . . . . . . . . . . 10, 66
Mixed-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Modied piezo model . . . . . . . . . . . . . . . . . . . . . . . 46
Monte Carlo. . . . . . . . . . . . . . . . . . . . . . 13, 22, 27, 33
Multi-gate compact modeling
DG FDSOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TG FinFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
N
Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 99
Nickel mono-silicide (NiSi) . . . . . . . . . . . . . . . 37, 39
P
Piezo coefcients . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Process simulation . . . . . . . . . . . . . . . . . . . . . . 7, 8, 63
Process variability compact modeling (PVCM)120
Process variations . . . . . . . . . . . . . . . . . . . . . 113, 123
Propagation delay . . . . . . . . . . . . . . . . . . 67, 102, 129
Q
Quasi-ballistic charge carrier transport . . . . . 21, 66
R
Random discrete dopants (RDD) . . . 124, 129, 133
Rapid thermal annealing (RTA) . . . . . . . . . . . 10, 66
Relaxation temperature . . . . . . . . . . . . . . . . . . . . . . 40
Ring oscillator . . . . . . . . . . . . . . . . . . . . 100, 104, 132
S
Saturation velocity . . . . . . . . . . . . . . . . 16, 22, 25, 92
Schottky contact resistances . . . . . . 17, 51, 81, 121
SG FDSOI . . . . . . . . . . . . . . . . . . . . 5, 61, 69, 93, 117
Shallow trench isolation (STI) . . . . . . . . . . . . 38, 78
Silicidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Silicide material parameters. . . . . . . . . . . . . . . 39, 40
SOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 2, 5, 69
SPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 18, 91, 119
SPICE parameter extraction . . . . . . . . . . . 67, 91, 98
Spike annealing . . . . . . . . . . . . . . . . . . . . . . 10, 58, 63
Spin-on-dopant source . . . . . . . . . . . . . . . . . . . 59, 82
SSlope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68, 70, 92
Static noise margin (SNM) . . . . . . . . . . . . . 110, 133
Surface roughness . . . . . . . . . . . . . . . . . . . . . . . 15, 69
T
TCAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 7
Temperature uctuations . . . . . . . . . . . . . . . . . . . . 122
TG FinFET . . . . . . . . . . . . . . . . . . . . 6, 61, 65, 69, 98
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal resistance network . . . . . . . . . . . . . . . . . . 26
Threshold latitude . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Threshold voltage . . . . . . . . . . . . . . . . . . . 67, 91, 117
Titanium di-silicide (TiSi
2
) . . . . . . . . . . . . . . . 37, 39
U
Undened region (UDR) . . . . . . . . . . . . . . . . . . . . 101
V
Velocity overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage controlled voltage soure . . . . . . . . . . . . . . 97
Voltage transfer characteristic (VTC) . . . . . . . . . 101
W
Within-Die variations (WiD) . . . . . . . . . . . . 113, 133
Write static noise margin (WSNM) . . . . . . . . . . 111
Y
Y-function . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 67, 91

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Christian Kam Pen Dissertation

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Evaluation of CMOS Architectures Below 50 nm

Gate Length by Numerical Simulations

C [37]. Here, the

C) at small time scales

is the transverse electric eld normal to the gate oxide surface, F

was set to a value of 2 [47], but was adjusted in SDevice [31] by

are t parameters [31].

is the Schottky resistance at an innity high doping

of the carriers are modied by mechanical stress.

the effective mass

in Eq. (3.7) was set to 0.78 m

1) 16.0 10.4 12.5

are the piezo coefcient and the stress value perpendicular (

the effective mass,

C for 20 s and 1070

C for 10 s. The expected doping concentration proles,

, the impact of tapered side walls has to be considered by

C) followed by a ash annealing scheme with a peak temperature of approximately

to implant into the sidewalls of

, while y-polarized light

C within a die. To take the impact of temperature

represents the difference of

. Figure 8.8(b) shows an exampled of a

Normal electric eld V/cm

Piezo coefcient perpendicular to the channel -

Piezo coefcient parallel to the channel -

Mechanical stress along the channel direction Pa

Mechanical stress perpendicular to the channel direction Pa

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