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Milan Brejl
Motorola Czech Systems Laboratories,
1. mje 1009, 756 61 Ronov p.Radh., Czech Republic,
E-mail: Milan.Brejl@motorola.com
Abstract: The article discusses FSK [1] demodulation algorithms suitable for an
implementation on a DSP. The algorithms are based on direct DFT (Discrete
Fourier Transformation) values computation. Their behavior in different noisy
environments is simulated. The implementation of this algorithm on a power-line
modem application is briefly described.
I. INTRODUCTION
The power of today's digital signal processors [2] enables implementation of digital
modulation/demodulation algorithms in software. Advanced demodulation techniques require
significantly higher computational power but also bring great improvement to the error ratio in
noisy environments.
The subject of this article is a discussion about FSK demodulation algorithms that are
designed for maximal noise proof and with respect to implementation on a DSP.
II. THEORY
DFT computes the continuous frequency function of a given discrete-time signal. Here,
DFT is used to compute the values F
0
and F
1
of a frequency function at only two discrete
points - at frequencies f
0
and f
1
. f
0
is the frequency of a signal element corresponding to bit 0
and f
1
is the frequency of a signal element corresponding to bit 1.
b
1
0
j
0
0
N
n
n
e n s F
;
, (1)
b
1
0
j
1
1
N
n
n
e n s F
;
(2)
where
s
f
f
0
0
! 2 ; , (3)
s
f
f
1
1
! 2 ; (4)
and s(n) is the signal element sample, f
s
is the sampling frequency.
Comparison of F
0
and F
1
decides if the signal element transfers bit 0 or bit 1. Lets
establish a binary vector MSG as the transmitted message. Then
0 1
F F j MSG (5)
where j is the index of the actual signal element and the corresponding bit.
Further solutions are required to establish synchronization to the signal element within
the incoming FSK signal and to suppress the noise influence.
150 200 250 300 350 400 450
0
0.05
0.1
0.15
0.2
0.25
0.3
Window No.
Spectral
Power
Density
Figure 1. The course of |F
0
|
2
(solid line) and |F
1
|
2
(dotted line) - variant 3:1. The data burst starts approx. at the
window No. 300 where the start sequence is recognizable.
In correspondence with the rule of a digital signal minimal frequency differentiation, the
signal element length T is chosen:
0 1
1
f f
T
(6)
to obtain a maximum bit rate. Than
T f N
s
(7)
The incoming signal is windowed by a rectangular window of length N. The rectangular
window shape and the window length N are necessary to accomplish maximum frequency
differentiation.
Lets establish an index i for indexing each signal window and the corresponding
variables.
The computation of F
0
(i) and F
1
(i) and consequential comparison is done for each signal
window:
i F i F i b
0 1
(8)
The approximate beginning of the data burst is set from the signal window where the
instantaneous value S
B
(i) crosses the doubled value S
A
(i):
i S i S
A B
2 (9)
S
B
(i) is a short-term sliding average of the sum of F
0
and F
1
. S
A
(i) is a long-term sliding
average of the sum of F
0
and F
1
. The sliding averages S
A
(i) and S
B
(i) are computed in each step
as follows:
( i F i F i S i S
1 0 B B B B
1 1 , (10)
if 1 2
A B
i S i S then
( i F i F i S i S
1 0 A A A A
1 1 (11)
otherwise S
A
is not updated: S
A
(i) = S
A
(i-1).
and
>
makes the S
A
long-term sliding average and S
B
the short-term one.
In order to achieve synchronization between the window and the signal element, a
synchronization byte is transmitted in the head of each data burst. The synchronization byte is
formed by a bit sequence [1 0 1 0 0 1 0 1]. The transmitter and receiver clocks are supposed to
be precise enough to maintain this synchronization during the whole data burst.
The best fit to the synchronization sequence is computed as the position where the
divergence between sequence b of the F
0
(i), F
1
(i) comparison results and the interpolated
synchronization bit sequence is minimal
SYN min of index idx (12)
where
(