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FLEX 8000
Programmable Logic
Device Family
January 2003, ver. 11.1 Data Sheet
DS-F8000-11.1
F
L
E
X
8
0
0
0
3
1
Features...
Low-cost, high-density, register-rich CMOS programmable logic
device (PLD) family (see Table 1)
2,500 to 16,000 usable gates
282 to 1,500 registers
System-level features
In-circuit reconfigurability (ICR) via external configuration
devices or intelligent controller
Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
MultiVolt
TM
I/O interface enabling device core to run at 5.0 V,
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
Low power consumption (typical specification is 0.5 mA or less in
standby mode)
Flexible interconnect
FastTrack
MAX+PLUS