EE 500 HDL Based Digital Design with Programmable Logic

Syllabus Spring 2014

Course info
EE 500 HDL Based Digital Design with Programmable Logic, 3 credits
Prereq: EE 278 Digital Principles with a grade of C or better
Lecture: M 5:00 PM 7:50 PM, Alumni 97
Labs: L1 Tu 12:00PM - 1:50PM, Furnas 214
L2 Tu 5:00PM - 6:50PM, Furnas 214
L3 Th 12:00PM - 1:50PM, Furnas 214
L4 Fr 5:00PM - 6:50PM, Furnas 214

Midterm Exam: March 10
th
- In class

Final Exam: 5/13/2014, Tuesday 7:15 PM - 10:15 PM, Knox 109

Term Paper Submission: 5/6/2014, Tuesday 11:59 PM

Deadline to return the Atlys Board: 5/9/2014, Friday 5:00 PM to Jason Tillman, EE

Instructor
Dr. Praveen Meduri,
praveenm@buffalo.edu
Office: 230 J Davis Hall
Office hours: M 4:00 PM to 5:00 PM or by appointment

Bulletin description
Introduction to hardware description languages (HDL). VHDL based design of digital systems.
Analysis via implementation on field programmable gate arrays (FPGAs).

Textbook
Jr. Charles H. Roth and Lizy K. John, Digital Systems Design Using VHDL, CL Engineering, 2
nd

edition, 2007, ISBN-10: 0534384625.

Course objectives
The overall course objective is to teach electrical engineering students fundamental concepts of
hardware description languages and advanced techniques in digital system design. Specific
objectives include the following:
1. Utilize VHDL to design and analyze digital systems including arithmetic units and state
machines.
2. Learn field programmable gate array (FPGA) technologies and utilize associated computer
aided design (CAD) tools to synthesize and analyze digital systems.
3. Learn testing strategies and construct testbenches.
4. Conduct laboratory experiments using an FPGA based development board to prototype digital
systems and to confirm the analysis done in class.
5. Prepare informative and organized lab reports that describe the methodologies employed, the
results obtained, and the conclusions made in a laboratory experiment.


Evaluation Procedures and Grading Criteria

Item Percentage
Homework 10%
Labs
Quizzes
Professionalism
15%
5%
5%
Term Paper 15%
Midterm exam 20%
Final exam 20%
Term Paper Presentation 10%

Evaluation:
A = [94-100] A- = [90-94)
B+ = [87-90) B = [84-87) B- = [80-84)
C+ = [77-80) C = [74-77) C- = [70-74)
D+ = [67-70) D = [64-67) D- = [60-64)
F = [0-60)

Homework
Homework submissions are on UBLearns by the deadline. No late submissions are accepted.
If you are absent from class or you know that you will be absent from class, you should, as soon
as possible, arrange with the instructor for any missed work. It is the student's responsibility to
contact the instructor in such a case.
Collaboration on homework is ok, copying is not ok; a separate solution is required for each
student.
Include your name on all homework assignments, reports, exams, etc.
Turn in solutions that are written clearly and neatly; disorganized or esthetically-ugly solutions
with scratched out text, figures, and formulas, etc. is penalized by deducting grade-points even if
the final answer is correct.

Labs
All labs must be completed or you will fail this course. One lab (missed for any reason) only can
be made-up in the final week. Make-up labs will only be allowed in special situations. The
extraordinary circumstances requiring a make-up lab must be verifiable. Lab assignment demos
and reports are due in the next lab following the lab with the assignment.

Term Paper
This is an individual term paper on topics related to VHDL and/or Digital Design in general. You
can pick from any of the following topics/get the prior permission of the instructor to select your
own topic.

Deadline for submission: Tuesday, May 6th 2014, 11:59 PM, Submission Via UBLearns Link
Length of the paper: 16 - 20 pages
Format for the paper: IEEE. See attached sample. IEEE_trans_jour_sample.docx
The attached sample (MS Word document) is in formatted as per guidelines. You may use this
pre-formatted sample to copy and paste your text/figures.

Topics for the paper:
You may choose any one of the following topics. However, if you are interested in any particular
topic that is not listed here, you may work on it after the instructors approval.
(1) Optimal State Assignment for Finite State Machines
(2) Built in Self Test (BIST) for Digital Integrated Circuits
(3) Automatic Test Pattern Generation (ATPG) for Digital Circuit Testing
(4) Gate Induced Drain Leakage (GIDL)
(5) Ultra-Low Power Subthreshold Logic Design
(6) Other topic of your choice, related to Digital Design. Instructors approval required before you
can start working.

You may choose to use EndNote software to easily create/insert references in your paper.
EndNote is available for free download from UB Libraries
(Win/Mac): http://library.buffalo.edu/help/endnote/
EndNote is one of the industry standard tools for managing Citations, References and
bibliographies.
A six minute power-point presentation is required in class for each person.

Attendance Statement, Quizzes and Other Policies
While university regulations do not require attendance in class, the student should know that
there may be material covered in class which is not discussed in the text or which may be
discussed in a different manner than presented in the text. The student is responsible for all the
material discussed in class whether or not the student was in class. If the student misses a class
period, it is the student's responsibility to obtain the notes from a classmate.
Having said that, Quizzes are designed to encourage class attendance. A total of 4 6 in class
surprise quizzes will be assigned in the class for a total of 5% of the final grade.
If the student has questions about the way a particular homework or exam problem was graded,
s/he should discuss this with the instructor during office hours. However, this must be done
within one week the exam or homework was returned to the class.
Questions during class are highly encouraged.

Professionalism
"Students are expected to use professional style in all communications, including email, with
course faculty and teaching assistants. This includes the use of salutations and closings
(including clear identification of the author) and proper grammar."
"Students are expected to refrain from use of cell phones or other electronic devices unless they
are clearly linked to class purposes (e.g., note-taking). Cell phones must remain off or muted."
No food or drinks in the labs
Special Needs
Students with disabilities or other special needs, who need special accommodations in this
course, are invited to share these concerns or requests with the instructor as soon as possible.





Academic Honesty
All work in this course must be completed in a manner consistent with University at Buffalo
academic integrity policy. Violation of this policy will result in receipt of a failing grade. Please
read: http://undergrad-catalog.buffalo.edu/policies/course/integrity.shtml
If you are in doubt, please ask me. Do not assume.


Lab Boards Checkout
You work in groups for the labs 2 persons per group
1 Report per group with the names of the partners clearly mentioned
You will be able to check out the Atlys boards to work at home. One board per group can
be checked out.
Both the partners of the group need to pay a fee in the university bookstore in order to
check out the boards.
The boards may be checked out (one per group) form Mr. Jason Tillman Technical
Associate, Department of Electrical Engineering, 230 Davis Hall.
Each partner needs to present a receipt of payment and sign a lease at the time of check out.