SUMMERY :

AT24C02 is two-wire serially programmable EEPROM. This means that for programming, the data and
control signals are provided serially along with clock signals from the other wire. The read-write
operations are accomplished by sending a set of control signals including the address and/or data bits
from a microcontroller.
This project demonstrates the memory reset operation of a 24C02 IC by using AT89C51. For basic
operations of AT24C02, refer interfacing serial EEPROM with 8051. It writes & reads a byte to/from the
EEPROM displaying it on a 16x2 LCD, and then resets the memory. The results can be monitored on the
LCD display


DESCRIPTION :

AT24C02 is a two-wire serial EEPROM from Atmel. 24C02 is an 8 pin IC and reads 8 bit data serially. Its
memory size is 2KB. Pins 1- 3 are address pins which are connected to ground. Pin 4 is GND; Pin 5 is
SDA (serial data); and pin 6 is SCL (serial clock input). Pin 7 is WP (write protect) pin and is connected to
GND. Pin 8 is Vcc for providing power supply. For details on its interfacing and operation, refer interfacing
24C02 with 8051.
The microcontroller monitors the start, stop, acknowledge, send, save, read instructions of EEPROM.
The memory can be reset after a power loss, a system reset or an interruption in protocol. The project
resets memory after a write and read operation continuously.

To reset memory, EEPROM is clocked nine times followed by the start condition. For this, a high SDA
signal is looked for in each cycle while SCL is high, i.e., acknowledge function is called 9 times.



SDA and SCL pins are connected to P1.0 and P1.1 of AT89C51 and through these pins, serial data
transfer takes place. Port P2 of microcontroller is used for connecting LCD data pin while control pins of
LCD (RS, RW & EN) are connected to P3.0, P3.1 and P3.6 of the controller. For more details, refer LCD
interfacing with AT89C51.


Start condition:
Any read or write operation in EEPROM is initiated by Start condition. This occurs when there is a high to
low transition of SDA while SCL is high. (Refer the following diagram) This tells the EEPROM that words
from the controller are ready for it. SCL is set low at the end of start condition. This is because any read
or write operation first involves transfer of some words to EEPROM. That requires a low to high transition
of clock corresponding to each bit of the word.



Clocking:
When a sequence of words is transferred to EEPROM, a clock is needed to be sent by the controller after
transmission of each word. This is required so that the controller can receive its acknowledgement. Clock
is just a high transition followed by a low transition of SCL when the initial clock signal is low.