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1
A High Voltage Gain DC-DC Converter Integrating
Coupled-inductor and Diode-capacitor Techniques
Xuefeng Hu, Chunying Gong, Member, IEEE

AbstractThe high voltage gain converter is widely employed
in many industry applications, such as photovoltaic systems, fuel
cell systems, electric vehicles and high intensity discharge lamps.
This paper presents a novel single switch high step up
non-isolated dc-dc converter integrating coupled-inductor with
extended voltage doubler cell and diode-capacitor techniques.
The proposed converter achieves extremely large voltage
conversion ratio with appropriate duty cycle and reduction of
voltage stress on the power devices. Moreover, the energy stored
in leakage inductance of coupled-inductor is efficiently recycled
to the output, and the voltage doubler cell also operates as a
regenerative clamping circuit, alleviating the problem of
potential resonance between the leakage inductance and the
junction capacitor of output diode. These characteristics make it
possible to design a compact circuit with high static gain and high
efficiency for industry applications. In addition, the unexpected
high pulsed input current in the converter with coupled-inductor
is decreased. The operating principles and the steady-state
analyses of the proposed converter are discussed in detail. Finally,
a prototype circuit is implemented in the laboratory to verify the
performance of the proposed converter.

I ndex TermCoupled-inductor, diode-capacitor, high voltage
gain, dc-dc, low voltage stress.
I. INTRODUCTION


n recent years, high voltage gain dc-dc boost converters
play more and more important role in many industry
applications such as uninterrupted power supplies (UPS),
electric traction, distributed photovoltaic (PV) generation
systems, fuel cell energy conversion systems, automobile HID
headlamps, and some medical equipments[1]-[8]. In these
applications, a classical boost converter is normally used, but
the voltage stress of the main switch is equal to the high
output voltage, hence, a high-voltage rating switch with high
on-resistance should be used, generating high conduction
losses. In addition, an extremely high duty cycle will results in


Manuscript received Sep 20, 2012; revised Feb 19, 2013; accepted for
publication Mar 27, 2013. This work was supported by the Fundamental
Research Funds for the Central Universities, Natural Science Foundation of
Anhui Education Committee (KJ2012A048).
X.F. Hu is with the Aero-Power Sci-tech Center, the College of Automation
Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing
210016, China, and also with Anhui Key Laboratory of Power Electronics and
Motion Control Technology, the College of Electrical and Electronic
Engineering, Anhui University of Technology, Maanshan 243002, China
(e-mail: hxu-123@163.com, ).
C.Y.Gong is with the Aero-Power Sci-Tech Center, the College of
Automation Engineering, Nanjing University of Aeronautics and Astronautics,
Nanjing 210016, China, (e-mail: zjnjgcy@ nuaa.edu.cn).

large conduction losses on the power device and serious
reverse recovery problems. As a result, the conventional boost
converter would not be acceptable for realizing high step-up
voltage gain (V
out
8 V
in
) along with high efficiency. Many
non-isolated topologies have been researched to achieve a
high conversion ratio and avoid operating at extremely high
duty cycle. These converters include the switched-capacitor
types [10]-[11], switched-inductor types [12]-[13], the
voltage-doubler circuits [15]-[16], the voltage-lift types [17],
and the capacitor-diode voltage multiplier [18]-[20]. All of
them can present higher voltage gain than the conventional
boost converter. However, more switched-capacitor or
switched-inductor stages will be necessary for an extremely
large conversion ratio, resulting in higher cost and complex
circuit. The quadratic boost converter using a single active
switch is another interesting topology for extending the
voltage gain [20]-[22], where the voltage conversion ratio is
given as a quadratic function of the duty ratio. However, the
voltage gain of this converter is moderately since the output
voltage level is determined only by the duty cycle. Moreover,
if the components used are idea ones, the voltage stress of the
active switch is equal to output voltage. Thus, in high output
voltage applications, a high-voltage rating switch should be
selected. In [23]an improved quadratic boost converter using
coupled inductor and voltage-lift techniques is presented, and
the authors suggest how to optimal coupling coefficient of the
coupled inductor for low input current ripple.
To achieve a high conversion ratio without operating at
extremely high duty ratio, some converters based on
transformers or coupled- inductors or tapped-inductors have
been researched [24]-[37]. The conventional flyback converter
is usually adopted for achieving high voltage gain by adjusting
the turns ratio of the transformer. However, the leakage
inductor of the transformer may not only cause high voltage
spikes on the power device, but also induce energy losses. In
order to improve above problems, a resistor-capacitor-diode
(RCD) snubber can be used, but the leakage inductor energy is
dissipated. Although active clamped techniques can release
high voltage spikes and reduce switching losses [31], an
additional active switch leads to complex structures and
control. Many boost converters based on Coupled-inductor or
tapped-inductor provide solutions to achieve a high voltage
gain, and low voltage stress on the active switch without the
penalty of high duty ratio [23][26], [28]. However, the input
current is not continuous. Particularly, as the turn ratio of the
coupled-inductor or tapped-inductor is increased to extend the
I
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
2
voltage conversion ratio, the input current ripple becomes
larger [27]-[29]. Thereby, an input filter is inserted into a
coupled-inductor boost converter [30]. In order to satisfy the
extremely high step-up applications and low input current
ripple, a cascaded high step-up converter with an individual
input inductor was proposed [31], which can be divided as a
basic boost converter and a boost-flyback converter [28].
In this paper, a novel single switch dc-dc converter with
high voltage gain is presented. The features of the proposed
converter are as follows: 1) the voltage gain is efficiently
increased by a coupled-inductor and the secondary winding of
the coupled inductor is inserted into a diode-capacitor for
further extending the voltage gain dramatically; 2) a passive
clamped circuit is connected to the primary winding of the
coupled-inductor to clamp the voltage across the active switch
to lower voltage level. As a result, the power devices with low
voltage rating and low on-state resistance R
DS
(ON) can be
selected. On the other hand, this diode-capacitor circuit is
useful to increase voltage conversion ratio; 3) the leakage
inductance energy of coupled-inductor can be recycled,
improving the efficiency; 4) the potential resonance between
the leakage inductance and the junction capacitor of output
diode may be cancelled.
The proposed converters steady-state operational principles
are given in section II. The circuit performance analysis will
be aim of section III, where an approximate dc analysis (losses
neglected) is performed to get the static voltage gain and
voltage stress on power devices. The key parameter design
guidance is presented in Section IV. The experimental results
of a 500W prototype at full load are shown in Section V to
verify the analysis. A valuable summary will end the paper in
the final section.
II. OPERATIONAL PRINCIPLE OF THE PROPOSED CONVERTER
Fig.1 (a) shows the circuit structure of the proposed
converter, which consists of an active switch Q, an input
inductor L
1
and a coupled-inductor T
1
, diodes D
1
, D
2
and D
O
, a
storage energy capacitor C
1
and a output capacitor C
O
, a
clamped circuit including diode D
3
and capacitor C
2
, an
extended voltage doubler cell comprising regeneration diode
D
r
and capacitor C
3
and the secondary side of the
coupled-inductor. The simplified equivalent circuit of the
proposed converter is shown in Fig.1 (b). The dual-winding
coupled inductor is modeled as an ideal transformer with a
turn ratio N (n
2
/n
1
), a parallel magnetizing inductance L
m
,
primary and secondary leakage inductance L
k1
and L
k2.
In order to simplify the circuit analysis of the converter,
some assumptions are as follows.
1) The input inductance L
1
is assumed to be large
enough so that i
L1
is continuous; every capacitor is
V
GS
i
DS
V
GS
i
L1
i
Lm
i
LK1
i
LK2
i
C1
i
C2
i
C4
t
0
t
1
t
2 t
3
t
4
t
5
t
t
t
t
t
t
t
t
t
T
S

Fig.2. The key waveforms of the proposed converter at C-CCM
operation.
R
Vin
+
-



+
+
+ +
1
n
2
n
3
D
1 L
i
1
L
1
D
2
D
2
C
O
D
O
V
O
C
+
-
3
C
r
D
Q 1
C
Clamp-circuit
Voltage doubler cell

R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
i
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q 1 C
V
+ - Lm
V
1 LK
i
Lm
i
2 C
i
2 n
V + -
2 K
L
1 K
L
3 c
i
o
i
ds
i
co
i
+ -
2 D V
1 D
V
+ -
+
+
+
+
-
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D V
+
-
2 n
i
2 LK
i
m
L
T1
L1

(a) (b)
Fig.1. Circuit configuration of the proposed converter. (a) Proposed converter. (b) Simplified equivalent circuit of proposed converter.

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3
sufficiently large, and the voltage across each capacitor
is considered to be constant during one switching
period.
2) All components are idea except the leakage
inductance of the coupled inductor.
3) Both inductor currents i
L1
and i
Lm
are operated
in continuous conduction mode, which is expressed as
C-CCM; the inductor current i
L1
is operated in
continuous conduction mode, but the current i
Lm
of the
coupled inductor is operated in discontinuous
conduction mode, which is called C-DCM.
A. C-CCM
Based on the aforementioned assumption, Fig. 2 illustrates
some key waveforms under C-CCM operation in one
switching period, and the corresponding equivalent circuits are
shown in Fig.3. The operating stages are described as follows:
1Stage 1 [t
0
-t
1
]:The switch Q is conducting at t=t
0
. Diodes
D
1, D
3
and D
O
are reverse-biased by V
C1
,V
C1
+V
C2
and
V
O
-V
C1
-V
C2
, respectively. Only Diodes D
2
and D
r
are turned on.
Fig. 3(a) shows the current-flow path. The dc source V
in

energy is transferred to the inductor L
1
through D
2
and Q.
Therefore, the current i
L1
is increasing linearly. The primary
voltage of the coupled inductor including magnetizing
inductor L
m
and leakage L
K1
is V
C1
and the capacitor C
1
is
discharging its energy to the magnetizing inductor L
m
and
primary leakage inductor L
K1
through Q. Then currents i
D2
, i
Lm

and i
K1
are increasing. Meanwhile, the energy stored in C
2
and
C
1
is released to C
3
through D
r
. The load R energy is supplied
by the output capacitor C
O
. This stage ends at t = t
1
.
2) Stage 2 [t
1
-t
2
]: In this transition interval, Fig. 3(b) depicts
the current-flow path of this stage. Once Q is turned off at t=t
1
,
the current through Q is forced to flow through D
3
. At the
same time, the energy stored in inductor L
1
flows through
diode D
1
to charge capacitor C
1
instantaneously and the
current i
L1
declines linearly. Thus, the diode D
2
is reverse
R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q 1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+ -
-

R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q
1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+
-

(a) (b)
R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q
1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+
-

R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q
1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+
-

(c) (d)
R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q 1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+
-

(e)
Fig.3. Equivalent circuits of five operating stages during one switching period at C-CCM operation.


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4
biased by V
C2
.The diode D
O
is still reverse biased by
V
O
-V
C1
-V
C2
. The energy stored in inductor L
K1
flows through
diode D
3
to charge capacitor C
2
.Therefore, the energy stored
in L
K1
is recycled to C
2
. The i
LK2
keeps the same current
direction for charging capacitor C
3
through diode D
3
and
regeneration-diode Dr .The voltage stress across Q is the
summation of V
C1
and V
C2
. The load energy is supplied by the
output capacitors C
O
. This stage ends when i
LK2
reaches zero at
t=t
2
.
3) Stage 3 [t
2
-t
3
]: During this transition interval, switch Q
remains off. Since i
LK2
reaches zero at t=t
2
, V
C2
is

reflected to
the secondary side of coupled inductor T
1
,thus
regeneration-diode Dr is blocked by V
C3
+
NV
C2
.Meanwhile,the diode D
O
starts to conduct. Fig. 3(c)
depicts the current-flow path of this stage. The inductance L
1
is still releasing its energy to the capacitor C
1
. Thus, the
current i
L1
still declines linearly. The energy stored in L
k1
and
L
m
is released to C
2
. Moreover, the energy stored in L
m
is
released to the output via n
2
and C
3
. The leakage inductor
energy can thus be recycled, and the voltage stress of the main
switch is clamped to the summation of V
C1
and V
C2
. This stage
ends when current i
LK1
= i
LK2
, thus the current i
C2
=0 at t = t
3
.
4) Stage 4 [t
3
-t
4
]: During this time interval, the switch Q,
diodes D
2
and D
r
is still turned off. Since i
C2
reaches zero at
t=t
3
, the entire current of i
LK1
flows through D
3
is blocked. The
current-flow path of this mode is shown in Fig. 3(d). The
energy stored in inductor L
1
flows through diode D
1
to charge
capacitor C
1
continually, so the current i
L1
is decreasing
linearly. The dc source V
in
, L
1
, L
m
, L
k1
, the winding n
2
, L
k2
and
V
C3
are series-connected to discharge their energy to capacitor
Co and load R. This stage ends when the switch Q is turned on
at t=t
4
.
5) Stage 5 [t
4
-t
5
]:The main switch Q is turned on at t
4
.During
this transition interval, diodes D
1
, D
3
and D
r
are reverse-biased
by V
C1
,V
C1
+V
C2
and V
O
-V
C1
-V
C2
, respectively. Since the
currents i
L1
and i
Lm
are continuous, only diodes D
2
and D
O
are
conducting. The current-flow path is shown in Fig. 3(e). The
inductance L
1
is charged by input voltage V
in
, and the current
i
L1
increases almost in a linear way. The blocking voltages V
C1

is applied on magnetizing inductor L
m
and primary-side
leakage L
K1
, so the current i
Lk1
of the coupled inductor is
increased rapidly. Meanwhile, the magnetizing inductor L
m

keeps on transferring its energy through the secondary
winding to the output capacitor C
O
and load R. At the same
time, the energy stored in C
3
is discharged to the output. Once
the increasing i
LK1
equals the decreasing current i
Lm
and the
secondary leakage inductor current i
K2
declines to zero at t=t
5
,
this stage ends.
B. C-DCM
To simplify the C-DCM analysis, all leakage inductances of
the coupled inductor are neglected. The coupled inductor is
modeled as a magnetizing inductor Lm and an ideal
transformer. The key waveforms of the proposed converter are
shown in Fig.4. There are four main stages during one
switching cycle. The equivalent circuits for each subinterval
are shown in Fig.5.The detailed operation of each case is
presented next.
1 Stage 1 [t
0
-t
1
]: During this time interval, Q is turned on.
Diodes D
2
and D
r
are conducted but diodes D1, D3 and DO
are blocked by V
C1
, V
C1
+V
C2
and V
O
-V
C1
-V
C2
, respectively.
The current-flow path is shown in Fig. 5(a). The
inductance L
1
is charged by input voltage V
in
, thus the
current i
L1
increases linearly. The energy from capacitor
C
1
transfers to magnetizing L
m
and current i
Lm
increases
linearly. Meanwhile, capacitor C
3
is charged through the
secondary winding coil n
2
by capacitors C
1
and C
2
. The
output capacitor C
O
provides its energy to load R. The
clamped diode D
3
is biased forward when the main switch
Q is turned off at t=t
1
, and this stage ends.
2 Stage 2 [t
1
-t
2
]: At t=t
1
, the switch Q is turned off,
resulting in a current commutation between the switch Q
and diode D
3
immediately. During this transition time
interval, diodes D
2
and D
r
are turned off because they are
respectively anti-biased by V
C2
and V
O
-V
C1
-V
C2
, and other
diodes are conducting. The current-flow path is shown in
Fig. 5(b). The dc sources V
in
is series-connected with
inductor L
1
and transfer their energies to the capacitor C
1

through D
1
. The capacitors C
2
is charged by the
magnetizing inductor L
m
via D
3
. Similarly, the dc source
V
in
, inductor L
1
, magnetizing inductor L
m
and capacitor C
3

VGS
iDS
iL1
iLm
iC1
iC2
to
t1 t2 t3 t4
TS
iLK2
t
t
t
t
t
t
t
iC4
t
DTS D`TS
t
iLK1

Fig.4. The key waveforms of the proposed converter at C-DCM operation.


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5
are series connected to transfer their energy to capacitor
Co and load R. This stage ends when the rising current i
C3

equals to current i
Lm
at t= t
2
. At the same instant, the diode
D
3
is reverse biased at t= t
2
.
3 Stage 3 [t
2
-t
3
]: During this time interval, the switch Q, D
2

and D
r
remain turned off. The diodes D
1
and D
o
are still
turned on. Since i
C2
reaches zero at t
2
, the coupled
inductor transfers energy to the output, and diode D
3
is
also blocked. The current-flow path is shown in Fig. 5(c).
The dc source V
in
and the input inductor L
1
are still
connected serially to charge capacitor C
1
. Thus, the
current i
L1
continues to decrease. Meantime, the primary
and secondary sides of doubled-inductor are serially
connected, and serially connected with V
C3
, delivering
their energy to the output capacitor C
O
and load R. This
stage ends when the current i
Lm
reduces to zero at t = t
3
.
4 Stage 4 [t
3
-t
4
]: During this transition time interval, the
switch Q and the diode D
2
is still turned off. Meanwhile,
the primary and secondary currents of the coupled
inductor have run dry at t
3
. Therefore, the diode D
3
is still
blocked by V
C1
+V
C2
, and only diode D
1
is conducting for
continuous i
L1
. The current-flow path is shown in Fig.5
(d). The capacitor C
1
is still charged by the energy stored
in L
1
and dc sources V
in
. Since the energy stored in L
m
is
empty, the energy stored in C
O
is discharged to load R.
This stage ends when Q is turned on at t=t
4
, which is the
beginning of the next switching period.
III. STEADY-STATE PERFORMANCE ANALYSIS OF THE
PROPOSED CONVERTER
A. C-CCM Operating Conduction
To simplify the analysis, the leakage inductances of the
coupled-inductor are neglected in the steady-state analysis.
Also, the losses of the power devices are not considered. Only
stages 1 and 3 are considered for C-CCM operation because
the time durations of stages 24 and 5 are short significantly.
At stage1, the main switch Q is turned on, the inductor L
1
is
charged by the input dc source V
in
, and the magnetizing
inductor L
m
is charged by the voltage across C
1
. The following
equations can be written from Fig.3 (a):
in L
V V =
1
.
(1)
1 C Lm
V V =

(2)
And the voltage of the switched capacitor C
3
can be
expressed by
2 1 1 3 C C C C
V V NV V + + =
.
(3)
During stage 3, the main switch Q is in the off state, the
inductor L
1
and magnetizing inductor L
m
are discharged
respectively. The voltages across the inductor L
1
and L
m
can
be obtained by:
.
1 1 C in L
V V V =

(4)
2 C Lm
V V =

(5)
3 2 1
) 1 (
C C C O
V V N V V + + + =

(6)
Using the inductor volt-second balance principle to the
inductor L
1
and magnetizing inductor L
m
, the following
equations can be expressed as:
R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q 1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+
-
-

R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q
1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+ -

(a) (b)
R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q
1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+
-

R
Vin
+
-



+
+
+
+
1
n
2
n
3
D
1 L
V
1
D
2 C
V
O
D
O
V
O
C
+
-
3 C
V
r
D
Q
1 C
V
+ -
Lm
V
2 n
V + -
2 K
L
1 K
L
o
i
co
i
+ -
2 D
V
1 D
V
+ -
+
+
+
+
-
-
-
-
DO
V
Dr
V
ds
V
2
D
3 D
V
+
-

(c) (d)
Fig.5. Equivalent circuits during one switching period at DCM operation.

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6
.
0 ) (
1
0
= +
} }
s
T
s
DT
C in
s
DT
in
dt V V dt V

(7)
0 ) (
2
0
1
= +
} }
s
T
s
DT
C
s
DT
C
dt V dt V

(8)
From equations (1-8), the voltages across capacitors C
1
, C
2

and C
3
are derived as follows:
.
N
V D
D
V
V
O in
C
+

=
2
) 1 (
1
1

(9)
N
DV
D
V D
V
O in
C
+
=

=
2
) 1 (
2
2

(10)
O
in
C
V
N
DN N
D
V DN N
V
+
+
=

+
=
2
) 1 (
) 1 (
) 1 (
2
3

(11)
Substituting (9),(10) and (11) into (6),the DC voltage gain
M
C-CCM
is obtained as :
.
2
) 1 (
) 2 (
D
N
V
V
M
in
O
CCM C

+
= =

(12)
Fig.6 demonstrates the relationships between the voltage
gain and the duty cycle in the conventional quadratic boost
converter, reference [32] converter and the proposed converter
at CCM operation. One can see that the proposed converter
can realize higher voltage gain with the same duty cycle and
turns ratio of the coupled inductor.
According to the description of the operating stages and
neglecting the voltage ripple on the clamp capacitor, the max
voltage stress of the main switch can be derived by:
.
N
V
V
O
Q stress
+
=

2

(13)
The comparison of the main switch voltage stresses
between the conventional quadratic boost converter, reference
[32] converter and the proposed converter is shown in Fig.7.
In the conventional quadratic boost converter, the voltage
stress of the main switch always equals to the output voltage.
The main switch voltage stress of reference [32] is determined
by duty cycle and the turn ratio of the coupled inductor, which
is far lower than the output voltage with increasing duty ratio.
Fortunately, the voltage stress of the main switch in the
proposed converter is only determined by the turn ratio of the
coupled inductor and the output voltage. One can see that the
voltage stress of the switch decreases sharply with increasing
turns ratio. Thus, the high-performance active switch can be
used here to improve the efficiency.
The voltage stress on the diodes are given by
.
O
in
D stress
V
N
D
D
V
V -
+

) 2 (
) 1 (
1
1

(14)
O in D stress
V
N
D
V
D
D
V -
+
= -

) 2 ( 2 ) 1 (
2

(15)
O
in
D stress
V
N
D
V
V -
+
=

) 2 (
1
) 1 (
2
3

(16)
O in
O
D stress
V
N
N
V
D
N
V -
+
+
= -

+
=

) 2 (
) 1 (
2 ) 1 (
) 1 (

(17)
O in
r
D stress
V
N
N
V
D
N
V -
+
+
= -

+
=

) 2 (
) 1 (
2 ) 1 (
) 1 (

(18)
In terms of the operating principles, the current ripples on
the input inductor and magnetizing inductor are expressed as:
1
1
L
V DT
I
in S
L
-
= A

(19)
m
C S
Lm
L
V DT
I
1
-
~ A

(20)
Since the average currents of i
C2
, i
C3
and i
Co
are zero in the
steady state, the average currents that flow through D
r
, D
O
and
the magnetizing inductor are, respectively, equal to the
average value of i
O
. The current stresses on power devices are
can be derived as:
.
2
1
1 ) ( 1
L
L peak D
I
I I
A
+ =

(21)
2
1
1 ) ( 2
L
L peak D
I
I I
A
+ =

(22)
0.3 0.4 0.5 0.6 0.7 0.8 0.9
0
5
10
15
20
25
Duty cycle
V
o
l
t
a
g
e

G
a
i
n
(
M

C
-
C
C
M
)
Proposed converter
Reference [32]
Conventional
quadratic
boost
N=1
N=2
N=2
N=1

Fig.6. Voltage gain comparison of the proposed converter.
0 1 2 3 4 5
0
0.5
1
1.5
Turns Ratio(N)
Reference [32]
Conventional quadratic boost
Proposed converter
P
r
o
p
o
r
t
i
o
n
(
V
Q
-
s
t
r
e
s
s

/
V
o
)
D=0.3
D=0.5
D=0.7

Fig.7. Voltage stress reduction comparison of the main switch.
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7
m
C S
O peak D
L
V DT
I I
2
1
) ( 3
+ =

(23)
D
I
I
O
peak Dr
2
) (
=

(24)
) 1 (
2
) (
D
I
I
O
peak DO

=

(25)
m
C S
O
L
L peak Lm peak D peak Q
L
V DT
I
I
I i I I
2 2
1 1
1 ) ( ) ( 1 ) (
+ +
A
+ = + =
(26)
When the switch Q is off, the average current stresses
which flow through capacitors C
1
and C
3
are can be estimated
as:
) 2 ( 2
) 1 (
) 1 (
2
1
2
2
1 ) ( 1
N L
V D DT
I
D
N
I I
O S
O L off C
+

+
~ =

(27)
O off C
I I =
) ( 3

(28)
By using the ampere-second principle on capacitors C
1
and
C
3
, the following equations can be expressed as
0
) ( 1
0
) ( 1
= +
} }
dt I dt I
S
T
S
DT
off C
S
DT
on C

(29)
0
) ( 3
0
) ( 3
= +
} }
dt I dt I
S
T
S
DT
off C
S
DT
on C

(30)
Substituting (27),(28) into (29) and (30), the following
equations are derived when the switch Q is on.
D N L
V D DT
I
D D
N
I
O S
O on C
) 2 ( 2
) 1 (
) 1 (
2
1
3
) ( 1
+

+
~

(31)
D
I D
I I
O
on C on C
) 1 (
) ( 2 ) ( 3

~ =

(32)
According to the current-balance principle on capacitor C
2
,
the following equation can be expressed as
0
) ( 2
0
) ( 2
= +
} }
dt I dt I
S
T
S
DT
off C
S
DT
on C

(33)
The average current stress on the capacitor C
2
is
approximated as the switch Q is off.
O off C
I I ~
) ( 2

(34)
B. C- DCM Operating Condition
In C-DCM operation, there are four stages. The key
waveforms are shown in Fig.4. During the time of stage 1, the
switch Q is turned on, and only diodes D
2
and D
r
are turned on.
The following equations can be written:
in L
V V =
1

(35)
1 C Lm
V V =

(36)
1 2 3 2 C C C Lm n
V V V NV V = =

(37)
During the time of stage 3, the switch Q is turned off, and
only diodes D
1
and D
O
are conducting. The voltage levels
across inductor L
1
and magnetizing L
m
and the secondary
winding coil n
2
are given as follows:
1 1 C in L
V V V =

(38)
1
1 3
+
+
=
N
V V V
V
O C C
Lm

(39)
1
) (
1 3
2
+
+
=
N
V V V N
V
O C C
n

(40)
During the time of stage 2, the output voltage V
O
can be
expressed as
2 3 1
) 1 (
C C C o
V N V V V + + + =

(41)
If D' is defined as the duty cycle of the magnetizing
inductor current from peak point ramped down to zero. By
applying the volt-second balance principle to the inductor L
1
,
magnetizing inductor L
m
and the secondary side of winding
coil n
2
, the following equations are derived:
0 ) (
) (
1
0
= +
} }
' +
s
T D D
s
DT
C in
s
DT
in
dt V V dt V

(42)
0
1
) (
1 3
0
1
=
+
+
+
} }
' +
s
T D D
s
DT
O C C
s
DT
C
dt
N
V V V
dt V

(43)
0
1
) (
) (
) (
1 3
0
2 1 3
=
+
+
+
} }
' +
s
T D D
s
DT
O C C
s
DT
C C C
dt
N
V V V N
dt V V V

(44)
From (38)-(44), the voltages of C
1
, C
2
, C
3
and D' are obtained:
D
V
V
in
C

=
1
1

(45)
D D
V D
V
in
C
'

=
) 1 (
2

(46)
D D
V D D N
V
in
C
'
+ ' +
=
) 1 (
] ) 1 [(
3

(47)
D D
D D N
V
V
M
in
O
DCM C
'
+ ' +
= =

) 1 (
) )( 2 (

48
in o
in
V N D V
V N D
D
) 2 ( ) 1 (
) 2 (
+
+
= '

49
The peak value of the magnetizing inductor current
Lmp
I is
expressed by
D
V
L
DT
DT
L
V
I
in
m
S
S
m
C
Lmp

= =
1
1

50
Since the average currents through capacitors C
2
, C
3
and C
O

are zero in steady state, the average current values of i
D3
, i
Dr
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8
and i
Do
are respectively equal to the average of I
O
, and
O
Lmp
DO Dr D
I
I D
i i i =
'
= = =
2
4 3

51
Since I
O
=V
O
/R, substituting (50) and (51) into (49) obtains
the voltage gain of the proposed converter in C-DCM as
follows:
) 1 ( 2
) 2 ( 2 ) 2 ( 2
2 2
D
f L
R
N D N N
V
V
M
s m
in
O
DCM

-
+ + + + +
= =

52
Where
s
f is the switching frequency.
C. BCM Operating Condition
If the input current through L
1
of proposed converter is
operated in boundary-condition mode, the boundary inductor
L
1B
can be derived as
s
B
f N
R D D
L
- +
-
=
2
4
1
) 2 ( 2
) 1 (

53
When the current through L
m
of proposed converter is
operated in boundary-condition mode, the boundary
magnetizing- inductor L
mB
can be depicted by (54):
s
mB
f N
R D D
L
- +
-
=
) 2 ( 2
) 1 (
2

54
The relationship between the L
1B
and the duty cycle, the
load, the switching frequency and the turn ratio are plotted in
Fig.8. Once the L
1
is higher than L
1B
, the inductor L
1
will be
operated in continuous conduction mode.
As shown in Fig.8. , if the L
m
is larger than L
mB
, the coupled
inductor will be operated in continuous conduction mode. In
the practical application, one can make a micro adjustment.
IV. KEY PARAMETER DESIGN GUIDANCE
A. Input InductorL
1
Selection
For renewable dc low-voltage sources such as PV array or
fuel cell, the lower input current ripples are usually required,
so the design guidance of the proposed converter employed in
C-CCM is given, and the input inductor L1 is designed to make
that the input current ripple is approximately 15% of the
average input current, which is derived by
s L
in
f I
D V
L
1
1
A
=

55
B. Turns Ratio and Magnetizing Inductor of Coupled
Inductor Selection
In the proposed converter, the coupled-inductor stores
energy like an inductor. Therefore, the coupled-inductor
should be designed like a fly-back transformer. The turns ratio
of the coupled inductor determines the switch duty cycle, and
the voltage, current stresses of power devices, which is
obtained by
2 ) 1 (
2
- = D
V
V
N
in
O

56
If the switch duty cycle is selected, the turns ratio of the
coupled inductor can be calculated and the power device
voltage/current stress can be easily carried out. As a result, the
power devices will be chosen easily by considering some
acceptable voltage and current margins. Usually, the duty
cycle should be less than 0.7 to reduce conduction loss of the
converter. However, if the duty ratio is too small, the
increasing turn ratio will lead to larger volume of the coupled
inductor and boundary magnetizing inductance. Furthermore,
the bigger magnetic core leads to more energy loss. As a result,
a compromise should be made to optimize the turns ratio of
the coupled inductor for a given voltage gain. In practical
applications, the turn ratio from 1 to 3 is more appropriate for
the proposed converter.
In this paper, the designed feature of the proposed converter
is mainly operated in C-CCM. In practical applications, the
theoretical boundary magnetizing inductance can be designed
at 30-45% full load by equation (54).
C. Active Switch and Diodes Selection
The voltage/current-rating of the active components can be
obtained from (13)- (18), and (21)-(26). In practice, voltage
spike usually could be produced during switch transition
process because of the effect of the leakage inductance and
parasitic capacitor. Besides, the spike voltage also could be
generated due to stray inductance and capacitance existing in
practical PCB. Therefore, regarding the above effects of the
circuit and traces, the voltage/current-rating of the selected
power devices will usually be more than 150% of the
calculated value.
D. Considerations of Capacitor Design
To suppress the voltage ripple on the clamp capacitor C
2
and the switched capacitor C
3
to a tolerant range is main
consideration. Hence, the estimated capacitances depend on
the equations (57) and (58).Where V is the maximum
tolerant voltage ripple on the capacitors C
1
, C
2
, C
3
or C
O
.
s C
f V
P
C
-
-
>
2
max
2

57
0 0.2 0.4 0.6 0.8 1
0
1
2
x 10
-4
Duty cycle
I
n
d
u
c
t
a
n
c
e
(
H
)
L
mB
L
1B

Fig.8.The boundary condition of the proposed converter with N=2.

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9
s C C
f V V
P
C
- A -
>
max

58
In practice, the equivalent series resistor (ESR) of an
aluminum electrolytic capacitor will be smaller as the
capacitance increases, so the capacitor is usually selected to be
larger than the calculated value during converter operation.
E. Analysis of Theoretical Efficiency
Once the major components parameters are chosen, the
efficiency of the converter can be estimated based on
considering the parasitic resistive components.
Some specific variable symbols of all parasitic components
are assumed as follows: r
L1
is the equivalent series resistor
(ESR) of the input inductor L
1
; r
N1
and r
N2
represent ESR of
the primary and secondary windings of the coupled inductor;
r
Q
is on-state resistance of the switch Q; r
C1
,r
C2
and r
C3
denote
respectively the equivalent series resistor(ESR) of capacitors
C
1
,C
2
and C
3
; V
FD1
, V
FD2
,V
FD3
,V
FD4
and V
FD5
are the forward
voltage drop of D
1
,D
2
,D
3
,D
4
and D
5
,respectively; r
D1
, r
D2
, r
D3
,
r
D4
and r
D5
are respectively the forward resistance of D
1
, D
2
,
D
3
, D
4
and D
5
;According to previous work [28][36], the
theoretical efficiency is found by
5 4 3 2
1
1
1
A A A A
A
+ +

= q

] ) 2 (
) 2 2 [(
) 2 (
) 1 (
5 4 3 2
1
2 2
1
FD FD FD FD
FD
in
V V V V D N
V D ND D ND
V N
D
A
+ + + +
+ + -
+

=

)] )( 2 2 (
) 1 2 2 ( ) )( 2 [(
) 1 (
) 2 (
1 1
2 2
2 2
2 1
3
2
D L
T D L
r r D ND D ND
r ND D ND D N r r D N
R D
N
A
+ + +
+ + + -
-
+
=

)] 2 )( 1 (
) )( 2 1 ( 2 [
) 1 (
) 2 (
1 1
1 1
2
3
N C T
T C N T
r r r D
r r r ND D N D Dr
R D
N
A
+ +
+ + + + + -

+
=

)] )( 1 (
) )( 2 1 ( ) 2 [(
1
1 2 5 3 2
1 4
C T N D C C
T C T
r r r r r r D
r r ND D N D r N D
DR
A
+ + + + +
+ + + + - =

R
r r
R D
r ND D ND D N
R
r r r
A
D C C D C N
) (
) 1 (
) 2 1 ( ) 2 ( ) (
5
3 2
3
1
2 2
4 3 2
+
+

+ + +
+
+ +
=

59
In order to state how different duty cycle and turn ratio
influence the efficiency, some parameters are assumed in the
following three cases.
Case1) V
in
=20V, N=1, r
N1
= r
N2
=50m, r
L1
= r
C1
= r
C2
=
r
C3
=30m, r
D1
= r
D2
= r
D3
= r
D4
= r
D5
= r
T
=20m, V
FD1
= V
FD2
=
V
FD3
=0.7V, V
FD4
= V
FD5
=1.2V, R=300.
Case2) V
in
=20V, N=2, r
N1
= 50m, r
N2
=0.2, r
L1
= r
C1
= r
C2
=
r
C3
=30m,r
D1
= r
D2
= r
D3
= r
D4
= r
D5
= r
T
=20m,V
FD1
= V
FD2
=
V
FD3
=0.7V, V
FD4
= V
FD5
=1.2V, R=500.
Case3) V
in
=20V, N=3, r
N1
= 50m, r
N2
=0.45, r
L1
= r
C1
=
r
C2
= r
C3
=30m, r
D1
= r
D2
= r
D3
= r
D4
= r
D5
= r
T
=20m, V
FD1
=
V
FD2
= V
FD3
=0.7V, V
FD4
= V
FD5
=1.2V, R=800.
Fig.9 plots the calculated efficiency under three operating
conditions. One can see that the theoretical efficiency is
improved slightly with increasing turns ratio of the coupled
inductor. But the efficiency will be decreased dramatically
when the duty ratio is larger than 0.7. Therefore, the turn ratio
can be designed as higher as possible under appropriate duty
cycle range if only efficiency is desired. However, it should be
noticed that the increasing turn ratio will result in larger
volume of the coupled inductor and boundary magnetizing
inductance. Furthermore, the bigger magnetic core leads to
more energy loss. As a result, a compromise should be
considered to optimize overall the systems performance.
V. EXPERIMENTAL RESULTS
To demonstrate the effectiveness of the theoretical analysis,
a prototype circuit of the proposed converter is built and tested
in the laboratory. The closed-loop control unit of this circuit is
based on microcontroller (TMS320F2812). The parameters of
the converter are described in Table.1. The key waveforms
operated in C-CCM are demonstrated in Figs. 10-11.
Duty ratio
E
f
f
i
c
i
e
n
c
y

Fig.9 Calculated efficiencyversus duty cycle for different parameters.

TABLE.I
UTILIZED COMPONENTS AND PARAMETERS OF PROTOTYPE
Components Parameters
Maximum output power P 500W
Input voltage
in
V 18-36V
Output voltage
O
V 380V
Switching frequency fs 40/kHz
Turns ratio n2/n1 of coupled inductor
N
13/7
Magnetizing inductor Lm 200H
Leakage inductor Lk1/Lk2 1.7H
Input inductor L1 60H
Power MOSFET Q FQP34N20
Dr/DO(Diodes) FFPF20U50
D1/D2/D3(Diodes) 20ETF02
C1(Capacitor) 470F/100 V
C2(Capacitor) 47F/100 V
C3(Capacitor) 47F/250 V
CO(Capacitor) 470F/ 600V


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10
Fig.10.(a) shows the gate signal of the switch Q and the
current waveforms including the input inductor current i
L1
, the
primary-side current i
LK1
and the secondary-side current i
LK2
of
the coupled-inductor. It can be seen that the input current is
continuous, and this is optimal for the input current ripple
cancellation, dynamic response improvement, and power
device peak current reduction. Fig.10. (b) gives the gate signal
of the switch Q and the measured current waveforms through
C
1
, C
2
, and C
O
, which are agreed well with the theoretical
analysis.
Fig.11 (a) illustrates the gate signal and the voltage stress of
Q, and the output voltage. It can be seen that the voltage stress
of the main switch is far lower level than output voltage when
the main switch turns off. The voltage stress waveforms of the
diodes D
1
, D
2
, D
3
and the output voltage are demonstrated in
Figs.11 (b). It is shown that the voltage stresses of these three
diodes are far lower than output voltage. Fig.11(c) represents
the output voltage, and the voltage stresses of regenerative
diode D
r
, output diode D
O
. The voltage stress of regenerative

(a)


(b)
Fig.12. Experimental current waveforms. (a):Vgs,iL1, iLK1, iLK2.(b): Vgs,iC1,
iC2 ,iCO


(a)


(b)


(c)
Fig.11. Experimental voltage stress waveforms.(a): Vgs Vds,VO ;(b): VD1,
VD2, VD3 ; (c): VDr, VDo, VO.

(a) (b)
Fig.10. Experimental current waveforms. (a):Vgs,iL1, iLK1, iLK2 ; (b): Vgs, iC1, iC2 , iCO.


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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
11
and output diodes is also lower than the output voltage.
In order to verify the feasibility operated in C-DCM, the
experimental waveforms under the light-load are shown in
Fig.12-13. The output power is about 140W.The experimental
results are consistent with the previous theoretical analysis.
Fig. 14 shows the measured efficiency according to the
power variation while maintaining the output voltage
regulation. Maximum efficiency is around 94% at the 270W
load condition and 30V input voltage. The full-load efficiency
is appropriately 91.1%.Another converter in [32] is also tested
under the same turn ratio and input/output voltage for
comparison. Because the low input voltage is applied to these
converters, they should experience very high input current at
full load condition, which leads to high conduction loss during
the switch turn-on period. In order to improve the conduction
loss, one can adopt parallel power devices to share the input
current. In addition, soft switching and interleaved techniques
are also employed to them for higher efficiency [37]-[39].
VI. CONCLUSION
For non-isolated high step-up industry applications, a novel
high voltage gain converter is introduced in this paper, which
combines a quadratic boost converter with coupled-inductor
and diode-capacitor techniques. A clamped-capacitor circuit is
connected to the primary side of the coupled inductor, the
voltage stress of the active switch is reduced greatly and the
clamped capacitor also transfers the primary leakage energy to
the output. At the same time, a diode-capacitor circuit is
integrated with the secondary winding for further extending
the voltage gain greatly. Furthermore, the energy of secondary
leakage inductor can be recycled and the turned off voltage
spikes on the main switch are suppressed. In addition,
compared with some active clamp or three level counterparts,
only one MOSFET is required to simplify the circuit
configuration and improve the system reliability, and the
proposed converter maintains the advantage of continuous
input current.
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Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
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Xuefeng Hu was born in Jiangsu Province,
China, in 1973. He received the M.S degree in
electronic engineering from China University of
Mining and Technology, China in 2001. He has
been working toward the Ph.D. degree in
electrical engineering from Nanjing University of
Aeronautics and Astronautics (NUAA), Nanjing,
China from 2008.
Since 2010, he has been an Associate Professor
in the college of Electrical and Electronic
Engineering, Anhui University of Technology,
Maanshan, China. He is the author or coauthor of
more than 20 technical papers. His current research interests include
renewable energy system, dc-dc power conversion, modeling and control of
the converters, and distributed power system.



Chunying Gong was born in Zhejiang
Province, China, in 1965. She received the
M.S and Ph.D degrees in electrical engineering
from Nanjing University of Aeronautics and
Astronautics (NUAA), Nanjing, China in 1990
and 1993, respectively
From 1984 to 1987, she was an Electrical
Assistant Engineer with Chengdu Aircraft
Design and Research Institute. In 1993, she
joined the College of Automation Engineering,
NUAA, as a Lecturer, where, in 1996 and
2004, she became an Associate Professor and a
Professor, respectively. She has published
more than 80 technical papers in journals and conferences. Her research
focuses on dc/dc converters, static inverters, power electronic systems
stability and power quality, renewable energy, and distributed generation.