COMPUTER ARCHITECTURE &

ORGANIZATION
CHAPTER 3
Von Neumann and Harvard Architecture
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VON NEUMANN ARCHITECTURE
John Von Neumann's: One shared memory for instructions (program)
and data with one data bus and one address bus between processor
and memory.
Instructions and data have to be fetched in sequential order (known
as the Von Neuman Bottleneck), limiting the operation bandwidth
Its design is simpler than that of the Harvard architecture. It is
mostly used to interface to external memory.[1]
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VON NEUMANN MACHINE OPERATION[2]
The Von Neumann consist of five major
component. Thick arrow represent data paths.
Thin arrow represent control path.
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The input unit provides instructions and data to the
system, which are subsequently stored in the Memory
Unit.
The instruction and data are processed by the
Arithmetic and Logic Unit (ALU) under the direction
of the Control Unit.
The result are sent to the Output Unit.
The ALU and control unit are frequently referred to
collectivity as the Central Processing Unit (CPU).
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The execution of a stored program is the most
important aspect of the Von Neumann model.
A program is stored in the computers memory along
with the data to be processed.
Under von Neumann architecture, the CPU can be
either reading an instruction or reading/writing data
from/to the memory. Both cannot occur at the same
time since the instructions and data use the same bus
system
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HARVARD ARCHITECTURE
The Harvard architecture is a computer
architecture with physically separate storage and
signal pathways for instructions and data.
The term originated from the Harvard Mark I relay-
based computer, which stored instructions on punched
tape (24 bits wide) and data in electro-mechanical
counters
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In a computer using the Harvard architecture, the
CPU can both read an instruction and perform a data
memory access at the same time, even without a
cache. A Harvard architecture computer can thus be
faster for a given circuit complexity because
instruction fetches and data access do not contend for
a single memory pathway.
Also, a Harvard architecture machine has distinct
code and data address spaces: instruction address
zero is not the same as data address zero. Instruction
address zero might identify a twenty-four bit value,
while data address zero might indicate an eight bit
byte that isn't part of that twenty-four bit value.
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DIFFERENTIATION OF VON NEUMANN AND
HARVARD ARCHITECTURE.
Von Neumann Havard
Physical
Share a memory and
bus@pathway for program
and data storage.
Separate memory and bus
@ pathway for program and
data storage.
Usage For normal and low
performance purpose and
application.
For high performance
purpose and application.
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Von Neumann Havard
Reading/
writing
data/
instruction
Under pure von Neumann
architecture the CPU can be
either reading an instruction
or reading/writing data
from/to the memory. Both
cannot occur at the same
time since the instructions
and data use the same bus
system.
CPU can both read an
instruction and perform a data
memory access at the same
time, even without a cache. A
Harvard architecture computer
can thus be faster for a given
circuit complexity because
instruction fetches and data
access do not contend for a
single memory pathway.
Economical Economical,because using a
single memory and bus for
both data and instruction.
Not economical,because using
different memory and bus for
data and instruction.
Speed Low speed performance High speed performance
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STRENGTH AND WEAKNESS OF VON
NEUMANN ARCHITECTURE
Strength Weakness
Economical : Share a memory
and bus for data and
instruction.
Low speed to read/write
data/instruction.
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REFERENCES
[1] search for Von Neumann Architecture
http://www.elec.canterbury.ac.nz/PublicArea/Staf
f/hof/p10-embed/p10-tutorial/p12.html
[2]Computer Architecture And Organization; An
Integrated Approach, Miles Murdocca and
Vincent Heuring, John Wiley & Sons,Inc.
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