Challenges for Sub-10 nm CMOS Devices

Tohru Mogami *
Selete, Inc., Tsukuba, Ibaraki 305-8569, Japan
* E-mail: mogami.toru@selete.co.jp
Abstract
Sub-10nm CMOS devices are the critical
issue, because CMOS scaling is going to be
sub-25nm regime. Scaling issues of nano-size
MOSFETs can be discussed on the basis of
sub-10 nm MOSFETs characteristics, which
have been developed and confirmed switching
characteristics and low-temperature character-
istics. Studying device limitation issues and
developing new breakthrough technologies are
required to challenge sub-10-nm CMOS
devices.
1. Introduction
Si-LSIs have been leading in micro-
electronics devices since 1970s. Device
scaling in Silicon MOSFETs has been
producing advantages of performance
improvement in Si-LSIs. However, several
limitation factors are emerging in sub-50 nm
CMOS devices, because of quantum effects,
intrinsic material characteristics, and so on. To
overcome these limitations, studying
ultra-small device characteristics and issues is
very important for scaling MOSFETs. In this
paper, device limitation factors and new
breakthrough technologies will be discussed.
2. Scaling challenges for sub-10nm CMOS
Sub-10 nm gate length MOSFETs have
been developing with a variety of structures.
One of the smallest devices is 5 nm MOSFET
using a bulk silicon substrate1). For that device
process, the notched poly-Si gate shown in
Fig.1 and the channel design with shallow
SDE/halo structure were used. Good switching
character- istics for n-/p-FETs are observed
shown in Fig.2, while DIBL effects become
increase with gate length reduction. For the
subthreshold characteristics of 6 nm gate length
at 2.7 Kelvin, negative-differential trans-
conductance is observed only for low
temperature and low drain voltage, shown in
Fig.3. Peak to valley current ratio is 1.74, and it
decreases with the increase in temperature.
This might be caused the Coulomb blockade by
double-barrier in channel region.
Direct tunneling current between source
and drain can be one of the device operation
limits. Fig.4 shows the subthreshold slope
dependence on temperature for various gate
lengths. At higher temperature, subthreshold
slope is proportional to temperature. This
means that the thermal current is dominant
around 300 Kelvin until 6 nm gate MOSFET.
On the other hand, below 30 Kelvin,
subthreshold slope is almost constant. This is
because the S/D direct tunneling current is
dominant below 30 Kelvin even for 17 nm gate
MOSFET. Furthermore, it has been reported
that S/D-direct tunneling currents depend on
gate length, gate voltage, temperature and drain
voltage. Fig.5 shows the subthreshold slope
dependence on drain voltage for n-/p-FETs at
30 Kelvin, in which the tunneling current
should be dominant. Drain voltage lowering
reduces the subthreshold slope. This result
indicates that the control method of the direct
tunneling may be the drain voltage reduction
with gate length shrinkage.
In order to clarify the S/D direct tunneling
current behavior in the drain current at 300 K,
the transport simulation was carried out.2)
Figure 6 shows the simulated subthreshold
characteristics of both drain currents and
tunneling currents at various temperatures in
0.8 V drain voltage for the nMOSFETs with
6-nm gate lengths. It is obtained that the
temperature enhances not only the thermal
current but also the S/D direct-tunneling
1-4244-0161-5/06/$20.00 2006 IEEE
currents. This can be due to the
direct-tunneling currents of higher-energy
electrons through a thinner potential barrier.
Figure 7 shows the calculated results at various
drain voltages for 6 nm gate length at 300 K.
This shows that the ratio values of tunneling
current decrease with the decrease in the drain
voltage. Therefore, it is shown that the S/D
direct-tunneling currents strongly depend on
not only the gate length but also the
temperature, drain- and gate-voltages. In order
to suppress the tunneling behavior, it is
important to reduce the supply voltage even
under the room temperature.
3. Summary
Transport properties of sub-10-nm planar
bulk MOS-FETs were discussed. It was found
that direct-tunneling currents between source
and drain (S/D) regions depend on not only the
gate-length, but also drain voltage for sub-10
nm CMOS devices at low temperature. A
quantum mechanical simulation shows that the
tunneling currents increase with the increase in
the temperatures and gate voltages, resulting in
the significant contribution to the subthreshold
current even at 300 K. Therefore, it is strongly
required that the supply-voltage should be
reduced to suppress the drain-induced
tunneling modulation effects for the sub-10 nm
CMOS devices even under the room-
temperature operations.
References
[1] H. Wakabayashi et al., IEDM Tech. Digest,
p.989, 2003.
[2] H. Wakabayashi et al., IEDM Tech. Digest,
p.429, 2004.
Fig.1 Cross sectional SEM of 5 nm gate MOSFET
20 nm
Gate
SiN SW
SiO
2
liner
Si-sub.
20 nm
Gate
SiN SW
SiO
2
liner
Si-sub.
10
0
10
1
10
2
20
40
60
80
100
200
400
600
800
Temperature T [K]
S
u
b
t
h
r
e
s
h
o
l
d

s
l
o
p
e

[
m
V
/
d
e
c
.
]
V
ds
= 0.8 V
17 nm
11 nm
L
g
= 6 nm
nMOS
S

T
:
t
h
e
r
m
a
l
c
u
r
r
e
n
t
3
0

K
3
0
0

K
0.0 0.5 1.0
20
40
60
80
100
200
400
600
800
Drain voltage |V
ds
| [V]
S
u
b
t
h
r
e
s
h
o
l
d

s
l
o
p
e

[
m
V
/
d
e
c
.
]
T = 30K
17 nm
11 nm
L
g
= 6 nm
nMOS
pMOS, L
g
= 8 nm
0.0 0.5 1.0
20
40
60
80
100
200
400
600
800
Drain voltage |V
ds
| [V] Drain voltage |V
ds
| [V]
S
u
b
t
h
r
e
s
h
o
l
d

s
l
o
p
e

[
m
V
/
d
e
c
.
]
T = 30K
17 nm
11 nm
L
g
= 6 nm
nMOS
pMOS, L
g
= 8 nm
1.5 1.0 0.5 0.0 0.5 1.0 1.5
10
9
10
8
10
7
10
6
10
5
10
4
10
3
Gate voltage V
g
[V]
D
r
a
i
n

c
u
r
r
e
n
t

I
d

[
A
/

m
]
light halo
L
g
= 5 nm
|V
d
| = 0.05, 0.10,..., 0.40 V
0.0 0.1 0.2
0
100
200
300
400
500
Gate voltage V
gs
[V]
S
o
u
r
c
e

c
u
r
r
e
n
t

I
s

[
p
A
/

m
]
L
g
= 6 nm
V
ds
= 0.1 V
2.7 K
5.0 K
1
0
K
3
0
K
5
0
K
PVCR
@ 2.7 K
= 1.74
100 K w/o NDT
5
0
K
3
0

K
1
0
K
5.0 K
Fig.2 Id-Vg characteristics for 5 nm n-/p-FETs
Fig.3 Negative differential Is-Vg characteristics
Fig.5 Subthreshold slope vs. Drain voltage Fig.4 Subthreshold slope vs. Temperature
1.0 0.5 0.0 0.5 1.0
10
12
10
11
10
10
10
9
10
8
10
7
10
6
10
5
10
4
Gate voltage V
gs
[V]
D
r
a
i
n

c
u
r
r
e
n
t

I
d

[
A
/

m
]
L
g
= 6 nm
V
ds
= 0.8 V
3
0
0
K
1
0
0
K 3
0
K
5
0
K
Dash: tunnel
Solid: drain current
1.0 0.5 0.0 0.5 1.0
0.0
0.1
0.2
0.3
0.4
0.5
Gate voltage V
gs
[V]
I
d
t
u
n
n
e
l

/

I
d
L
g
= 6 nm
V
ds
= 0.8 V
0.4 V
0.1 V
T = 300 K
Fig.6 Simulated tunneling drain current vs.
gate voltage.
Fig.7 Simulated tunneling drain current vs.
gate voltage.