Progress In Electromagnetics Research Symposium Proceedings, Suzhou, China, Sept.

1216, 2011

541

A Broadband Low Noise Amplifier for X-band Applications

Cheng-Chi Yu1 , Jiin-Hwa Yang2 , Hsiao-Hua Yeh1 , and Lien-Chi Su1
1

Department of Communications Engineering, Feng-Chia University

No. 100, Wen-Hua Rd., Seatwen, Taichung 407, Taiwan, R.O.C.
2
Ph.D. Program in Electrical and Communications Engineering, Feng-Chia University
No. 100, Wen-Hua Rd., Seatwen, Taichung 407, Taiwan, R.O.C.

Abstract A broadband low noise amplifier (LNA) for X-band (812 GHz) applications is
proposed in this study. The proposed LNA circuit is composed of three-stage NMOS transistors
which construct a cascade configuration. The design can achieve wide-band matching and higher
gain at the same time. The proposed LNA chip is fabricated by TSMC 0.18 m CMOS process.
The chip occupies a die area of 0.45 mm2 (0.73 mm 0.62 mm) only. On-wafer measurement was
used to measure the characteristics of the LNA. The measured results show that gain (S21 ) of
15.15 20.05 dB, noise figure (NF) of 2.9 3.1 dB are obtained. The total power consumption
is 12.45 mW under a power supply voltage of 0.75 V. The good performances of the LNA make
it suitable for X-band applications
1. INTRODUCTION

The high sensitivity X-band (812 GHz) receiver is an important device for wireless communication
application such as radar and satellite communication. The X-band systems are widely used in
military radar and aircraft [1]. Low noise amplifier (LNA) is one of the most important building
blocks in front end of communication systems. It is a key component that provides good input
return loss, low noise figure and good linearity for the receiver. Low voltage, low power, and good
performances are always targets of LNA design, especially for radar applications. At high frequency,
the parasitic affect the circuit performance greatly. To find a good architecture is essential that can
fit demand and provide a good performance for X-band LNA This paper demonstrates a three-stage
cascade configuration X-band broadband LNA design by TSMC 0.18 m CMOS process
2. CIRCUIT DESIGN AND ANALYSIS

The complete schematic of the proposed LNA is shown in Fig. 1. This circuit is a three-stage NMOS
transistor architecture It is constructed by a cascade configuration which is adopted to enhance
the bandwidth. For producing the 812 GHz operating frequency range of the proposed LNA, the
operating frequencies of first, second and third stages are designed at 8 GHz, 10 GHz and 12 GHz,
respectively. The three-stage architecture can achieve wide-band matching and higher gain at the
same time [2]. The source inductor is used to improve impedance matching in this circuit [3].
Furthermore, in order to reduce chip area, the authors self-layout mutual coupled inductor [4]
which combines with source inductors of MOS1 and MOS2 is presented in this design to replace
the conventional structure of the CMOS process. And the circuit only uses two supply power pads
on one side. That can save the area of supply power pad on other side. An obvious size reduction
is obtained by these topologies. The proposed LNA chip is fabricated by TSMC 0.18 m CMOS

Figure 1: Schematic of the proposed broadband LNA.

Figure 2: Photograph of the X-band LNA.

PIERS Proceedings, Suzhou, China, September 1216, 2011

542

process. The die photograph of the LNA is shown in Fig. 2 The chip only occupies a die area of
0.45 mm2 (0.73 mm 0.62 mm).
3. EXPERIMETAL RESULTS

The proposed LNA was simulated by ADS simulator. The simulated S-parameters are shown in
Fig. 3. The simulated and measured results of the LNA are summarized in Table 1. The simulated
and measured results have a good agreement. The LNA requires only a 0.75 V supply voltage and
consumes 12.45 mW powers. The circuits -factor is more than 1 which means that the circuit is
unconditional stable in the operating frequency. The simulated and measured power gain is shown
in Fig. 4. Between the operating bandwidth of 812 GHz, the proposed LNA has power maximum
gain of 2005 dB, noise figure (NF) of 2.9 3.1 dB, with input return loss between 10.5 to 9.7 dB
and output return loss less than 1 dB. The proposed LNA exhibits a good performance of gain,
noise and chip size.

30

25

20

20

10

15
10

-10

Gain (dB)

Magnitude (dB)

0
-20
-30
-40
-50

5
0
-5
-10

-60

-15

S11 [dB]
S22 [dB]
S21 [dB]
S12 [dB]

-70
-80
-90

-20
Sim
Meas

-25
-30

10

12

14

16

10

12

14

16

Frequency (GHz)

Frequency (GHz)

Figure 3: Simulated S-parameters of broadband low

noise amplifier.

Figure 4: Simulated and measured results for power

gain of broadband LNA versus frequency.

Table 1: The performance of proposed broadband LNA.

Broadband Low-Noise Amplifier
Vdd1 / Vdd2 (V)

0.75 / 0.75

Technology

Simulation

Measurement

Operating Frequency (GHz)

8 12

8 12

Power Gain (dB)

18.5 1.5

17.6 2.45

Input Return Loss (dB)

< 10

10.5 ~ 9.7

Output Return Loss (dB)

< 10

< 10

Isolation (dB)

< 40

< 40

Noise Figure (dB)

2.8 ~ 3.3

2.9 ~ 3.1

Pin,1dB (dBm)

24 @ 8 GHz
20 @ 10 GHz
19 @ 12 GHz

27 @ 8 GHz
23 @ 10 GHz
19 @ 12 GHz

Stability

Unconditional
Stability

Unconditional
Stability

12.45

12.45

Power consumption (mW)

2

Chip size (mm )

0.73 * 0.62 = 0.45

Progress In Electromagnetics Research Symposium Proceedings, Suzhou, China, Sept. 1216, 2011

543

4. CONCLUSION

A Broadband LNA for X-band application has been proposed. The circuit is composed of a threestage NMOS transistor architecture which is constructed by a cascade configuration. The threestage architecture can achieve wide-band matching and higher gain. Using the authors self-layout
mutual coupled inductor and two supply power pads on one side of the circuit design can efficiently
reduce the chip size. The results of proposed wideband LNA have a good agreement between
simulated and measured results.
ACKNOWLEDGMENT

The authors would like to thank National Chip Implementation Center (CIC) for chip implementation and measurement support.
REFERENCES

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