Lab for VHDL 101

Rev 1.0 6/16/2011

Introduction:
This lab supports the book VHDL 101 Everything you need to know to get
started. In addition to providing some of the source code used in the book, a
detailed explanation of the thought process and various higher level diagrams are
provided to help the reader understand the nature of designing for FPGAs rather
than just the mechanics of coding. This lab will introduce the concept of designing
from specification, some additional testbenching, and implementation on a demo
board. Although during the development cycle each module was independently
tested, the discussion of the testing is omitted from this document as it becomes
quite verbose. The individual testbenches for the lower level modules are included
in the downloadable file set for your review.
The Design Overview:
Successful designs start from a specification. The specification describes exactly
what (but not how) the design is to behave, and in some cases how the design is
NOT going to behave.
Although this design is elementary enough to be run on virtually any demo board,
this design is targeted to the Avnet Spartan-6 FPGA LX9 Microboard. This board was
chosen for its low cost and small physical size. Other boards manufactured by Xilinx,
Avnet, or Digilent would work equally as well and would only require a change to the
User Constraint File1 (UCF) to run properly.
The design for this lab leverages the UART and debouncer modules presented in the
book. The overall function of the design is to processes user data via the RS-232
serial connection. If a character is a lower case alpha character, the design will
return the capitalized form of that letter and light the lower order LED (the lower
order LED is lit for any alpha character). If the character is an upper case alpha
character, the design will return the lower case form of that letter and light the
lower order LED. If the character is a symbol, the symbol will be echoed back to
the user and both LEDs on the board will light. If the character is a numeric, then
the higher order LED will light and the numeric will be returned. If no character is
received for 1 second, then the LEDs will de-illuminate.
There are four DIP switches present on this board. If there is a change in the value
of the DIP switches, the numeric value of the new settings will be transmitted to the
user via the RS-232 link. That is, if the DIP switches are changed to 0110, then the
FPGA would send a numeric character 6 to the user.
1

The User Constraint File contains information regarding the physical aspect of the design as
it resides in the FPGA. Pin locations, timing constraints, and placement information is kept in
this file.

Specifications:
The following specifications are based on the high-level description presented
above. Each major specification is indicated with an integer and details
supporting that specification are provided as decimals under that integer.
During the processes of coding and writing test-benches, these numbers will be
referred to so that we know that all testable aspects of the design are covered. If
our specifications are well written and thorough, this will virtually guarantee that
our design will run as expected the first time we download it into the FPGA.
Although specifications are not the most exciting read, please pay close attention to
the use of shall which indicates that the design must absolutely and in all
circumstances (unless otherwise indicated) perform this behavior, while may
indicates that the design is allowed to perform this behavior, but is not required to.
1. The design shall communicate with a host device using an RS-232 serial
communication link.
1.1.The supported baud rate shall be 19,200 baud.
1.2.Eight (8) data bits shall be supported.
1.3.One (1) stop bit shall be supported.
1.4.No parity shall be supported.
1.5.The RS-232 serial communication link may be replicated via USB 2.
2. The design shall drive two LEDs as status monitors
2.1.The lower order LED shall illuminate for 2 seconds when either an alpha
character or symbol is received via the RS-232 communications channel.
2.2.The higher order LED shall illuminate for 2 seconds when either a numeric
character or symbol is received via the RS-232 communications channel.
2.3.When no information has been received for at least 1 second both LEDs shall
beunlit.
3. The design shall monitor four DIP switches.
3.1.Each switch shall be debounced3 for at least 50 ms.

USB Universal Serial Bus. Traditional RS-232 D type connectors are quite bulky and
require voltages typically no longer found on many demo boards. The Avnet LX-9 board
converts the RS-232 protocol into USB for higher speeds and smaller connectors.
3
When a mechanical switch is thrown, two pieces of conductor must either separate or
come together. This contact or breaking of contact often results in some vibration or
mechanical imperfections which cause the signal to ring or oscillate for some period of
time usually on the order of 100 us to 10 or more milliseconds depending on the quality of
the switch. A debouncing mechanism eliminates this ringing (which is seen by digital
circuitry as a stream of alternating 1s and 0s until the bouncing ends and a clear 1 or 0
emerges). An RC (resistor-capacitor) filter can be used as a first order low-pass filter which
provides a gradual rise or fall in voltage until the capacitor is full charged or discharged. This
technique relies on the input circuitry to threshold the voltage into the proper digital state.
While adequate for many needs, the presence of additional components on a board is
typically not welcome and the charging constants can only be changed with new
components and a soldering iron. Digital debouncing removes the need for external
components and costs only a little bit of logic inside the FPGA.

3.2.When a change is detected in the DIP switch settings, the hexadecimal

equivalent to the DIP switches shall be sent via RS-232 communications
channel.
4. Each character received shall be echoed with its inverse capitalization
4.1.If a capital letter is received, then the echo will be the lower-case letter
4.2.If a lower-case letter is received, then the echo will be the capital letter
4.3.If the character received is not a letter, then it is echoed with no modification
5. Higher speed modules shall have higher precedence than lower speed modules
5.1.If a character being echoed back arrives in the same clock cycle as a change
in the DIP switch, then the echoed character shall take precedence.
From this specification we can see that several modules are going to be required
1)
2)
3)
4)

A
A
A
A

UART module for managing serial communications via the RS-232 port
mechanism that recognizes received values from the UART and drives LEDs
debouncer for each DIP switch.
means of coding the DIP switch to:
a. Recognize that the DIP switch has changed
b. Collect the 4 DIP switch values and convert to an ASCII pattern for
transmission
5) Finally, a module that ties all of these together.
Now that we have a basic idea of what we need, well need to see how its all strung
together

Figure 1 Design Block Diagram

As we saw in the book (see Table 3.13 and corresponding section), we can start the
coding process by defining the interfaces for each module beginning at the top
level. Remember that the top level of the design becomes the pins on the FPGA.
While explicitly declaring buffers with specific capabilities is possible, for simplicitys
sake we will use the intrinsic ability of the Xilinx Synthesis Tools (XST) to
automatically insert the right type of buffer.

Everything that pierces the dotted line represents the outside world (i.e. not in the
FPGA) . Input and Output in the table below are from the FPGAs perspective
(that is, an input is a signal coming from off-chip into the FPGA). From this we
derive the following table

Signal
Name

Type

reset
clk

std_logic (input)
std_logic (input)

serialDataIn

std_logic (input)

serialDataO
ut
LED_hi
LED_lo
DIP

std_logic (output)
std_logic (output)
std_logic (output)
std_logic_vector(3
downto 0) (output)

Significance
Reset signal from on-board button
40 MHz signal from one of the on-board
sources
Data arriving via the RS-232/USB
interface
Data being sent to the RS-232/USB
interface
High order LED
Low order LED
4 lines coming from the DIP switch

Table 1 - Interface Description for the Top Module

The next module is that of the UART. Since weve covered the details in the book,
well just copy the interface information here with no further explanation regarding
either the UART or the subordinate modules it contains.
Since this component is completely contained within the top module, inputs and
outputs are all contained within the FPGA. Even though some of the signals pierce
the FPGA-outside world boundary, they are buffered through the top module.

Signal
Name

Type

reset
clk
serialDataIn

std_logic (input)
std_logic (input)
std_logic (input)

parallelData
Out
dataValid

std_logic_vector (7
downto 0) (output)
std_logic (output)

parallelDataI
n
transmitRequ
est

std_logic _vector(7
downto 0) (input)
std_logic (input)

ready

std_logic (output)

Significance
Reset signal from on-board button
40 MHz signal
Data arriving via the RS-232/USB
interface
De-serialized data which arrived via the
RS-232/USB interface
Indicates when parallelDataOut becomes
valid
Data to serialize for transmission via the
RS-232/USB interface to the user
Single pulse to begin transmitting the
data on parallelDataIn. Note: ready must
be de-asserted when transmitRequest is
asserted or the data will not be sent.
Indicates that the transmitter module
within the UART is not busy (i.e. ready to
begin a new transmission).

serialDataOu
t

std_logic (output)

Data being sent to the RS-232/USB

interface

Table 2 - Interface Description for the UART4

The Character Decoder module is responsible for receiving data from the UART
receiver and deciding what to do with it. At this point in the development the how is
going to be deferred and we will focus only on the signal interface. From Figure 1 we
have

Signal Name

Type

clk
charFromUART_v
alid
charFromUART

std_logic (input)
std_logic (input)

LED_hi

std_logic _vector(7
downto 0) (input)
std_logic (output)

LED_lo

std_logic (output)

send_character
character_to_sen
d5

std_logic (output)
std_logic _vector(7
downto 0) (output)

Significance
40 MHz signal
Indicates when parallelDataOut
becomes valid
Data to serialize for transmission via
the RS-232/USB interface to the user
Asserts when received character is a
numeric character or symbol
Asserts when received character is an
alpha character or symbol
Asserts when character_to_send is valid
Character to echo to the user

Table 3 - Interface Description for the Character Decoder

Since the specification requires that something needs to be timed, a generic

containing the provided clock frequency should be passed into the module. The
module can then do whatever calculations are necessary to provide the requested
timing.

Generic
Name
CLOCK_FREQUE
NCY

Type
integer

Significance
Frequency of the clock in Hertz.

Table 4 - Interface Description for the Generics for the Debouncer

Continuing to the Character Encoder module

Signal
Name
clk
send_characte
r
character_to_s
4
5

Type

Significance

std_logic (input)
std_logic (input)

40 MHz signal
Asserts when character_to_send is valid

std_logic _vector(7

Character to echo to the user

Table 3.13 in the book is missing the ready signal

Absent from block diagram due to space and readability limitations

end
tx_ready

downto 0) (input)
std_logic (input)

parallelDataIn

std_logic _vector(7
downto 0) (output)
std_logic (output)

transmitReque
st
DIP_dbncd

std_logic _vector(3
downto 0) (input)

High when UART ready for new character

to transmit
Data to serialize for transmission via the
RS-232/USB interface to the user
Single pulse to begin transmitting the
data on parallelDataIn. Note: ready must
be de-asserted when transmitRequest is
asserted or the data will not be sent.
Debounced DIP switch values

Table 5 - Interface Description for the Character Encoder

Finally, the interface table for a single debouncer module. This module will be
replicated four times, one for each switch.

Signal
Name

Type

clk
signal_in
signal_out

std_logic (input)
std_logic (input)
std_logic (output)

Significance
40 MHz signal
Asserts when character_to_send is valid
Character to echo to the user

Table 6 - Interface Description for the Debouncer

The debouncer can use one additional piece of information how long to debounce?
This information can be passed to the debouncer as a generic. In order for the delay
value to be interpreted correctly, the frequency of the clock must also be passed to
this component.

Generic
Name

Type

DELAY_VALUE

integer

CLOCK_FREQUE
NCY

integer

Significance
Indicates the number of clocks that an
incoming signal must be stable before
the output changes.
Frequency of the clock in Hertz.

Table 7 - Interface Description for the Generics for the Debouncer

At this point in the design process, all of the module ports have been defined. These
sources can be found in the following files: top_level_ports_only.vhd,
uart_ports_only.vhd, character_decode_ports_only.vhd,
character_encode_ports_only.vhd, and debouncer_ports_only.vhd.

From here filling in the detailed behavior of each module should be performed.
Following the same order of description from above, we have
Lab Design Top

The lab_design_top module shall be a structurally coded module which connects the
UART, character_decoder, character_encoder, and debouncers together and
connects them to the physical pins of the FPGA.
The ability to insert the proper buffers on the ports by the Xilinx Synthesis Tool
(XST) shall be leveraged; therefore, no explicit buffer definitions are required.
The modules shall be connected according to the Design Block Diagram (Figure 1)
above.
UART
The UART module and subordinate modules are thoroughly described in the book
VHDL 101 and are not repeated here.
Character decoder
The character decoder module is responsible for receiving an 8 bit ASCII encoded
character from the UARTs receiver module. This data is valid when the signal
dataValid is asserted (high). Upon receipt of a valid character the character_decoder
module must categorize the data into one of three groups: alpha character, numeric
character, or symbol character. If the character is an alpha character then LED_lo
shall be illuminated for 10 seconds. If the character is a numeric character, then
LED_hi shall be illuminated for 10 seconds. If the character is a symbolic character
then both LED_hi and LED_lo shall be illuminated for 10 seconds.
The time specification implies a timer based on the incoming clock.
Based on the description above, the character decoder module shall be constructed
as follows:

Figure 2 Initial Character Decoder Module Block Diagram (not complete)

The decoding_table process shall be written as a process which takes the character
(when charFromUART_valid is asserted) and makes the request to the LED control
process as to which LEDs should be illuminated. When the character is decoded, the
timer shall be reset regardless of if a previous character was received within 10

second ago. The LED control module shall illuminate the requested LEDs then
discontinue after 10 seconds.

The second responsibility of the character decoder is to reverse the capitalization of

the characters received and pass them to the character encoder. This expands the
block diagram as follows:

Figure 3 - Updated Character Decoder Module Block Diagram

Now that the processes and connecting signals have been defined, this module can
be coded along with its test bench. See character_decoder.vhd and
character_decoder_tb.vhd.
Character Encoder
The main responsibility of the character encoder is to first monitor the state of the
DIP switches. If a change is seen then it must generate an ASCII hexadecimal
character and transmit it. It must also transmit any characters indicated by the
character decoder module. This leads the module to appear as:

Figure 4 - Character Encoder Block Diagram

Since there are two requesters and only one transmitter, there is a possibility of a
data collision; therefore, some type of collision avoidance or collision recovery
scheme is necessary. Since a human is controlling the DIP switches, it is a fair
assumption that this will occur very infrequently, certainly less than once per
character transmitted therefore, adding a single buffer to capture the new DIP
data is probably sufficient6. This buffer will hold the new value from the DIP switch
until the transmitter becomes ready.
Similarly, a buffer can be placed on the character_decoder side as well to provide a
single character hold. There is a bit more of a concern here as serial data can
(although it is unlikely) be streamed requiring the transmitter to transmit every
character as it arrives just to keep up with the incoming serial data. If the DIP switch
is changed during this time, then the new DIP switch value will be queued in its
buffer, but never have a chance to transmit until the serial stream abates.
This is an unlikely situation so we can assume 7 that this condition wont occur and
single buffer each incoming port.
The selector module must immediately buffer any characters being echoed (i.e.
coming from the character decoder module) and any character arriving from the DIP
encoder. A priority scheme can be developed so that echoed character have the
right of first refusal to be transmitted. That is, if there are both pending requests
from the character decoder and the DIP encoder, then the character decoder will
take precedence as serial data is anticipated to arrive more quickly than DIP
switches changing.
The selector module shall monitor the ready signal from the transmitter and
transmit any characters from the character decoder. If there is no character present,
then the selector module will pass a character from the DIP encoder. If there is no
character present, then the selector module waits for the next character to arrive
from either source. If both sources present on the same clock cycle, then the
character decoder shall take precedence. (Thus meeting Specification 5 and 5.1)

Debouncer
The debouncer is an adjustable mechanism which removes ringing from
mechanical switches and buttons. The basic operation is that each time a change is
seen on the input to the debouncer, a counter is restarted. The duration of that
6

The specification could be improved to cover this case which would describe how many DIP
switch changes must be buffered.
7
Assumptions are usually deadly as they are typically not documented! This assumption is
DOCUMENTED so that anyone reading this design description will understand that this was
a considered situation and should not occur in this way.

counter is programmable and is set to 100 ms. The general practice for selecting
the timing constant is to connect the switch to a digital sampling oscilloscope and to
trigger on movement in voltage. The trace will clearly see the ringing and measure
the time. Often several buttons or switches of the same type are tested and the
worst case values are selected.

Figure 5 - testing a switch for ringing

The debouncer will ensure that the incoming signal is stable (either high or low)
before the output of the debouncer changes.
Lab for Using the Xilinx Tools:
1. Acquiring, Installing, and Launching the Xilinx Project Navigator Tool (webpack
version)
1.1.Open a browser and navigate to http://www.xilinx.com/tools/webpack.htm
1.1.1. Click download
1.1.2. Select ISE Design Suite 13.1 Full Product Installation > All Platforms

Figure 5 - Xilinx Webpage to download WebPACK

Note: you may download either the Windows or Linux version, or the combined
version.
1.1.3. Once downloaded, launch the installer. Accept the default choices.
1.2.Please unzip the source files to an easily accessible location. These source
files will be imported into PlanAhead so that simulation and
implementation can be run. Remember this location!
2. Creating a Project in PlanAhead. Begin by launching PlanAhead by doubleclicking on the desktop icon, or Start > All Programs > Xilinx Design Suite
13.1 > PlanAhead > PlanAhead
A. Create a new PlanAhead project by first selecting Create New Project at the
welcome screen. This will walk you through the process of creating a new
project including the selection of the device, adding sources, etc.
a) Select Create New Project

Figure 6 - Selecting "Create New Project" from the PlanAhead Welcome Screen

b) The initial dialog box is a welcome screen which begins the Create New
Project wizard. Click Next >.

Figure 6 - Create New PlanAhead Project Wizard Welcome Screen

c) The first dialog screen of the actual wizard asks you to select a project
name and location for this project. Please name this project VHDL101_lab.
You are free to place the project wherever you wish. If you choose to use

names and locations other than what is shown in the next screen shot,
please take note of them for later use.
Enter a project name and location, then press Next

Figure 8 - Select a name and location for your PlanAhead project

Click Next >.

d) The next dialog which appears asks which type of project you will be
creating. Since the VHDL sources are presented to you choose Specify
RTL Sources.

Figure 9 Specifying Type of Project

Click Next > .

e) Next you will be able to select the sources to use for this project. Click
Add Files

Figure 10 Dialog Box for Selecting VHDL Source Files to Import

f) Navigate to where you unzipped the source files. Select all source files
and click OK. When complete, the Add Sources dialog box will open.
Change the HDL Sources for to Simulation Only for all sources ending
in _tb (which refers to all the testbench files). Click Next when done.

Figure 11 - Listing of Selected Sources

g) The next dialog box invites you to add any IP (black box modules) to the
project. Since this project does not require any, click Next >.

Figure 12 - Addition of IP Dialog

h) The following dialog box invites you to add any User Constraint Files to the
project. The UCF contains timing and pin location information which is
necessary for the successful implementation of the design. A suitable UCF
for the Avnet LX-9 board has been provided for you. Select this file and
click Next.

Figure 3 - Addition of Constraints File to Project

i) Next you will select which part will be targeted. The Avnet LX-9 board
which uses a XC6LX9CSG324-1. Using the pull-down menus select General
Purpose > Spartan6 > Spartan6LX > CSG324 > -1. The following screen
shots will walk you through this process. Alternately you can type
XC6SLX9CSG324-2 into the search box and click Next to continue to the
summary screen, then Finish to complete the project creation.

Figure 147 - Selecting the Spartan 6 Family

Figure 15 - Selecting "General Purpose" and Spartan-6 to the Parts Filter

Figure 16 - Selecting the Sub-Family of Spartan 6

Figure 17 - Project Summary Screen

3. Simulation
A number of the sources imported in the previous step are not synthesizable they
are intended for simulation only. There are a number of test-benches included for
this as well as modules which support simulation. All of these files must be marked
as simulation files which was done during the importing step. If you missed any, the
source can be marked for simulation by selecting the file name, right-clicking, and
selecting move to simulation source from the pop-up menu.
There are a number of simulation files these were used to validate various
modules during development and are provided here for your reference. We will
concern ourselves here with only the top level testbench.
a) Begin simulation by selecting Behavioral Simulation from the Project
Manager tab on the far left selection menu.

Figure 88 - Selecting Behavioral Simulation in PlanAhead

b) Once selected, the Launch Behavioral Simulation dialog box will open.

Figure 99 - Launch Behavioral Simulation Dialog Box

Ensure that lab_design_top_tb is selected. You may have to browse to

locate this file. Click Options.
The Options window allows you to select the options for the simulation.
1) The full testbench takes about 2.5 seconds to exercise all of the test
scenarios, so next to Simulation Run Time type in 2500 ms.
2) You should also modify the wcfg (specify waveform Configuration File)
field to select lab_design_top_tb.wcfg which contains an organized signal
list for ease of debugging and analysis. This is done by double clicking in
the wcfg value field and browsing to the file by clicking the down arrow in
that field.
3) Click OK to accept these changes.

Figure 20 - Simulation Options Dialog Box

c) Click Launch to run the simulation with the selected options. The simulation
may take a few minutes depending on the type of computer you are running.
d) Expand the Board Signals group by clicking on the hierarchy arrow next to the
Board Signals name. This will show all the signals in this group.
e) Zoom out to show the entire 2.5 second simulation by either clicking the
icon or selecting View > Zoom > Zoom to full View.
Heres an explanation of what you are seeing:
View 1 Full Zoom Out
Notes the initial portion of the simulation (times 0 to 50 ms) exercise the serial
communication requirements and LED responses. Beginning at or near 400 ms the
DIP switches are exercised until about 2,200 us.

Figure 21 - ISim - Overall Simulation View

When you zoom to the range 1ms to about 45ms you can see the sequence of serial
character sent into the FPGA and the sequence of serial characters leaving the
FPGA. Note that other groups have been expanded to see key signals.

Figure 22 - Serial Input Sequence

Zooming in even further you can see the individual serial bits being converted into
character bytes.

Figure 23 - Serial Receiver Details

Finally, after the last character received, the LED Timer begins its final countdown
which completes at about 1300ms which causes the LEDs to turn off.

Figure 24 - LED Timeout Test

As an aside play with the ISim simulation tool it has many, many powerful
features including the relaunch feature which allows you to recompile and re-run
the simulation when you make changes to the source while in the ISim tool. Any
source can easily be reached by expanding lab_design_top_tb in the Instances
and Processes panel on the far left.
4. Implementation
Implementation is the process of converting the source code to a bitstream
which can be downloaded (Step 5) to the board. Two things to keep in mind
during the implementation phase make certain your User Constraint File(s)
(UCFs) are present (and correct) and that there are no timing errors.
The UCF(s) contain physical information regarding your design how fast it
should run, which signals attach to which pins, and if necessary, where certain
items are located inside the FPGA (floorplanning).
Timing Errors occur when there is not enough time for a signal to get from one
portion of the design to another. The tools report this in several places; the
easiest location to view this information is in the project summary.
The process of both writing good UCFs and achieving timing closure (making
certain that there are no timing errors) is a non-trivial matter and is handled
excellently in Xilinxs 2-day instructor led training Designing for Performance.

a) Ensure that the UCF is listed in the Project Hierarchy

b) Launch implementation by clicking on the IMPLEMENT icon on the Project
Manager control bar on the far left. The tools are smart enough to
regcognize that the sources have not yet been synthesized and will ask you
to launch synthesis. Click OK. You will be asked for the top module name
select lab_design_top and click OK to close the selection and OK to launch
synthesis and implementation.
c) Open the implemented design when prompted.
d) Select Program and Debug and choose Generate Bitstream from the list.

Figure 25 - Beginning the Generate Bitstream Process

e) This opens the Generate Bitstream Options Dialog Box. You may choose to
leave the options in their default settings, or you may add a User ID code as
shown in the screenshot below. The User ID is often used to stamp a
bitstream to confirm that the desired bitstream was downloaded to the part.
Note that the 8 hex digit User Code below shows the date that the bitstream
was created (6 hex digits) plus a count code which can be used to indicate
a sequential number to distinguish one bitstream from another when created
on the same day.
Click OK to begin the bitstrem generation process.
f) When the bitstream generation process is complete, a dialog box will appear
to let you know that the process has completed. Click OK.

Figure 26 - Generate Bitstream Option Dialog Box with User ID Enabled

5. Downloading the Bitstream

The final phase is to take the completed bitstream and download it to the target
board.
Physical Connection
First, the Avnet LX-9 board needs to be connected to the computer that you
will use to download and verify with. There are two connections required: (1)
the USB-JTAG connection (shown on the left in the figure below) and (2) the
USB-RS-232 connection.

Figure 27 - Avnet LX9 Board

The USB-JTAG connection is found on the tapering end of the board. This
slides into any available USB slot on your computer. You may wish to put this
on a USB extension cable or hub so that you have easy access to the LEDs
and DIP switches.
The USB-RS-232 connection is made using a USB A/micro-B cable to the
micro-B USB connector located next to the large RJ-45 Ethernet connector.
The A side of the cable goes to your computer.
Power for the LX-9 board is provided through either of these cables.
Tool Connection
The tool connection consists of two aspects. First, additional software must be
installed on your machine to support the programming interface. Software
download and instructions can be found here:
http://www.digilentinc.com/Products/Detail.cfm?
NavPath=2,66,768&Prod=DIGILENT-PLUGIN
a) Once the programming software for this board is installed, you can launch
Xilinxs programming tool: iMPACT by expanding the Program and Debug
entry on the left side of the display and double-clicking iMPACT.

Figure 2810 - Lauching iMPACT from PlanAhead

An error in connecting the cable dialog box will likely appear. Click OK to
acknowledge the problem. This will be fixed in the next step.
b) Since the LX-9 uses the Digilent programming hook, you will need to
designate a different cable then the default. This is initiated by selecting
Output > Cable Setup from the iMPACT menu line.

Figure 29 - Selecting Cable Setup in iMPACT

c) The Cable Setup dialog box invites you to choose how the download cable is
connected to the PC. Check the Cable Plug-In check box and either type or
select from the pull-down menu digilent_plugin. This will select the Digilent
Inc. communications software.

Figure 30 - iMPACT Tool Cable Setup

d) Click OK. iMPACT will now find the cable and connect to it.
e) Discover what is connected via the JTAG chain by clicking File > Initialize
Chain. All JTAG devices will appear in the work area. Click OK to confirm.
f) Right-click on the only FPGA in the chain xc6slx9 and select Assign New
Configuration File

Figure 30 - Assigning a New Configuration File for the FPGA

g) Navigate to the working directory and select lab_design_top.bit.This file is

located in the PlanAhead project under VHDL101_lab.runs > impl_1. Click
Open.
h) When prompted for SPI or BPI PROMs select NO.
i) Program the device by right-clicking the FPGA icon and selecting Program.
Click OK at the dialog box.
j) You should be rewarded with a blue box stating Program Succeeded
6) Testing the Design
You will need an RS-232 emulation tool such as hyperterminal to connect to
your board. For a free terminal emulation tool you can use http://hwserver.com/software/termv19b.html. Make certain that your terminal
emulator is set to 19200 baud, 8 data bits, no parity, 1 stop bit, no
handshaking. You will need to determine the COM port for your machine.
a. Enter the letter A. You should see a response of a and the left hand
LED should light for 1 second.
b. Enter the number 1. You should see a response of 1 and the right
hand LED should light for 1 second.
c. Finally, enter !. You should see a response of 1 and both LEDs should
light for 1 second.

Last notes:
A number of improvements can be made to this design.
The first is to reduce the clock frequency. The advantage to this is that slower
designs consume less power. Additional power and space is saved in the debouncer
in that a smaller counter can be built to cover the same amount of time. Alternately,
the DSP48 hard silicon device can be used as a counter which frees up FPGA fabric
and also reduces power.
Most FPGAs contain some form of clock management. Xilinxs Spartan-6 contains
both a Digital Clock Manager (DCM) and analog Phase Lock Loop (PLL). Both of
these devices have the ability to divide the incoming clock from 40 MHz down to
something more desirable. They also provide a signal which indicates that the clock
is stable. The inverse of the clock stable signal should then be routed to all the
modules which use reset. The reset signal from the button is then used to reset the
DCM or PLL.