EXP.

NO:
DATE :

ESTIMATION OF RESISTANCE, CAPACITANCE AND

INDUCTANCE

AIM:
To estimate resistance, capacitance and inductance of CMOS inverter using Microwind.
TOOLS REQUIRED:
Microwind.
PROCEDURE:
1. Open export Microwind and create a new file.
2. Click on File -> Select foundry to select foundry. The palette contains contacts, devices and
pads.
3. Draw the layout design for inverter circuit by selecting icons in the palette.
4. Click on File -> Save to save the layout with " inverter.MSK " file format.
5. To Run the design, Simulate -> Start Simulation give access to the automatic extraction
and simulation of the layout.
6. Select View navigator window. A new navigator window will open. Select different
nodes to display their resistance, capacitance & inductance values.
7. Tabulate those values in the following format :
Node
Resistance
Capacitance Inductance

THEORY:
RESISTANCE:
The resistance of a uniform slab of conducting material can be expressed as

R
Where is the resistivity. This expression can be written as

R
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Where

= /t is the sheet resistance and has the units of /square. To obtain the resistance

of a conductive on a layer, multiply the sheet resistance by the ratio of length to width of the
conductor. The resistivity of the thin metal films used in wires trends to be higher because of the
scattering of the surfaces and grain-bound rises.
CAPACITANCE:
An isolated wire over the substrate can be modeled as a conductor over a ground plane.
The wire capacitance has two major components: the parallel plate capacitor of the bottom of the
wire to ground and fringing capacitance arising from fringing fields along the edge of a
conductor with finite thickness. The classic parallel plate capacitance formula is,

C
Note that oxides are often doped with phosphorous to trap ions before they damage the
transistors. This oxide has ox ~ ko, k = 4.1 as compared to 3.9 for an ideal oxide or lower for
low-k dielectrics.
The dielectrics used between adjacent wires have the lowest possible dielectric constant khoriz to
minimize capacitance.
The dielectric between layers must provide greater mechanical stability and may have a larger
kvert. The constant Cfringe term accounts for fringing capacitance and gives a better fit for w and s
upto several times minimum.
INDUCTANCE:
The constant of proportionality is called inductance L. The inductance of a conductor of
length l and width w located a height h above a ground plane is approximately

Assuming w < h and thickness is negligible. Typical on-chip inductance values are in the range
of 0.15-1.5 pH/m depending on the proximity of the power or ground lines.
CROSS SECTION OF CMOS INVERTER:

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INVERTER LAYOUT DIAGRAM:

SIMULATION RESULT:

TABULATION :
RESISTANCE, CAPACITANCE & INDUCTANCE VALUES AT DIFFERENT NODES :
Node

Resistance

Capacitance

Inductance

RESULT:
Thus the resistance, capacitance and inductance were estimated for CMOS Inverter
using micro wind and its output was verified successfully.

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