RASEDA 2012 - ADC BIST - Ridgetop Group PDF

Built-In Self-Test Circuit for Total Ionizing Dose
Radiation Effects in Analog-to-Digital Converters

Esko O. Mikkola1, Viraj S. Pandit2, Byoung Uk Kim1, and Andrew Levy1*
1Ridgetop
Group, Inc., USA

2 Novellus Systems, Inc., USA
* Presenter
Presented at: RASEDA, Tsukuba, Japan, December 12, 2012
Outline
Introduction and ADC BIST Overview

TID Radiation Effects
ADC BIST Operation
Tested ADC
Simulation with TID Models
Ridgetop Group Overview
Summary
SBIR DATA RIGHTS

Contractor Name: Ridgetop Group, Inc.
Contractor Address: 3580 West Ina Road, Tucson, AZ 85741
Expiration of SBIR Data Rights Period: 5 years after completion of the contract
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Research (SBIR) Program clause contained in the above-identified contract. No restrictions apply after the expiration date shown above. Any reproduction of
technical data, computer software, or portions thereof marked with this legend must also reproduce the markings.
A.Levy
RASEDA 2012
Tsukuba, Japan
December 12 2012
3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com
Introduction and ADC BIST Overview (1)

Innovative Built-In Self-Test (BIST) circuit for monitoring Total
Ionizing Dose (TID) radiation effects in Analog-to-Digital
Converters (ADC)
Monitors changes in most important ADC performance

metrics affected by TID:
DNL
INL
Gain error
Offset error
Missing codes
Designed in a commercial 0.25 nm CMOS process
A.Levy
RASEDA 2012
Tsukuba, Japan
December 12 2012
Introduction and ADC BIST Overview (2)
Simulated and verified through VHDL, VHDL-AMS, and

SPICE
Parts of the system, such as the DAC and ADC have been
fabricated and verified on silicon
Radiation effect simulations performed in VHDL-AMS to
prove the effectiveness of the BIST circuit in capturing the
TID-induced parameter drifts in a commercial 8-bit ADC
The main challenge has been to design the rad-hard, lowpower, area-efficient circuit blocks that create the highly
linear voltage ramp test input used in the BIST
A.Levy
RASEDA 2012
Tsukuba, Japan
December 12 2012
TID Radiation Effects

TID Impact on Integrated Circuits
Accumulated charge trapped in semiconductor oxides over time
Measured in rads
Causes gradual IC performance degradation
VT Shift in NMOS/PMOS Devices

Causes offset in analog circuitry
Not generally a concern below 180 nm CMOS
Leakage Current in NMOS Devices

From silicon inversion next to insulation trench oxides
Reduced effect in modern CMOS fabrication processes

Still a concern for analog/mixed signal & I/O circuits
Studies: COTS ADCs useless after 5-60 krads
A.Levy
RASEDA 2012
Tsukuba, Japan
December 12 2012
ADC BIST Operation and Block Diagram

Operation Principle
Radiation hardened 12-bit counter and
12-bit delta sigma ADC create a highly
linear voltage ramp that is the test input
for the ADC during the calibration cycle
Digital Averager circuit calculates the
average of 64 -128 output words of the
ADC that operates at the nominal clock
speed
The averaged value is then stored onto
an on-chip or external rad-hard memory.
The data in the memory is parallel-toserial converted and read out using
JTAG bus
A.Levy
RASEDA 2012
Tsukuba, Japan
December 12 2012
Averager Block Diagram
Averager computes the

arithmetic average of
64-128 consequent
ADC conversion results
Stores average into an
on-chip 4 kilobyte
radiation-hardened
SRAM memory
A.Levy
RASEDA 2012
Tsukuba, Japan
December 12 2012
Tested ADC
Sub-ranging, 2-step, analog-to-digital

converter.
A.Levy
RASEDA 2012
Flash-type ADC
Tsukuba, Japan
December 12 2012
Simulation with TID Models
Simulation with TID models show

that the ADC output is severely
distorted by missing codes after
500 krads of TID stress.
A.Levy
RASEDA 2012
The codes stored in the SRAM during

the BIST cycle show exactly the same
distortion effects as observed in the
output of the ADC (Fig. 3), proving the
functionality of the BIST system.
Tsukuba, Japan
December 12 2012
Ridgetop Group Overview

Arizona-based firm, founded in 2000, with focus on
products and design services for critical applications
10
Two divisions: Semiconductor & Precision

Instruments (SPI) and Advanced Diagnostics &
Prognostics (ADP)
Technology leader in high accuracy ADCs for harsh
environment applications
Wide range of commercial and government
customers, including NASA, DOE, and DoD Agencies.
Worldwide nanotechnology R&D
partners in industry and academia
Foundation and focus in physics-offailure for complex electronic systems
A.Levy
RASEDA 2012
Tsukuba, Japan
10
December 12 2012
Road | Tucson
TucsonAZ
AZ || 85741
85741 || 520-742-3300
520-742-3300 || ridgetopgroup.com
ridgetopgroup.com
3580 West Ina Road,|
10
Summary
The BIST circuit can be used to monitor TID-induced

performance degradation effects in ADCs, such as
missing codes, increased DNL and INL, and increased
gain error and offset error.
Functionality of the designed BIST circuits and the
effectiveness of the system in monitoring TID effects in a
commercial ADC were verified through rigorous electrical
and radiation effect simulations in SPICE and VHDL-AMS.
A.Levy
RASEDA 2012
Tsukuba, Japan
December 12 2012
11
Questions
Thank You!
Andrew.Levy@RidgetopGroup.com
A.Levy
RASEDA 2012
Tsukuba, Japan
December 12 2012
12

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Built-In Self-Test Circuit for Total Ionizing Dose

Radiation Effects in Analog-to-Digital Converters

Group, Inc., USA

Presented at: RASEDA, Tsukuba, Japan, December 12, 2012

Introduction and ADC BIST Overview

SBIR DATA RIGHTS

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

Introduction and ADC BIST Overview (1)

Monitors changes in most important ADC performance

Designed in a commercial 0.25 nm CMOS process

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

Introduction and ADC BIST Overview (2)

Simulated and verified through VHDL, VHDL-AMS, and

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

TID Radiation Effects

VT Shift in NMOS/PMOS Devices

Leakage Current in NMOS Devices

Reduced effect in modern CMOS fabrication processes

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

ADC BIST Operation and Block Diagram

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

Averager Block Diagram

Averager computes the

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

Sub-ranging, 2-step, analog-to-digital

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

Simulation with TID Models

Simulation with TID models show

The codes stored in the SRAM during

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

Ridgetop Group Overview

Two divisions: Semiconductor & Precision

The BIST circuit can be used to monitor TID-induced

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

3580 West Ina Road | Tucson AZ | 85741 | 520-742-3300 | ridgetopgroup.com

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