UNIVERSITY SCIENCE INSTRUMENTATION CENTRE

(USIC)
JVD COLLEGE OF SCIENCE AND TECHNOLOGY,

ANDHRA UNIVERSITY

M.Sc(Tech.) VLSI Design

( 2008 11)

DETAILED SYLLABUS

Course duration: 3 years

No of semesters: 6

Semester 1

VL 101 - Applied mathematics 1

VL 102 - Advanced digital system design & Computer architecture
VL 103 - Programming concepts & C language
VL 104 - Device modelling
VL 105 - Practical C programming lab

Semester 2

(VL 201 Applied mathematics 2)

1. SPECIAL FUNCTIONS:
Bessels equation Bessel functions, Legendres equation- Legendre polynomials,
Roadridues formula - recurrence relations Generating functions & Orthogonal Property for
Bessels Function of the First kind.

2. FUNCTIONS RELATIONS AND GRAPH THEORY

Types of functions, inverse functions and composition of functions, relations and their
properties Graph Theory: Introduction and types of graphs, basic terminology, representation
of graphs and graph isomorphism. Connectivity, paths, indirect and undirected graphs and
isomerism.

3. CALCULUS AND VARIATIONS

Introduction, functionals, Eulers equations, solutions of Eulers equations, Isoperimetric
problems, several dependent variables, Functional involving higher order derivatives,
Approximation solutions of boundary value problems, Rayleigh Ritz Methods Galerkin
method.

4. LINEAR INTEGRAL EQUATIONS & PROBABILITY THEORY

Introduction definition, different kinds of integral equations, Fredholm and Volterra integral
equations, conversion of a linear differential equation to an integral equation and vice-versa,
Greens functions, solutions of Fredholm equations and Fredholm integral equations by the
method of successive approximations.
5. Basic terminology, concept of probability, additive law, multiplicative law and bayers
theorem (with out proof) Random variables, classification of random variables, discrete and
continuous random variables.
6. Distribution functions, conditional distribution functions and their properties. Moments of a
random variable and generating functions.Correlation coefficient Basic distributions:
Binomial, poision and normal distribution and momentum generating functions
Text Books:
Discrete Mathematics and its Applications by Kenneth.H.Rosem, Tata McGraw Publications,
New Delhi.(Unit-II)
Probability Theory and Stochastic process by P.Santhosbabu and D.Malathi Devi, SURE
Publications [Formerly Spectrum Publications] 2-1-338, Nallakunta, Hyderabad-44.(Unit-IV)
Higher Engineering Mathematics by B S Grewal. ( Unit-I,Unit-III, Unit-IV)

(VL 202 Digital signal processing)

1. DISCRETE TIME SIGNALS AND SYSTEMS :

Sampling of Analogue signals-Basic sequences and sequence operations- aliasing

standard discrete time signals classification discrete time systems Linear time
invariant stable casual discrete time systems classification methods linear and
circular convolution difference equation representation DFS, DTFT, DFT FFT
computations using DIT and DIF algorithms. Z-transforms and its properties Inverse
Z- transforms-Time response and frequency response analysis of discrete time
systems to standard input signals.
Structures for Discrete-Time Systems:

Signal flow graph representation of linear constant coefficient difference equations.

Basic IIR structures. Transposed forms. Basic structures for FIR systems. Overview
of finite-precision numerical effects.
2. INFINITE IMPULSE RESPONSE DIGITAL FILTERS:

Review of design of analogue Butterworth and Chebyshev Filters, Frequency

transformation in analogue domain Design of IIR digital filters using impulse
invariance technique Design of digital filters using bilinear transform pre warping
Frequency transformation in digital domain Realization using direct, cascade and
parallel forms.
3. FINITE IMPULSE RESPONSE DIGITAL FILTERS:

Symmetric and Anti symmetric FIR filters Linear phase FIR filters Design using
Frequency sampling technique Window design using Hamming, Hanning and
Blackmann Windows Concept of optimum equiripple approximation Realization
of FIR filters Transversal, Linear phase and Polyphase realization structures.
4. FINITE WORD LENGTH EFFECTS :

Quantization noise derivation for quantization noise power Fixed point and binary
floating point number representations Comparison Overflow error truncation
error coefficient quantization error limit cycle oscillations- signal scaling
analytical model of sample and hold operations.
5. SPECIAL TOPICS IN DSP:

Discrete Random Signals- Mean, Variance, Co-variance and PSD Periodiogram

Computation Principle of Multi rate DSP decimation and Interpolation by integer
factors Time and frequency domain descriptions Single, Multi stage, polyphase
structures QMF filters Sub band Coding
TEXT BOOK:

1. John G. Proakis and Dimitris G.Manolakis, Digital Signal Processing, Algorithms

and Applications , PHI of India Ltd., New Delhi 3rd Edition 2000.
REFERENCES:

1. Sanjit K.Mitra Digital Signal Processing, A Computer Based Approach, Tata

McGraw-Hill, New Delhi, 1998.
2.Allan Y. Oppenhein & Ronald W. Schater , "Digital Signal Processing, PHI, 2004.
3.J. R. Jhohnson, Intorduction to Digital Signal Processing, PHI, 2000.
4. Signal processing by B.P. Lathi

(VL 203 System modeling using VHDL & Verolig)

1. BASICS OF VHDL:

Introduction to VHDL - Levels of abstraction - Design Flow

2. LANGUAGE FUNDAMENTALS:

Basic code structure of VHDL - Lexical elements of VHDL - Data objects - Data
types - Operators Attributes - Identifiers
3. BEHAVIORAL DESCRIPTION:

Delay Model - Sequential Statements

4. STRUCTURAL DESCRIPTION AND DATA FLOW DESCRIPTION:

Concurrent Statements
5. MODELING COMBINATIONAL LOGIC CIRCUITS USING VHDL PACKAGE:

Adders, Multiplexers, Decoders, Encoders, Priority encoders, Comparators, ALU

6. MODELING SEQUENTIAL LOGIC CIRCUITS USING VHDL PACKAGE:

Latch - Flip-flops(R-S,JK,T,D) - Counters:2-bit counter using JK flip-flop,4-bit

counter using JK flip-flop, Counter with parallel load, Decade counter, Johnson
counter, Ring counter, Ripple counter, Up-Down counter
Registers:8-bit register with enable input, Shift registers, Serial-in Serial-out, Serial-in
Parallel-out, Parallel-in Serial-out, Parallel-in Parallel-out, and Multiplier
State Machines: 101over lapping Mealy sequence detector, 101 over lapping Moore
sequence detector, 101 non over lapping Moore sequence detector, 101 non over
lapping Mealy sequence detector
7. INTRODUCTION TO VERILOG:

Design function using Verilog - Levels of synthesizing Verilog - Designing N/W using
Verilog - Simple design - wires - wire assignments
8. Test -Benches - Response capture - RTL Verilog, If - statement synthesis
Text Books

1. Ashenden The Designers Guide to VHDL Tata McGraw Hill Publications, 2nd
Edition.
2. Mohammed Ismail Analog VLSI Integrated Circuits, Prentice Hall of India.
3. Grey, Hurst Luwis, Mayer, Analysis and Design of Analog Integrated Circuits
John Willey Sons.

(VL 204 Network analysis & synthesis)

1. Analysis of Networks in S Domain

Network elements, Transient and sinusoidal steady state analysis using Laplace
Transformation, Network functions, Two port networks: Parameters and transfer
function, Interconnection of two ports.
2. Methods for Computer Aided Network Analysis

State Variable Method, Analytic & numerical solutions, Graph theoretic analysis for
large scale networks, Formulation and solution of network graph of simple networks,
State space representation, Analysis using PSPICE.
3. Elements of Network Synthesis

Network realizability, Hurwitz Polynomials, Positive real functions, Properties of RC,

RL & LC networks, Foster & Cauer forms of realization, Transmission zeroes,
Synthesis of transfer functions, Frequency and impedance denormalisation, Types of
frequency selective filters, linear phase filters.
4. Passive Filter Design

Butterworth and Chebyshev approximations, Normalized specifications, Frequency

transformations, Frequency and impedance denormalisation, Types of frequency
selective filters, Linear phase filters.
5. Active Filter Design

Controlled sources, Op-amp as a controlled sourse, Sallen & Key structure, Single
amplifier LP, HP, BP & BR Filters, Principle of design, Sensitivity.
Text Books:

1. Someshwar C. Gupta, John W Bayless, Behrouz Peikari, Circuit Analysis-with

computer applications to problem solving, Wiley-Eastern Ltd,1991.
2. Louis Weinberg, Network Analysis & Synthesis, McGraw Hill Book Company
Inc., 1962.
3. Vasudev K. Aatre,Network Theory & Filter Design, Wiley-Eastern Ltd, Second
Edition, 1993.
References:

1. Franklin F. Kuo, Network Analysis & Synthesis, John Wiley.

2. Van Valkenberg, Network Analysis, Prentice Hall India Pvt. Ltd., New Delhi,
1994.
3. Lawrence P. Huelsman, Active and Passive Analog Filter Design, McGraw
Hill,1993.

(VL 205 VHDL & Verilog lab)

1. Basic logic gates
2. Flip Flops
3.
(a)
(b)
(c)

Adders
Half- Adder
Full Adder
CLA

4. Multiplexer
4:1 Multiplexer
8:1 Multiplexer
5.

Decoder

6.

Encoder

7. ALU
8. Counters
4 bit binary up down counter
Mod N counter
Counter with Parallel Load and clear facility
9. Shift Registers
Serial in Serial Out
Serial in Parallel Out
Parallel in Serial Out
Parallel in Parallel Out
10. Mealy & Moore machines
11. RAM & ROM
12. Sequence detector

Semester 3

(VL 301 VLSI Technology)

1. VLSI Design Flow :
Design hierarchy concepts of regularity, modularity & locality. VLSI Design styles CMOS
Fabrication Technology- Introduction, Fabrication Process flow- basic steps, CMOS n-well
process, Advanced CMOS fabrication technologies, layout design rules Introduction Full
custom Mask Layout design CMOS Layout design rules- CMOS inverter Layout design
Layout of CMOS NAND & NOR gates Complex CMOS Logic gates.
2. Parasitic extraction & performance estimation from physical structure :
Introduction Reality with interconnection MOSFET capacitances- interconnect
capacitance estimation interconnect resistance estimation.
3. Clock signals & system timing:
On chip clock generation & distribution using ring & pierce crystal oscillator, non
overlapping clock signals and gate level implementation - H-tree clock distribution N/Wclock skew reduction-Zero Skew clock routing N/W- Clock distribution N/W for DEC
alpha MP chips.
4. Testability of Integrated systems VLSI for Fuzzy logic systems:
Design constraints- Testing - The rule of ten terminology Failures in CMOS
CombinationalLogic Testing Practical Ad- Hoc DFT Guidelines Scan design techniquesIntegrated implementation of FLC, Digital Implementation of FLCs, Analog implementation
of FLCs, Mixed digital / analog implementations of Fuzzy systems, CAD automation for
FLC Design, NN implementing fuzzy systems.
5. Arithmetic for Digital Systems :
Introduction-notation systems - Principles of generation & Propagation, 1 bit full adder
Enhancement Techniques for Adders- multi-operand Adders- Multiplication- Addition and
Multiplication in Galois Fields GF (2n).
Refererence Books:
Cheng., SZE ., VLSI Technology., Prentice Hall of India,
Douglas A. Pucknell and Kamran Eshraghian, Basic VLSI Design Systems and circuits,
Prentice Hall of India Pvt Ltd., 1993.
Horspool., Gorman., The ASIC Handbook Tata Mc-Graw Publication., 1999
Randall.L. Geiger and P.E.Allen, - VLSI Design Techniques for Analog and Digital Circuits,
McGraw Hill International Company, 1990
Klir., Yan., Fuzzy Sets and Fuzzy logic ., Prentice Hall of India

(VL 302 VLSI Signal processing)

1.PIPELING AND PARALLEL PROCESSING :
Introduction Pipelining of FIR Digital Filters- Parallel Processing- Pipelining and
parallel Processing for Low Power.
2.RETIMING:
Introduction Definitions and Properties Solving system
Techniques.

of Inequalities Retiming

3.UNFOLDING :
Introduction An algorithm for unfolding properties of unfolding Critical path, unfolding
and retiming- Application of unfolding.
4.SYSTOLIC ARCHITECTURE DESIGN:
Introduction - systolic Array Design Methodology FIR systolic Arrays- Selection of
scheduling vector- Matrix Multiplication and 2 D systolic array Design Systolic design for
space representations containing Delays.
5.FAST CONVOLUTION:
Introduction- Cook Toom algorithm- Winogard algorithm Iterated convolution cyclic
Convolution Design of fast convolution Algorithm by Instpection.
6.SCALING AND ROUNDOFF NOISE
Introduction Scaling and Round off noise- State variable Description of digital filtersScaling and Round off noise computation - Roundoff Noise in Piplined HR filter- Roundoff
Noise Computation Using State varianle description Slow down, retiming, and pipelining
REFERENCES:
Keshab.K. Parhi, VLSI Digital signal processing systems- Design and Implementations
wiley- Inter science, 1999.
Mohammed Ismail, Terri, Fiez, Analog VLSI signal and Information Processing, 1994
McGraw Hill.
Keshab K.Parhi, VLSI Digital signal processing systems Design. And Implementation
Wiley- Inter science, 1999.
Kung.S.Y. H.J. While house, T.Kailath, VLSI and Modern signal processing, Prentice hall,
1985.
Jose E. France, Yannis Tsividis Design of Analog- Digital VLSI circuits for
Telecommunications and signal processing- Prentice Hall, 1994.

(VL 303 VLSI design)

1. MOS Transistor Theory
Gajski Chart in VLSI design domain, MOS structure, Biasing and operation of MOS, Scaling
in MOS Ckts, Small geometry effects, MOS capacitances, Mobility variations, Hot electron
effect.
2. MOS Inverter Design and Optimization
Static and Switching characteristics, Resistive Load Inverters, Inverter with n-type MOSFET
load, CMOS Inverters, Introduction to Switching characteristics, Inverter Delay Time
definitions and calculations, Delay constraints and in inverter.
3. CMOS Combinational Circuit Design
Introduction, MOS Logic Circuits with depletion MOS load, CMOS NAND and NOR gates,
Complex Gate Design, Pass transistor logic, Transistor gate logic [3].
4 CMOS Sequential Logic Design
Bistable elements, SR latch ckt, Clocked Latch and Flip-Flop ckts, CMOS D-latch edge
triggered flip/flop, CMOS SRAM design, CMOS DRAM design.
5. Dynamic Logic and Clocking Ckts.
Dynamic Pass Transistor ckts., Dynamic Transmission gate design, High Performance
dynamic logic ckts (Dynamis CMOS Logic,C2MOS Logic, CMOS Domino logic, NP
domino, Zipper CMOS ckt) Setup and Hold Time ,Clock Skew in CMOS ckts, PLL technique
for clock synchronization[2].
6. CMOS Chip Design Options and I/O Design.
Programmable Logic, Programmable Logic Structures, Programmable Interconnect,
Reprogrammable Gate Arrays, Sea-of-Gate and Gate Array Design, Standard Cell Design[2],
I/O Design-Introduction, ESD Protection, Input Ckts, Output Ckts and L(di/dt) noise, LatchUp prevention.
Reference Books:
1. Sung-Mo Kang, Yusuf Leblebici CMOS VLSI Design
2. H.E. Weste, Kamran Eshrigian Principles of CMOS VLSI Design- A System
Perspective Neil, Second Edition,Low Price Edition, Pearson education,Asia .
3. Jan M Rabey Digital Integrated Ckts.
4. Rabaey, Chandrakasan, Nikolic, Digital Integrated Circuits-- A Design Perspective 2nd
ed.,
Prentice Hall, c. 2003, ISBN 0-13-597444-5
5. Weste, Eshraghian, Principles of CMOS-VLSI Design-- A Systems Perspective, 2nd
ed. Addison-Wesley, c. 1994, ISBN 0-20-153376-

(VL 304 VLSI design tools)

1. Introduction to VLSI Methodologies
VLSI Physical Design Automation - Design and Fabrication of VLSI Devices - Fabrication
process and its impact on Physical Design.
2. A Quick Tour of VLSI Design Automation Tools
Data structures and Basic Algorithms, Algorithmic Graph theory and computational
complexity, Tractable and Intractable problems.
3. General purpose methods for combinational optimization:
Partitioning, floor planning and pin assignment, placement, routing.
4. Simulation-logic synthesis:
Verification-High level synthesis - Compaction. Physical Design Automation of FPGAs,
MCMS-VHDL-Verilog-Implementation of Simple circuits using VHDL and Verilog.
5. Design & Testing Tools
Commercial VLSI Design Tool (Availabvle in the Lab)
Reference Books:
1. N.A. Shervani, Algorithms for VLSI Physical Design Automation, 1999.
2. S.H.Gerez, Algorithms for VLSI Design Automation, 1998.
3. Commercial VLSI Design Tools Documentation(Availabvle in the Lab)

(VL 305 VLSI design lab)

Physical Design tools are extensively used for the following Exercises.
1. Design and testing of Flip flops.
2. Design and testing of registers, counters.
3. Design and testing of RAM, ROM Single Cells.
4. Design and testing of memory units.
5. Design and testing of circuits for combinational logic circuits.
6. Design and testing of programming logic arrays.
7. Design and testing of adders, multipliers.
8. Design and testing of Operational Amplifier
9. Design and testing of A/D, D/A converters.
10. Design and testing of applications based on synchronous logic.

Semester 4

(VL 401 Design and analysis of ICs)

1. CIRICUIT CONFIGURATION FOR LINEAR IC:
Current Sources, analysis of difference amplifiers with active load, supply and temperature
independent biasing technique, voltage references.
2. OPERATIONAL AMPLIFIERS :
Analysis of Operational amplifier circuits, slew rate model and high frequency analysis,
operational amplifier noise analysis and low noise operational amplifiers.
3. ANALOG MULTIPLIER AND PLL :
Analysis of four quadrant and variable transconductance multiplier, voltage controlled
oscillator, closed loop analysis of PLL.
4 MOS ANALOG ICS :
Design of MOS Operational Amplifier, CMOS voltage references, MOS Power amplifier and
analog switches.
5. MOS SWITCHED CAPACITOR FILTERS :
Design Techniques for switched capacitor filters, CMOS switched capacitor filters and MOS
integrated active RC filters.
Reference Books:
Behazad Razavi, Principles of Data Conversion System Design, S. Chand & Company Ltd,
2000
Grey and Meyar, Analysis and Design of Analog Ics. Wiley International, 1996.
Kenneth R. Laker, Willy M.C. Sansen, William M.C. Sansen, Design of Analog
Integrated
Circuits and Systems, McGraw Hill, 1994
Grey, Wolley, Brodersen, Analog MOS Integrated Circuits, IEEE

(VL 402 Electro magnetic interference & compatibility in design)

1. EMI ENVIRONMENT:
Sources of EMI, conducted and radiated EMI, Transient EMI, EMI EMC definitions and
units parameters. EMI Coupling Principles conducted, Radiated and Transient Coupling,
Common impedance Ground Coupling, Radiated Common Mode and Ground loop coupling
Radiated Differential mode coupling, Near field cable to cable to coupling, Power mains and
power supply coupling.
2. EMI SPECIFICATION/ STANDARDS / LIMITS :
Units of specification, civilian standards Military standards.
3. EMI MEASUREMENT:
EMI Test Instruments, Systems, EMI test, EMI shielded chamber. Open Area test site, TEM
Cell Antennas, Conductors Sensors / Injectors /Couplers, Military test methods and
Procedures, Calibration Producers.
4. EMI CONTROL TECHNIQUES :
Shielding, Filtering,Grounding , Bonding, Isolation Transformer, Transient Suppressors,
Cable Routing , Signal control, Component selection and Mounting.
5. EMI DESIGN OF PCB :
PCB Traces Cross Talk, Impedance control, Power Distribution Decoupling, Zoning Mother
board Design and Propagation delay performance models.
REFERENCE BOOKS:
1.. Bernhard Keiser Principles of Electromagnetic Compatibility, Artech House, #rd Ed,
1986.
2. Henry W. Ott., Noise education Techniques in Electronic System, John Wiley and Sons,
New
York,1988.
3. V.P.Kodali, Engineering EMC Prnciples, Measurements and Technologies, IEEE
Press,1996.

(VL 403 VLSI Physical design)

1.VLSI Methodologies:
VLSI Physical Design Automation-VLSI design cycle- Physical design cycle- design styles.
System packaging styles-die packaging and attachment styles. Design and Fabrication of
VLSI Devices-Fabrication of VLSI circuits- nMOS fabrication process- CMOS fabrication
process. Fabrication process and its impact on VLSI Design: status of fabrication processcomparison of fabrication processes. Future of fabrication process-SIA road map- advances in
lithography- innovations in interconnect- other process innovations- solutions for interconnect
issues.
2.VLSI Design Automation Tools:
Algorithms for NP-hard problems- computational geometry algorithms- graph algorithmsmatching algorithms.
3.Graph Algorithms for Physical Design:
classes of graphs in physical design-graphs related to set of lines- graphs related to set of
rectangles- relationship between graph classes- graph problems in physical design.
4.General purpose methods for combinational optimization:
Placement algorithms-constructive placement- iterative placement. Partitioning algorithmsKerninghan-lin algorithm. Floor planning-Terminology and floor plan representationoptimization problems in floor planning. Routing-Introduction to area routing- channel
routing- global routing.
5.Layout compaction:
Design rules- symbolic representation- problem formulation-applications of compactioninformal problem formulation- graph theoretical formulation. Algorithms for constraint graph
compaction-longest path algorithm for DAGs- Liao-Wong algorithm- The Bellman-Ford
algorithm.
6.Physical Design automation of FPGAs- MCMs- Implementation of simple circuits using
VHDL and Verilog.
Text books:
N.A Sherwani, Algorithms for VLSI Physical design Automation 1999.

S.H. Gerez, Algorithms for VLSI Design Automation 1998.

(VL 404 VLSI Circuit testing and verification)

1. Introduction to Testing
Introduction- Digital and Analog Testing, Types of Testing, Testing Equipments, Test
Economics.
2. Fault Modeling and Simulation
Introduction, Levels of Fault Models, Simulation for Design Verification and Test Evaluation,
Modeling Circuits for Simulation, algorithms for fault simulation.
3. Test Generation
Combinatorial Circuit Test Generation, Sequential Circuits test generation.
4. Analog & Mixed Signal Testing
Memory Test - Memory Test Levels, Memory Testing, Definitions, Static ADC and DAC
Testing Methods.
5. Design for Testability
Design For Test Fundamentals, Built-in Self Test Fundamentals, System Test and
architecture, Future of Testing.
Reference :
1. Michel L Bushnell and Vishwani D Agrawal, Essentials of electronic testing for Digital,
Memory and
Mixed-signal VLSI circuits, Kluwer Academic Publishers, 2000
2. M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable
Design", IEEE Press, 1990.( Available as JAICO Publication)
3. T.Kropf, "Introduction to Formal Hardware Verification", Springer Verlag, 2000.
4. Samiha Mourad and Yervant Zorian, Principles of Testing Electronic Systems, Wiley
(2000).
5. P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Verification-Methodology and
Techniques",
Kluwer Academic Publishers, 2001.

(VL 405 VLSI minor project 1)

Semester 5

(VL 501 FPGA design)

1. Introduction to PLDs:
ROMs, Logic array (PLA), Programmable array logic, GAL, bipolar PLA, NMOS PLA, PAL
14L 4, examples
2. Programmable gate arrays
Xilinx logic cell array (LCA) I/O Block Programmable interconnect Xilinx 3000 series and
4000 series FPGAs. Altera CPLDs, altera FLEX 10 K series PLDs.
3. Placement and routing :
Mincut based placement iterative improvement placement Routing: Segmented channel
routing Maze routing Routability and routing resources Net delays
4. Verification and testing:
Verification Timing verification Testing concepts Fault coverage ATPG Types of tests Testing
FPGAs Design for testability.
5 Recent developments :
New architectures Field programmable interconnect Configuring logic arrays and prototyping
boards CAD support.
Text books
1. P.K. Chan & S. Mourad, Digital Design sing Field Programmable Gate Array Prentice Hall,
1994.
2. J. V. Old Field & R.C. Dorf, Field Programmable Gate Array, John Wiley, 1995.
References
1.M. Bolton, Digital System Design with Programmable Logic, Addison Wesley, 1990.
2.Thomas E. Dillinger, VLSI Engineering, Prentice Hall.

(VL 502 ASIC design)

1. INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY DESIGN:
Types of ASICs Design flow-CMOS transistors CMOS Design rules- Combinational Logic
Cell- Sequential logic cell Data path logic cell- Transistors as Resistors- Transistor Parasitic
Capacitance- Logical effort- Library cell design - Library architecture.
2. PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS AND
PROGRAMMABLE ASIC I/O CELLS.
Anti fuse- static RAM EPROM and EEPROM technology - PREP benchmarks- Actel
ACT- Xilinx LCA- Altera FLEX- Altera MAX DC & AC inputs and outputs- Clock &
Power inputs- Xilinx I/O blocks.
3.
PROGRAMMABLE ASIC INTERCONNECT, PROGRAMMABLE ASIC
DESIGN
SOFTWARE AND LOW LEVEL DESIGN ENTRY
Actel ACT Xilinx LCA Xilinx EPLD Altera MAX 5000 and 7000- Altera MAX
9000- Altera FLEX- Design systems- Logic Synthesis Half gate ASIC Schematic entry
Low level design language PLA tools- EDIF- CFI design representation.
4.
LOGIC SYNTHESIS, SIMULATION AND TESTING
Verilog and logic synthesis- VHDL and logic synthesis types of simulation boundary
scan test- fault simulation - automatic test pattern generation.
5. ASIC CONSTRUCTION, FLOOR PLANNING, PLACEMENT AND ROUTING
System partition - FPGA partitioning partitioning methods, floor planning placementphysical design flow- global routing - detailed routing special routing circuit extraction
DRC.
Text Book :
1. M.J.S. Smith,-Application- Specific Integrated CircuitsAddison -Wesley Longman Inc.,
1997
Reference Books:
Andrew Brown,- VLSI Circuits and Systmes in silicon , McGraw Hill, 1991.
S.D. Brown, R.J. Francis, J. Rox, Z.G. Uranesic, Field Programmable Gate Arrays Kluever Academic Publishers, 1992.
Mohammed Ismail and Terri Fiez, Analog VLSI Signal and Information Processing , Mc
Graw Hill, 1994.
S.Y. Kung, H.J. Whilo House, T. Kailath, VLSI and Modern Signal Processing, Prentice
Hall , 1985.
Jose E. France, Yannis Tsividies, Design of Analoig- Digital VLSI Circuits for
Telecommunication and Signal Processing , Prentice Hall, 1994

(VL 503 Low power VLSI design)

1. INTRODUCTION :
Need for Low power VLSI chips- Low Power Design Methodology Logic synthesis for
Low power Sources of power dissipation.
2. POWER ESTIMATION:
Statistical Techniques- Estimation of Glitching Power- Sensitivity Analysis - Circuit
Reliability - Power Estimation at the circuit level- High level power Estimation Information Theory based approaches - Estimation of maximum power.
3. SYNTHESIS FOR LOW POWER:
Behavioral Level Transforms- Logic level optimization for low power - Circuit level
Transforms.
4. DESIGN AND TEST OF LOW VOLTAGE AND LOW POWER CIRCUITS:
Circuit Design style Leakage current in Deep sub-micrometer Transistors- Design IssuesMinimizing SCE Low voltage circuit design techniques Testing Deep sub-micrometer ICs
Multiple supply voltages Low energy computing - sources of software power dissipationsoftware power estimation- software power optimization Automated Low power code
generation - CODESIGN for low power.
REFRENCES :
Kaushik Roy and Sharat C. Prasad Low Power CMOS VLSI circuit Design John Wiley &
Sons, 2000.
Gary. B Yeap. K., Practical Low Power Digital VLSI Design, Kluwer academic
publishers, 1998.
Sasan Iman and Massoud Pedram, Logic synthesis for Low power VLSI Designs Kluwer
academic publishers, 1998.

(VL 504 Mixed signal design)

1. Introduction
Introduction to CMOS analog circuits, MOS transistor DC and AC small signal parameters
from large signal model, Common source amplifier with resistive load, diode load and current
source load, Source follower, Common gate amplifier, Cascode amplifier, Folded Cascode.
2. Frequency response
Frequency response of amplifiers, Current source/sink/mirror, Matching, Wilson current
source and Regulated Cascode current source, Band gap reference, Differential amplifier,
Gilbert cell, Op-Amp, Design of 2 stage Op-Amp, DC and AC response, Frequency
compensation, slew rate, Offset effects, PSRR, Noise, Comparator, Sense Amplifier.
3. Matching
Sources of mismatch, Systematic layout errors, Sizing and ratio strategy, Unit elements and
common, centroid layout and Random mismatch models
4. Data Converter
Data Converter Fundamentals, Analog Versus Discrete Time signals, Converting analog
signals to Digital signals, Sample and Hold Characteristics, Data Architectures, DAC and
ADC specifications. Mixed Signal Layout Issues, DAC Architectures,R-2R Ladder Networks,
Current steering, Pipeline DAC. ADC Architectures, Flash, The Two step Flash ADC, The
Successive Approximation ADC, RF amplifier, Oscillator, PLL, Mixer.
5. Nyquist A/D and D/A Converters; Comparators
Non-linearity specs, Voltage scaling D/A, settling, Current scaling D/A, matching,
segmentation, Charge redistribution, Flash A/D, ENOB vs BW, sparkle code elimination,
kickback, Asynchronous, Regenerative band Offset cancellation
6. A/D Converters and Mixed Signal Layout Issues
Basic principles, Sample & Hold characteristics, Practical implementations, SC vs
continuous time, Z domain model, Single bit vs multi-bit F/B, Higher order - MASH vs single
loop and D/A principle.
Recommended Texts
1. Laker & Sansen - "Design of Analog Integrated Circuits and Systems" , McGraw Hill.
2. Gray Hurst, Lewis & Meyer- "Analysis and Design of Analog Integrated Circuits (4th Ed)"
3. Geiger, Allen & Strader- VLSI Design Techniques for Analog and Digital Circuits",
McGraw-Hill.
4. Allen & Holberg CMOS Analog Circuit Design", Oxford UP.
5. Phillip. E. Allen, Douglas R. Holberg, CMOS Analog circuit Design Oxford University
Press, 2002
6. Razavi B., RF Microelectronics, Prentice Hall, 1998.
7. Baker, Li, Boyce, CMOS: Circuit Design, Layout and Simulation, Prentice Hall of
India, 2000
8. Bosco Leung, VLSI for Wireless Communication, PH, 2002
References:
Razavi B., Design of Analog CMOS Integrated Circuits, TMH, 2003
Mukherjee, VLSI System Design: Introduction to NMOS and CMOS VLSI System Design,
Prentice-Hall, 1986

(VL 505 VLSI minor project 2)

Semester 6

(VL 601 VLSI major project )