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A. Boora, Arash and Zare, Firuz and Ledwich, Gerard F. and Ghosh, Arindam
(2008) A New DC-DC Converter with Multi Output: Topology and Control
Strategies . In Proceedings EPE-PEMC - 13th International Conference on Power
Electronics and Motion Control, Poznan, Poland.
I. INTRODUCTION
To clarify the advantages of proposed topology in
comparison with other multi-output topologies, single
output Positive Buck Boost converter (PBB) circuit is
shown in (Fig. 1) [1, 2, 3].
PBB has the advantage of an extra freedom degree in
comparison with basic DC-DC converters of Buck Boost
and Inverting Buck Boost (IBB) [1]. This extra freedom
degree can be applied to decouple the inductor current
and capacitor voltage.
L
i
Vi
Io
V
V
= o = i
D RD RD 2
(1)
Boost
Il =
Io
V
DVi
= o =
D RD RD 2
(2)
IBB
Vo DVi
=
R
R
(3)
Buck
(4)
PBB
Il = I o =
Il =
1
1 Vo DBuck Vi
Io =
= 2
R
DBoost
DBoost
R DBoost
Dn
C n
R n
vn
.
.
.
Sk
Ck
Rk
vk
R2
v2
.
.
.
S2
SBu
Table I: All possible switching states with charging and discharging states
L
i
V in
C 2
S1
DBu
S0
v1
SBuck
S0
S1
Vc1
Vc2
IL
Charge
Charge
Discharge
Charge
Discharge
Discharge
Discharge
Discharge
No change
Charge
Charge
Discharge
Charge
Discharge
Discharge
Discharge
Discharge
Charge
v2
R2
110
V in
C1
C2
R2
V in
C1
R1
v1
C2
R2
v2
v2
010
C1
v2
101
R2
V in
v1
R1
C2
v1
R1
C2
R2
v2
001
V in
C1
R1
v1
C2
R2
v2
100
V in
C1
R 1
000
v1
V in
C1
R1
v1
100
B oost
101
B u ck
DBu Rk D j
Vk =
010
001
j=k
2
n
R D
k
j
j =k
k =1
(11)
Vin
00 0
110
IL =
B u ck-B oost
Dj = 1
0 Dj
j=0
(5)
0 D Bu 1
DBu
Vin
2
n
R D
j
k
k =1
j =k
R I
j
di
L L = D Bu vin Vk D j
dt
K
=
1
j
=
k
n
v
dv k
= i L D j i R 2 = i L D j k
Ck
dt
j =k
j =k
Rk
(6)
(7)
0 C1
0 0
0 0
0 0
0 0
n
Dj
j =1
n ...
D
j
j =k
...
Dn
0 iL
0 0 v1
0 0 ...
=
0 0 vk
... 0 ...
0 C n v n
0
...
Ck
0
n
Dj
j =1
... D j
j =k
1 R1
...
1 Rk
(8)
Dn
i L D Bu
0
0 v1 0
... 0
v i
0
0 +
vk 0
0
0 ... 0
...
0 v n 0
0 1 Rn
...
Rk D j
iL ( s ) =
j =k
Rk Ck s + 1
(9)
D Bu
2
n
R D
k
j
n
j =k
Ls +
1
R
C
s
+
k =1
k
k
vin
IL =
2
Rj
(13)
j =1
DBuVin
(12)
(10)
Vin V j Rj
I R1
j =1
(14)
I min = I R1
(15)
In step up case:
n
I Rj
Vin < V j
I R1
j =1
n
I Rj
I R1
I min = j
I R1
j =1
(16)
V. DISTURBANCE REJECTION
The extra current stored in the inductor lets MOPBB to
have a margin of input voltage fluctuation and load
change without low frequency (lower than switching
frequency) effect on output voltage. In other words this
extra current lets the MOPBB to block these disturbances
from output voltage as far as they are inside the above
mentioned margin.
The ratio of actual inductor current in any case to the
minimum inductor current () is important because it
shows the level of robustness of this converter against
input voltage fluctuations and load changes as well as
level of extra switching loss arising as a consequence of
extra current storage. Here we define the disturbance
rejection margin as a function of .
(17)
= I L I min
(18)
M {I Rj } =
(22)
j I Rj
j (1 + M + {I Rj })I Rj
j =1
j =1
=
n I Rj
n (1 + M + {I Rj })I Rj
min1, j
min1, j
+
j =1 (1 + M {I R1 })I R1
j =1 I R1
(23)
If we assume that same margin for all loads is required,
M + {I Rj } = 1
(24)
M = 1 D Bu
M + {I R }
M {Vin }
(19)
n I
min 1, j Rj
j =1 I R1
= 1
(20)
j I Rj
j =1
IL =
I Rj
n
min 1, j
j =1 I R1
= I Rk I L
(25)
j =k
C k Vk = TswBoost D j ( I L I Rk )
j =k
(26)
Ck Vk I L
TswBoost = min
I Rk ( I L I Rk
k = 1,..., n
(27)
Step Down :
stepUp : TswBoost
n
C k Vk j I Rj
j =1
= min
I I I
j Rj
Rk
Rk
j =1
(28)
VavgBoost = Vk D j
k =1
j =k
(29)
n
n
LI L
= Vk D j T fall =
T fall
k =1
j =k
L I L
n
Vk D j
k =1
j=k
(30)
n
n
LI L
= Vin Vk D j Trise =
Trise
k =1
j=k
LI L
n
Vin Vk D j
k =1
j =k
k D j 1 k D j
k =1
j=k
k =1
j =k
LI L I L
= n
n
( k I Rk ) I L ( k I Rk )
k =1
k =1
=
(31)
TswBuck =
LI L I R1
n
( k I Rk ) I R1 ( k I Rk )
k =1
k =1
n
LI L j I Rj
stepUp : TswBuck =
j =1
n
n
( k I Rk ) j I Rj ( k I Rk )
k =1
k =1
j =1
(32)
Duty Cycle
Current
Hysteresis
Control
Inductor current
Minimum
Inductor current
Input voltage
Output voltage V1
Output voltage V2
Reference
Current
ioutC2
Priority
Conditioning
ioutC1
OR
Vi
Reference
Voltages
Voltage
Hysteresis
Control
time
Inductor current
Inductor current
Minimum
Inductor current
Input voltage
Output voltage V1
IX. ACKNOWLEDGMENT
The authors thank the Australian Research Council
(ARC) for the financial support for this project through
the ARC Linkage Grant LP0774899.
References
Output Current of C1 (ioutC1)
R2= 20, 20||40, 20 ||20
R2=10
Output voltage V2
time
Figure 9 simulation results of the hysteresis control system for MOPBB
when input voltage and R2 change
VIII.
CONCLUSION