1.

Flip-flops, also called bistable gates, are digital logic circuits that can be in one of two states
2. SR flip flop, D flip flop, JK flip flop, Master-slave flip flop
3. A latch is an electronic logic circuit that has two inputs and one output. One of the inputs is called
theSET input; the other is called the RESET input.
4.

5.

using nand gate

using nor gates

6.

7. A JK flip-flop is an improved version of SR flip flop where J is analogous to the S (set) input and K is
analogous to the R(reset) input. The major difference is that J and K inputs may both be high
simultaneously.
8. The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the Master circuit, which
triggers on the leading edge of the clock pulse while the other acts as the Slave circuit, which
triggers on the falling edge of the clock pulse. This results in the two sections, the master
section and the slave section being enabled during opposite half-cycles of the clock signal.

9. propagation delay (tP), which is the time a flip-flop takes to change its output

after the clock edge. The time for a high-to-low transition (tPHL) is sometimes
different from the time for a low-to-high transition (tPLH).
When cascading flip-flops which share the same clock (as in a shift register), it is
important to ensure that the tCO of a preceding flip-flop is longer than the hold time
(th) of the following flip-flop, so data present at the input of the succeeding flip-flop
is properly "shifted in" following the active edge of the clock.

10. Setup time is the minimum amount of time the data signal should be held

steady before the clock event so that the data are reliably sampled by the clock.
This applies to synchronous input signals to the flip-flop.
11. Hold time is the minimum amount of time the data signal should be held
steady after the clock event so that the data are reliably sampled. This applies to
synchronous input signals to the flip-flop.
Synchronous signals (like Data) should be held steady from the set-up time to
the hold time, where both times are relative to the clock signal.
12. Pulse WidthModulation is a simple method for controlling analog devices via a
digital signal
13.
14. The highest frequency at which a clock input of an integrated circuit can be driven, while
maintaining proper operation.
15.

Synchronous Counter

In a synchronous counter, the input pulses are applied to all clock pulse
inputs of all flip flops simultaneously (directly). Synchronous counter is also
known asparallel sequential circuit.

Asynchronous Counter

In an asynchronous counter, the flip flop output transition serves as a

source for triggering other flip flops. In other words, the clock pulse inputs
of all flip flops, except the first, are triggered not by the incoming pulses, but
rather by the transition that occurs in previous flip flops output..
Asynchronous counter is also known as serial sequential circuit.