Overview

State machines

! Last lecture
" Cascading flip-flops
" Clock skew
" Registers

! Combinational logic and storage elements

" Localized feedback loops
" Choice of storage elements alters the logic
# D flip-flop, T flip-flop, etc.

! Today
" Introduction to finite state machines

Inputs

# State diagrams
"

Outputs

Combinational
Logic

Counters as finite state machines

# Counter design
State Inputs

State Outputs
Storage Elements

CSE370, Lecture 19

CSE370, Lecture 19

Asynchronous versus synchronous

Finite-state machines

! Asynchronous
" State changes occur when state inputs change
" Feedback elements may be wires or delays

! States: Possible storage-element values

! Transitions: Changes in state
" Clock synchronizes the state changes

! Synchronous
" State changes occur synchronously
" Feedback elements are clocked

! Sequential logic
" Sequences through a series of states
" Based on inputs and present state

Asynchronous

Synchronous

Combinational
Logic

Combinational
Logic

In = 1
In = 0

Clock

CSE370, Lecture 19

Drawing state diagrams

OUT1

on transition arcs

0
001

101
0
0

In = 1

110

CSE370, Lecture 19

OUT3

! Simple state machines

" Output is the counters state
! Next state is well defined
" Does not depend on input (no inputs)

D Q

001

110

010

011

1
010

1
0

CSE370, Lecture 19

D Q

100

000

OUT2

CLK

1
0

D Q

IN

in state nodes

100

111
In = 0

Begin by studying counters

! Show input values

! Show output values

010

001

0
1

111

000

111

011
5

CSE370, Lecture 19

100

3-bit up-counter

110

101

Counter design procedure

1. Draw a state diagram

1. Draw a state diagram

2. Draw a state-transition table
3. Encode the next-state functions
"

010

001

Minimize the logic using k-maps

4. Implement the design

000

101

110

111

100

3-bit up-counter

Example: Design the 3-bit up counter

CSE370, Lecture 19

011

CSE370, Lecture 19

2. Draw a state-transition table

3. Encode the next state functions

! Like a truth-table
" State encoding is easy for counters Use count value

! Assume D flip-flops

000

011

010

001

100

3-bit up-counter
110

111

current state
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

101

as state elements

C3

N2

C1 0

C1 1

C2

next state
001 1
010 2
011 3
100 4
101 5
110 6
111 7
000 0

CSE370, Lecture 19

C3

N1

C3
0
0
0
0
1
1
1
1

C2
0
0
1
1
0
0
1
1

C1
0
1
0
1
0
1
0
1

N3
0
0
0
1
1
1
1
0

N2
0
1
1
0
0
1
1
0

N1
1
0
1
0
1
0
1
0

C2
C3

N3

N1 := C1'
N2 := C1C2' + C1'C2
:= C1 xor C2

C1 0

N3 := C1C2C3' + C1'C3 + C2'C3

:= C1C2C3' + (C1' + C2')C3
:= (C1C2) xor C3

CSE370, Lecture 19

4. Implement the design

Class example

! 3 flip-flops hold state

" Counter is synchronously clocked

! Redesign the 3-bit up counter using T flip-flops

D Q

2. Draw a state-transition table

OUT2
D Q

10

1. Draw a state diagram

! Minimized logic computes next state

OUT1

C2

3. Encode the next-state functions

OUT3

"

D Q

Minimize the logic using k-maps

4. Implement the design

CLK

"1"

CSE370, Lecture 19

11

CSE370, Lecture 19

12

1. Draw a state diagram

2. Draw a state-transition table

! Like a truth-table
" State encoding is easy for counters Use count value

010

001

000

011

3-bit up-counter

000

CSE370, Lecture 19

CSE370, Lecture 19

13

3. Encode the next state functions

C3

T1
C1

C2
0
0
1
1
0
0
1
1

C1
0
1
0
1
0
1
0
1

N3
0
0
0
1
1
1
1
0

N2
0
1
1
0
0
1
1
0

CSE370, Lecture 19

N1 T3 T2 T1
1
0
1
0
1
0
1
0

C3

T3
C1

C1
C2

T1 :=
C3
0
0
0
0
1
1
1
1

C3

T2

C2

100

3-bit up-counter

111

T flip-flops

011

101

110

111

010

001

100

C2

T3 :=

T2 :=

4. Implement the design:

C1
T

C2
T Q

C3
T

CLK
15

110

101

current state
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

next state
001 1
010 2
011 3
100 4
101 5
110 6
111 7
000 0

14