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VHDL codes for common Combinational Circuits:

Simple 4 : 1 multiplexer using case statements


Here is the code for 4 : 1 MUX using case statements.The module contains 4 single bit input lines and one 2
bit select input.The output is a single bit line.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplexer4_1 is
port (
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic
);
end multiplexer4_1;
architecture Behavioral of multiplexer4_1 is
begin
process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => bitout <= i0;
when "01" => bitout <= i1;
when "10" => bitout <= i2;
when others => bitout <= i3;
end case;
end process;
end Behavioral;

Simple 1 : 4 Demultiplexer using case statements


Here is the code for 4 :1 DEMUX using case statements.The module has 4 single bit output lines and one 2
bit select input.The input line is defined as a single bit line.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1_4 is
port (
out0 : out std_logic;
--output bit
out1 : out std_logic;
--output bit
out2 : out std_logic;
--output bit
out3 : out std_logic;
--output bit
sel : in std_logic_vector(1 downto 0);
bitin : in std_logic
--input bit
);
end demux1_4;
architecture Behavioral of demux1_4 is
begin
process(bitin,sel)
begin
case sel is
when "00" => out0 <= bitin; out1 <=
when "01" => out1 <= bitin; out0 <=
when "10" => out2 <= bitin; out0 <=
when others => out3 <= bitin; out0
end case;
end process;
end Behavioral;

'0'; out2 <=


'0'; out2 <=
'0'; out1 <=
<= '0'; out1

'0'; out3 <='0';


'0'; out3 <='0';
'0'; out3 <='0';
<= '0'; out2 <='0';

3 : 8 Decoder using basic logic gates


Here is the code for 3 : 8 Decoder using basic logic gates such as AND,NOT,OR etc.The module has one 3bit input which is decoded as a 8-bit output.

--libraries to be used are specified here


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--entity declaration with port definitions
entity decoder is
port(
input :
in std_logic_vector(2 downto 0); --3 bit input
output : out std_logic_vector(7 downto 0) -- 8 bit ouput
);
end decoder;
--architecture of entity
architecture Behavioral of decoder is
begin
output(0)
output(1)
output(2)
output(3)
output(4)
output(5)
output(6)
output(7)

<=
<=
<=
<=
<=
<=
<=
<=

(not input(2)) and (not input(1)) and (not input(0));


(not input(2)) and (not input(1)) and input(0);
(not input(2)) and input(1) and (not input(0));
(not input(2)) and input(1) and input(0);
input(2) and (not input(1)) and (not input(0));
input(2) and (not input(1)) and input(0);
input(2) and input(1) and (not input(0));
input(2) and input(1) and input(0);

end Behavioral;

4 bit comparator with testbench


Here is the code for 4 bit comparator using if .. elsif ... else statements.The module has two 4-bit inputs which
has to be compared, and three 1-bit output lines.One of these output lines goes high depending upon whether
the first number is equal to,less or greater than the second number.

--libraries to be used are specified here


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--entity declaration with port definitions
entity compare is
port(
num1 : in std_logic_vector(3 downto 0); --input 1
num2 :
in std_logic_vector(3 downto 0); --input 2
less :
out std_logic;
-- indicates first
number is small
equal :
out std_logic;
-- both are equal
greater :
out std_logic
-- indicates first number is
bigger
);
end compare;
--architecture of entity
architecture Behavioral of compare is
begin
process(num1,num2)
begin
-- process starts with a 'begin' statement
if (num1 > num2 ) then --checking whether num1 is greater than num2
less <= '0';
equal <= '0';
greater <= '1';
elsif (num1 < num2) then
--checking whether num1 is less than num2
less <= '1';
equal <= '0';
greater <= '0';
else
--checking whether num1 is equal to num2
less <= '0';
equal <= '1';
greater <= '0';
end if;
end process;
-- process ends with a 'end process' statement
end Behavioral;