Lab 2: Inverter

Characteristics and the

Ring Oscillator
Deanna Sessions
ECEN 248- 511
TA: Priya Venkatas
Date: September 16, 2013

Objectives:
In the first experiment in this lab I will learn about how the output voltages change in correlation
to the input voltages in a logic gate. This will help to better understand what happens in the inbetween voltages when it is not strictly a high or low input. The second experiment in this
lab will teach how to create an oscillating voltage output just by using a series of NOT gates and
how to properly wire a SN7404 while creating this ring oscillator. More importantly, this will
teach how to use the oscilloscope properly and read information off of it to collect data.

Design:
Experiment 1:
Experiment 1 requires one inverter, a power source, and a multimeter. This was just an inverter
hooked up to an adjustable power source and a multimeter and the power source was
incrementally changed and the voltage output was recorded.
Experiment 2:
Experiment 2 requires one SN7404 which houses 5 NOT gates, a power source, a mutlimeter,
and an oscilloscope. The design of this circuit is included in the lab manual.

Results:
Experiment 1:
Vout
0
1
1.2
1.4
1.6
1.8
2
3
4
5

3.9
3.77
2.77
0.67
0.0975
0.0974
0.0975
0.0975
0.0974
0.0974

Voltage Transfer Characteristics

Voltage Output (V)

Vin

4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0

Voltage Input (V)

This data shows that for the input voltages of 0-1 V the setup is solidly showing a Logic 1
output, but at about 1.3 V there is a significant drop to having Logic 0 as an output and it
stabilizes at 1.6 V to being consistently giving the same value of Logic 0 from 1.6 5 V. This
was an interesting thing to learn because I had expected it to return a Logic 0 closer to 1 V than
to 2 V because I had assumed any amount of voltage would return a Logic 0 from an inverter.
However, it makes sense that it would give a Logic 0 after having just passed 1 V because it
wouldnt be feasible to have the only way to get a Logic 0 by having zero voltage attached to the
circuit.

Experiment 2:

The period of the Ring Oscillator was found to be 59.4 ns. Using this equation:
Dinv =
Where T is the period and N is the number of NOT gates used in the oscillator and Dinv is the
delay of an inverter. This results in an inverter delay of 5.94 ns for this particular 5 gate circuit.
The graph displayed above shows the actual wave pattern that the circuit created and it is no
surprise that the circuit fell into a sinusoidal wave pattern as it bounced back and forth from
Logic 0 and Logic 1.

Conclusion:
In this lab I became more acquainted with the lab equipment and the inner workings of logic
gates. For example, I now know the tolerance levels for the different logic states within a logic
gate and can plan accordingly in future circuits. I also now have the knowledge and the means to
create a ring oscillator which will allow me to have a constant sinusoidal stream of logic states
that alternate between low and high while also creating a consistent time delay between each
state. On top of this, I learned how to properly wire an SN7404 with 5 NOT logic gates internally
working with each other and how to use the oscilloscope to collect data from the circuit.

Questions:
1.

Voltage Output (V)

Voltage Transfer Characteristics

4.5
4
3.5
3
2.5
2
1.5
1
0.5
0

Logic 1

Logic 0

Voltage Input (V)

The graph above depicts the ranges for voltages in which Logic 1 and Logic 0 are shown. The
range of input voltage for which the inverter shows Logic 1 as output is 0 1 V and the range of
input voltage for which the inverter shows Logic 0 as the output is 1.6 5 V.
2. As shown above in the results section of the lab, the single stage delay of the Ring Oscillator
can be calculated using this equation:
Dinv =

This comes out to have an inverter delay equaling 5.94 ns for my particular ring oscillator with 5
NOT gates. The question suggests a 21 stage ring oscillator with Dinv equaling 10 ns and asks
what the frequency would be. Using the above equation coupled with f = 1/T you are able to
calculate that the period is 420 ns and that makes the frequency of this 21 stage Ring Oscillator
2.38 * 106 Hz.
3. The signals at P, Q, R, and S are periodic and they have a time period of 5.94 ns which is the
same time as the delay and this should not differ from the signal at node A because node A is just
another gate exactly like the other 4.

Student Feedback:
1. I really liked that this lab went more into the inner workings of the logic gates. I didnt
like how I didnt know how to properly wire an SN7404 or use an oscilloscope properly
and had to muddle through it a bit.
2. I wish the manual told what pins connect with the other pins to create the internal NOT
gates for the SN7404 because I didnt intuitively know that certain pins must be skipped
and gone back to in order to create the proper wiring. This part of the experiment could
have been made better if there were a better overview of the proper usage of the
oscilloscope. I also wish question 3 in the post-lab deliveries was more straightforward as
to what it is specifically wanting.
3. Include a diagram of how to properly wire the SN7404, include a comprehensive tutorial
on how to properly use the oscilloscope and get the data to look the way it is supposed to
look with the settings, and reword Post-Lab Deliverables #3.