Low-Power SRAM-Based Delay Buffer Using Gated Driver Tree

SRAM BASED DELAY BUFFER USING GATED DRIVER
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1. INTRODUCTION
1.1 NEED FOR THE PROJECT
The skyrocketing increasing transistor count and circuit density of modern very
large scale integrated (VLSI) circuits have made them extremely difficult and expensive
to test comprehensively.
In a digital processing chip of mobile communications, the delay buffer takes up a
large portion of the circuit layout. If the power consumption of the delay buffer could be
reduced significantly, the overall power consumption of the digital processing chip could
be reduced significantly as well. On the other hand, as these chips are working at even
higher operation frequencies, a new, low-power delay buffer should be operable under
high frequencies. As illustrated, the delay buffer contains N.times.W shift registers 10,
arranged between the input and the output in N stages, each with W shift registers. The
N.times.W shift registers are triggered by a same clock signal CLK. For every clock
period of CLK, W-bit data is shifted from W shift registers of a previous stage to those of
a next stage, and so on. A W-bit data input N clock periods ago therefore would be
delayed and output after N clock periods. The clock signal CLK is provided to all N.
times. W shift registers, contributing to the high power consumption.
One of the common delay buffer implementation is a dual-port SRAM memory
whose operation is different from that of the shift-register-based delay buffer. For an N
.times. W SRAM-based delay buffer, there is no data movement between stages. Instead,
at every clock period, a W-bit data is written to one of the N .times .W storage locations
of the SRAM-based delay buffer, and another W-bit data that is written N clock periods
ago is output. The power consumption of a SRAM-based delay buffer is mainly from the
address decoder and the drivers for its input and output ports. As memory related
technology has already quite mature and satisfactory results in terms of layout area and
speed are achievable. Therefore in reality a delay buffer is often implemented using
SRAM memory.
Sri Sunflower College Of Engineering & Technology
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1.2 MEMORY ORGANISATION:
Memory organization is two-fold. First we discuss the hardware (physical)
organization, then the internal architecture. The type of computer and its size do not
reflect the type of memories that the computer uses. Some computers have a mixture of
memory types. For example, they may use some type of magnetic memory (core or film)
and also a semiconductor memory (static or dynamic). They also have a read-only
memory which is usually a part of the CPU. Memory in a computer can vary from one or
more modules to one or more pcbs, depending on the computer type. The larger
mainframe computers use the modular arrangement, multiple modules (four or more), to
make up their memories. Whereas, minicomputers and microcomputers use chassis
or assemblies, cages or racks, and motherboard or backplane arrangements. Minis
and micros use multiple components on one pcb or groups of pcbs to form the
memory.
There are several ways to organise memories with respect to the way they are
connected to the cache
1.2.1 ONE-WORD-WIDE MEMORY ORGANISATION
The memory is one word wide and connected via a one word wide bus to the
cache.
1.2.2 WIDE MEMORY ORGANISATION
The memory is more than one word wide (usually four words wide) and
connected by an equally wide bus to the low level cache (which is also wide). From the
cache multiple busses of one word wide go to a MUX which selects the correct bus to
connect to the high level cache.
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1.2.3 INTERLEAVED MEMORY ORGANISATION
There are several memory banks which are one word wide, and one one word
wide bus. There is some logic in the memory that selects the correct bank to use when the
memory gets accessed by the cache.
Memory interleaving is a way to distribute individual addresses over memory
modules. Its aim is to keep the most of modules busy as computations proceed. With
memory interleaving, the low-order k bits of the memory address select a module, and the
high-order m bits name a location within that module. Hence, consecutive addresses are
located in successive modules. A request to access consecutive memory locations can
keep several modules busy at the same time.
1.2.4 INDEPENDENT MEMORY ORGANISATION
There are several banks, which can all be accessed simultaneously by several
buses.
Memory geometry:
In the design of modern personal computers, memory geometry describes the
internal structure of random-access memory. Memory geometry is of concern to
consumers upgrading their computers, since older memory controllers may not be
compatible with later products. Memory geometry terminology can be confusing because
of the number of overlapping terms.
1.3 PHYSICAL FEATURES
Memory geometry describes the logical configuration of a RAM module, but
consumers will always find it easiest to grasp the physical configuration. Much of the
confusion surrounding memory geometry occurs when the physical configuration
obfuscates the logical configuration. The first defining feature of RAM is form factor.
RAM modules can be in compact SO-DIMM form for space constrained applications like
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laptops, printers, embedded computers, and small form factor computers, and in DIMM
format, which is used in most desktops.
The other physical characteristic determine with by physical examination are the
number of memory chips, and whether both sides of the memory "stick" are populated. If
4 is a factor of the number of memory devices or chips (or more generally, a power of
two), then the module does not feature ECC, if 9 is a factor of the number of memory
chips (or one more than a power of two), then the module does. RAM modules are 'keyed'
by indentations on the sides, and along the bottom of the module. This determines the
technology, and classification of the modules, for instance whether it is DDR2, or DDR3,
and whether it is suitable for desktops, or for servers. It is important to make sure that the
keying of the module matches the key of the slot it is intended to occupy. Additional, nonmemory chips on the module are an indication that it could be designed for high capacity
memory systems for servers, and that the module may be incompatible with desktop
systems.
As the next section of this article will cover the logical architecture, which covers
the logical structure spanning every populated slot in a system, the physical features of
the slots themselves becomes important. By consulting the documentation of your
motherboard, or reading the labels on the board itself, you can determine the underlying
logical structure of the slots. When there is more than one slot, they are numbered, and
when there is more than one channel, the different slots are separated in that way as well usually colour-coded.
1.4 LOGICAL FEATURES
In the 90s specialized computers were released where two computers that each
had their own memory controller could be networked at such a low level that the software
run could use the memory, or CPU of either computer as if they were one unit. With
AMD's release of the Opteron, and Intel's corresponding systems that share more than one
memory controller in a single system have become common in applications that require
the power of more than one common desktop. For these systems schemes like NonUnified Memory Architecture are used.
Channels are the highest level structure at the local memory controller level.
Modern computers can have two, three or even more channels. It is usually important
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that, for each module in any one channel, there is a logically identical module in the same
location on each of the other populated channels.
Kingston describes each module as having a geometry of 128Mx64,
meaning that each one has 64 bits 128 million deep, equaling 8.192 billion bits, or
1.024 Gigabytes. Kingston describes each "device", or chip as having a geometry of
64Mx8, so each module has four banks. So from the MCHPOV when there are 4
1GB modules, it sees 2 channels, each with 8 banks.
1.5 HIERARCHY OF ORGANIZATION
1.5.1 MEMORY CHIP
The lowest form of organization covered by memory geometry, sometimes
called "memory device". These are the component ICs that make up each module,
or module of RAM. The most important measurement of a chip is its density,
measured in bits. Because memory bus width is usually larger than the number of
chips, most chips are designed to have width, meaning that they are divided into
equal parts internally, and when one address "depth" is called up, instead of
returning just one value, more than one value is returned. In addition to the depth, a
second addressing dimension has been added at the chip level, banks. Banks allow
one bank to be available, while another bank is unavailable because it is refreshing.
An example of chip notation is 64Mb (depth) X 8 (width) X 8 Banks.
1.5.2 MEMORY MODULE
Some measurements of modules are size, width, speed, and latency. A
memory module consists of a multiple of the memory chips to equal the desired
module width. So a 32 bit SIMM module could be composed of four 8-bit wide (x8)
chips. As noted in the memory channel part, one physical module can be made up of
one or more logical ranks. If that 32 bit simm were composed of eight 8-bit chips
the simm would have two ranks. An example of Module notation is 128Mb x 64-bit.
1.5.3 MEMORY CHANNEL

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A memory channel is made up of ranks. Physically a memory channel with just
one memory module might present itself as having one or more logical ranks.
1.5.4 CONTROLLER ORGANIZATION
This is the highest level. In a typical computer there will only be a single memory
controller with only one or two channels. The logical features section described NUMA
configurations, which can take the form of a network of memory controllers. For
example, each socket of a two socket AMDK8 can have a two channel memory
controller, giving the system a total of four memory channels.
1.5.5 RANDOM-ACCESS MEMORY
Random-access memory (RAM) is a form of computer data storage. Today, it
takes the form of integrated circuits that allow stored data to be accessed in any order
(that is, at random). "Random" refers to the idea that any piece of data can be returned in
a constant time, regardless of its physical location and whether it is related to the previous
piece of data.[1]
The word "RAM" is often associated with volatile types of memory such as
DRAM (memory modules), where the information is lost after the power is switched off.
Many other types of memory are RAM as well, including most types of ROM and a type
of flash memory called NOR-Flash.
1.5.6 TYPES OF RAM
Modern types of writable RAM generally store a bit of data in either the state of a
flip-flop, as in SRAM (static RAM), or as a charge in a capacitor (or transistor gate), as in
DRAM (dynamic RAM), EPROM, EEPROM and Flash. Some types have circuitry to
detect and/or correct random faults called memory errors in the stored data, using parity
bits or error correction codes. RAM of the read-only type, ROM, instead uses a metal
mask to permanently enable/disable selected transistors, instead of storing a charge in
them. Of special consideration is a SIMM and DIMM memory module.
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SRAM and DRAM are volatile. Other forms of computer storage, such as disks
and magnetic tapes, have been used as persistent storage. Many newer products instead
rely on flash memory to maintain data when not in use, such as PDAs or small music
players. Certain personal computers, such as many rugged computers and netbooks, have
also replaced magnetic disks with flash drives. With flash memory, only the NOR type is
capable of true random access, allowing direct code execution, and is therefore often used
instead of ROM; the lower cost NAND type is commonly used for bulk storage in
memory cards and solid-state drives. A memory chip is an integrated circuit (IC) made of
millions of transistors and capacitors. In the most common form of computer memory,
dynamic random access memory (DRAM), a transistor and a capacitor are paired to
create a memory cell, which represents a single bit of data. The capacitor holds the bit of
information a 0 or a 1 . The transistor acts as a switch that lets the control circuitry on
the memory chip read the capacitor or change its state.
Memory hierarchy:
Many computer systems have a memory hierarchy consisting of CPU registers,
on-die SRAM caches, external caches, DRAM, paging systems, and virtual memory or
swap space on a hard drive. This entire pool of memory may be referred to as "RAM" by
many developers, even though the various subsystems can have very different access
times, violating the original concept behind the random access term in RAM. Even within
a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or
interleave organization of the components make the access time variable, although not to
the extent that rotating storage media or a tape is variable. The overall goal of using a
memory hierarchy is to obtain the higher possible average access performance while
minimizing the total cost of the entire memory system (generally, the memory hierarchy
follows the access time with the fast CPU registers at the top and the slow hard drive at
the bottom).
In many modern personal computers, the RAM comes in an easily upgraded form
of modules called memory modules or DRAM modules about the size of a few sticks of
chewing gum. These can quickly be replaced should they become damaged or when
changing needs demand more storage capacity. As suggested above, smaller amounts of
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RAM (mostly SRAM) are also integrated in the CPU and other ICs on the motherboard,
as well as in hard-drives, CD-ROMs, and several other parts of the computer system.
By convention, bus and network data rates are denoted either in bit/s (bits per
second) or byte/s (bytes per second). In general, parallel interfaces are quoted in byte/s
and serial in bit/s. The more commonly used is shown below in bold type.
On devices like modems, bytes may be more than 8 bits long because they may be
individually padded out with additional start and stop bits; the figures below will reflect
this. Where channels use line codes (such as Ethernet, Serial ATA and PCI Express),
quoted rates are for the decoded signal.
The figures below are simplex data rates, which may conflict with the duplex rates
vendors sometimes use in promotional materials. Where two values are listed, the first
value is the downstream rate and the second value is the upstream rate.
All quoted figures are in metric decimal units, where:
1 Byte = 8 bit
1 kbit/s = 1,024 bit/s
1 Mbit/s = 1,024 kbit/s
1 Gbit/s = 1,024 Mbit/s
1 kB/s = 1,024 Byte/s
1 MB/s = 1,024 KByte/s
1 GB/s = 1,024M Byte/s
1 TB/s = 1,024 GByte/s
These decimal prefixes have been established in data communications for long
time, also before 1998 when IEC and other organizations tried to make it standard for all
computing applications, and introduced new binary prefixes.
1.5.7 MEMORY SYSTEM
Memory in a computer system is required for storage and subsequent retrieval of
the instructions and data. A computer system uses variety of devices for storing these
instructions and data which are required for its operations. Normally we classify the
information to be stored on computer in two basic categories: Data and the Instructions.
"The storage devices along with the algorithm or information on how to control and
manage these storage devices constitute the memory system of a computer."
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A memory system is a very simple system yet it exhibits a wide range of
technology and types. The basic objective of a computer system is to increase the speed
of computation. Likewise the basic objective of a memory system is to provide fast,
uninterrupted access by the processor to the memory such that the processor can operate
at the speed it is expected to work.
But does this kind of technology where there is no speed gap between processor
and memory speed exist. The answer is yes they do, but unfortunately as the access time
(time taken by CPU to access a location in memory) becomes less and less the cost per bit
of memory becomes increasingly higher. In addition, normally these memories require
power supply till the information need to be stored. Both these things are not very
convenient, but on the other hand the memories with smaller cost have very high access
time which will result in slower operation of the CPU. Thus, the cost vs access time
anomaly has lead to a hierarchy of memory where we supplement fast memories with
larger, cheaper, slower memories. These memory units may have very different physical
and operational\ characteristics, therefore, making the memory system very diverse in
type, cost,\ organisation, technology and performance.
a. Internal Processor Memories:
These consist of the small set of high speed registers which are internal to a
processor and are used as temporary locations where actual processing is done. This will
be covered in greater details in Block 2.
b. Primary Memory or Main Memory:
It is a large memory which is fast but not as fast as internal processor memory.
This memory is accessed directly by the processor. It is mainly based on integrated
circuits. Secondary Memory/Auxiliary Memory/Backing Store: Auxiliary memory in fact
is much larger in size than main memory but is slower than main memory. It normally
stores system programs (programs which are used by system to perform various
operational functions), other instructions, programs and data files. Secondary memory can
also be used as an overflow memory in case the main memory capacity has been
exceeded. Secondary memories cannot be accessed directly by a processor. First the
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information of these memories is transferred to the main memory and then the
information can be accessed as the information of main memory.
There is another kind of memory which is increasingly being used in modern
computers, this is called Cache memory. It is logically positioned between the internal
memory (registers) and main memory. It stores or catches some of the content of the main
memory which is currently in use of the processor. We will discuss about this memory in
greater details in a subsequent section of this unit.
Before discussing more about these memories let us first discuss the technological
terms commonly used in defining and accessing the memory.
1.5.8 CHARACTERISTICS TERMS FOR VARIOUS MEMORY DEVICES
The following terms are most commonly used for identifying comparative
behaviour of various memory devices and technologies.
1.5.8.1 STORAGE CAPACITY:
It is a representative of the size of the memory. The capacity of internal memory
and main memory can be expressed in terms of number of words or bytes. The storage
capacity of external memory is normally measured in terms of bytes.
Unit of transfer:
Unit of transfer is defined as the number of bits read in or out of the memory in a
single read or write operation, For main memory and internal memory, the normal unit of
transfer of information is equal to the word length of a processor. In fact it depends on
number of data lines in and out of the memory module. (Why?) In general, these lines are
kept equal to the word size of the processor. What is a word? You have already learnt
about this term in Unit 1 of this block. The unit of transfer of external memory is
normally quite large (Why? You will find the answer to this question later in this unit)
and8is referred to as block of data.
1.5.8.2 ACCESS MODES:
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Once we have defined the unit of transfer next important characteristics is the
access mode in which the information is accessed from the memory. A memory is
considered to consist of various memory locations. The information from memory
devices can be accessed in the following ways.
1.5.8.3 RANDOM ACCESS MEMORY (RAM):
It is the mode in which any memory location can be accessed in any order in the
same amount of time. Ferrite and Semiconductor memories which generally constitute
main memory are of this nature. The storage locations can he accessed independently and
there exist separate access mechanism for each location.
1.5.8.4 SEQUENTIAL ACCESS:
On the other hand we have memories which can be accessed in pre-defined
sequences for example; the songs stored on a cassette can be accessed only one by one.
The example of sequential access memory is Magnetic Tape. Here the access mechanism
needs to be shared among different locations. Thus, either the location or the read/write
head or both should be moved to access the desired location.
1.5.8.5 DIRECT ACCESS:
In certain c apses the information is neither accessed randomly nor in sequence
but something in between. In this kind of access, a separate read/write head exist for a
track and on a track the information can be accessed serially. These semi-random modes
of operation exist in magnetic disks.
1.5.8.6 ACCESS TIME:
The access time is the time required between the request made for a read or write
operation till the time the data is made available or written at the requested location.
Normally it is measured for read operation. The access time depends on the physical
characteristics and access mode used for that device. Permanence or Storage: Is it
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Possible to lose information by the memories over a period of time. The reasons of the
loss of information and what should be done to avoid it. There are several reasons for
information destruction, these are destructive readout, dynamic storage, volatility and
hardware failure.
If for a particular memory the reading process destroys the stored information. we
call it Destructive readout. In such memories the information has to be written back on
the same location from which it had been read after each read operation. The reading
process where the data is not destroyed on reading are referred to as Non-destructive
readout. There can be some memories where the stored 1 looses its strength to become 0
over a period of time. These kind of memories require refreshing. The memories which
require refreshing are termed as dynamic memories. In contrast, the memories which do
not require refreshing are called static memories.
Another factor which can destroy the contents is die presence and absence of
electricity. The memories which loses their content on failure of power am armed as
volatile memories, those which do not are called non-volatile. Magnetic memories are
non-volatile and semiconductor main memories am volatile in nature.
Cycle Time:
It is defined as the minimum time elapsed between two consecutive read requests.
Is it equal to access time? Yes, for most of the memories except the ones in which
destructive readout is encountered. Cycle time for such memories is the access time (time
elapsed when a read request is made available) plus writing time as after the data has been
made available the information has to be written back in the same memory location as the
previous value has been destroyed by reading. But for most of the commonly used
semiconductor memories cycle time is equal to the access time
2. DELAY BUFFERS
2.1 DELAY BUFFERS
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This section describes PJMEDIA's implementation of delay buffer. Delay buffer
works quite similarly like a fixed jitter buffer, that is it will delay the frame retrieval by
some interval so that caller will get continuous frame from the buffer. This can be useful
when the operations are not evenly interleaved, for example when caller performs burst of
put() operations and then followed by burst of operations. With using this delay buffer,
the buffer will put the burst frames into a buffer so that get() operations will always get a
frame from the buffer (assuming that the number of get() and put() are matched).
The buffer is adaptive, that is it continuously learns the optimal delay to be
applied to the audio flow at run-time. Once the optimal delay has been learned, the delay
buffer will apply this delay to the audio flow, expanding or shrinking the audio samples as
necessary when the actual audio samples in the buffer are too low or too high.
Fig 2.1: Buffer
2.2 EXISTING TECHNIQUE:
Fig 2.2: Existing Block Of Memory Organisation

2.2.1 INPUT BUFFER:
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The Input buffer is also commonly known as the input area or input block.
When referring to computer memory, the input buffer is a location that holds all incoming
information before it continues to the CPU for processing.
Input buffer can be also used to describe various other hardware or software
buffers used to store information before it is processed.
Some scanners (such as those which support include files) require reading from
several input streams. As flex scanners do a large amount of buffering, one cannot control
where the next input will be read from by simply writing a YY_INPUT() which is
sensitive to the scanning context. YY_INPUT() is only called when the scanner reaches
the end of its buffer, which may be a long time after scanning a statement such as an
include statement which requires switching the input source.
a
b
2:1
Fig 2.3: InputBuffer

2:1
I1
I2
Out
B
Table 2.1: Truth Table For
Mux
2.2.2 MEMORY BLOCK:
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(RAM) Random-access memory (RAM) is a form of computer data storage.
Today, it takes the form of integrated circuits that allow stored data to be accessed in any
order (that is, at random). "Random" refers to the idea that any piece of data can be
returned in a constant time, regardless of its physical location and whether it is related to
the previous piece of data.
The word "RAM" is often associated with volatile types of memory such as
DRAM (memory modules), where the information is lost after the power is switched off.
Many other types of memory are RAM as well, including most types of ROM and a type
of flash memory called NOR-Flash.
Scan design has been the backbone of design for testability (DFT) in industry for
about three decades because scan-based design can successfully obtain controllability and
observability for flip-flops. Serial Scan design has dominated the test architecture because
it is convenient to build. However, the serial scan design causes unnecessary switching
activity during testing which induce unnecessarily enormous power dissipation. The test
time also increases dramatically with the continuously increasing number of flip-flops in
large sequential circuits even using multiple scan chain architecture. An alternate to serial
scan architecture is Random Access Scan (RAS). In RAS, flip-flops work as addressable
memory elements in the test mode which is a similar fashion as random access memory
(RAM). This approach reduces the time of setting and observing the flip-flop states but
requires a large overhead both in gates and test pins. Despite of these drawbacks, the RAS
was paid attention by many researchers in these years. This paper takes a view of recently
published papers on RAS and rejuvenates the random access scan as a DFT method that
simultaneously address three limitations of the traditional serial scan namely, test data
volume, test application time, and test power.
A Decoder is used to address every FF. The RAS allows reading or writing of any
flip-flop using address bits where n is the number of scanned flip-flops when the
address is applied, the address decoder produces a scan enable signal to the corresponding
flip-flop needed to be placed with a data from the scan-in. In this technique, the scan
function is implemented as a random-access memory. Hence at every given time only one
FF is accessed while other FFs retain their state. The architectures described in most
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literatures mainly consists of a scan-in signal that is broadcasted to every FF, a test
control signal that is broadcasted to all FFs, and a unique decoder signal from the decoder
to every FF.
A more feasible decoder has been designed. The grid architecture shown in Fig 2.5
is one efficient way to layout the decoders. With a minimum of two layers of metal
routing, the row wires can be accommodated within the channel in between the cell rows
and the column wires can be routed over the cell in the next metal layer. Hence there will
be an increase of one track per channel (assuming m channels) and n tracks that are
routed on the next metal layer.
Fig 2.4: Design Of RAS
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Fig 2.5: Decoder Design

In those two decoder structures, suppose there are Nff flip-flops in the circuit. In
Figure 1, there will be Nff - address wires to those N flip-flops. Compared to Figure 1,
there are only
Nff address wires to N-ffs in Figure 2. Although this structure need both
row decoder and column decoder when only one decoder is used in Figure 1, the
hardware overhead reduced greatly using structure 2.
2.3 COMMON RAM MEMORY TYPES:
SRAM - Static random access memory uses multiple transistors, typically four to
six, for each memory cell but doesn't have a capacitor in each cell. It is used primarily for
cache.
DRAM - Dynamic random access memory has memory cells with a paired
transistor and capacitor requiring constant refreshing.
FPM DRAM - Fast page mode dynamic random access memory was the original
form of DRAM. It waits through the entire process of locating a bit of data by column and
row and then reading the bit before it starts on the next bit. Maximum transfer rate to L2
cache is approximately 176 megabytes per second.
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EDO DRAM - Extended data-out dynamic random access memory does not wait
for all of the processing of the first bit before continuing to the next one. As soon as the
address of the first bit is located, EDO DRAM begins looking for the next bit. It is about
five percent faster than FPM. Maximum transfer rate to L2 cache is approximately 264
megabytes per second.
SDRAM - Synchronous dynamic random access memory takes advantage of the
burst mode concept to greatly improve performance. It does this by staying on the row
containing the requested bit and moving rapidly through the columns, reading each bit as
it goes. The idea is that most of the time the data needed by the CPU will be in sequence.
SDRAM is about five percent faster than EDO RAM and is the most common form in
desktops today. Maximum transfer rate to L2 cache is approximately 528 megabytes per
second.
RDRAM - Rambus dynamic random access memory is a radical departure from
the previous DRAM architecture. Designed by Rambus, RDRAM uses a Rambus in-line
memory module (RIMM), which is similar in size and pin configuration to a standard
DIMM. What makes RDRAM so different is its use of a special high-speed data bus
called the Rambus channel. RDRAM memory chips work in parallel to achieve a data
rate of 800 MHz.
Credit Card Memory - Proprietary self-contained DRAM memory module that
plugs into a special slot for use in notebook computers.
PCMCIA Memory Card - Another self-contained DRAM module for notebooks. Cards of
this type are not proprietary and should work with any notebook computer whose system
bus matches the memory card's configuration.
Flash RAM - A generic term for the small amount of memory used by devices like
TVs, VCRs and car radios to maintain custom information. Even when these items are
turned off, they draw a tiny amount of power to refresh the contents of their memory. This
is why every time the power flickers; the VCR blinks 12:00. It's also why you lose all
presets on your radio when your car battery dies! Your computer has Flash RAM to
remember things like hard disk settings -- see for details.
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VRAM Video RAM, also known as multiport dynamic random access memory
(MPDRAM), is a type of RAM used specifically for video adapters or 3-D accelerators.
The "multiport" part comes from the fact that VRAM normally has both random access
memory and serial access memory. VRAM is located on the graphics card and comes in a
variety of formats, many of which are proprietary. The amount of VRAM is a determining
factor in the resolution and color depth of the display. VRAM is also used to hold
graphics-specific information such as 3-D geometry data and texture maps.
Random access memory (RAM) is the best known form of computer memory. But
the way it works and what the different terms mean can be very confusing.
RAM is considered "random access" because you can access any memory cell
directly if you know the row and column that intersect at that cell. The opposite of RAM
is serial access memory (SAM). SAM stores data as a series of memory cells that can
only be accessed sequentially (like a cassette tape). If the data is not in the current
location, each memory cell is checked until the needed data is found. SAM works very
well for memory buffers, where the data is normally stored in the order it will be used. A
good example is the texture buffer memory on a video card.
How RAM Works
Similar to a microprocessor, a memory chip is an integrated circuit (IC) made of
millions of transistors and capacitors. In the most common form of computer memory,
dynamic random access memory (DRAM), a transistor and a capacitor are paired to
create a memory cell, which represents a single bit of data. The capacitor holds the bit of
information -- a 0 or a 1 (see How Bits and Bytes Work for information on bits). The
transistor acts as a switch that lets the control circuitry on the memory chip read the
capacitor or change its state.
A capacitor is like a small bucket that is able to store electrons. To store a 1 in the
memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The problem
with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full
bucket becomes empty. Therefore, for dynamic memory to work, either the CPU or the
memory controller has to come along and recharge all of the capacitors holding a 1 before
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they discharge. To do this, the memory controller reads the memory and then writes it
right back. This refresh operation happens automatically thousands of times per second.
This refresh operation is where dynamic RAM gets its name. Dynamic RAM has to be
dynamically refreshed all of the time or it forgets what it is holding. The downside of all
of this refreshing is that it takes time and slows down the memory.
Memory cells are etched onto a silicon wafer in an array of columns (bit lines) and
rows (word lines). The intersection of a bit line and word line constitutes the address of
the memory cell.
DRAM works by sending a charge through the appropriate column (CAS) to
activate the transistor at each bit in the column. When writing, the row lines contain the
state the capacitor should take on. When reading: the sense-amplifier determines the level
of charge in the capacitor. If it is more than 50% it reads it as a 1, otherwise as a zero. The
counter tracks the refresh sequence based on which rows have been accessed in what
order. The length of time necessary to do all this is so short that it is expressed in
nanoseconds (billionths of a second). A memory chip rating of 70ns means that it takes 70
nanoseconds to completely read and recharge each cell.
Memory cells alone would be worthless without some way to get information in
and out of them. So the memory cells have a whole support infrastructure of other
specialized circuits.
These circuits perform functions such as:
Identifying each row (row address select or RAS) and column (column address
select or CAS) keeping track of the refresh sequence (counter) reading and restoring the
signal from a cell (sense amplifier) telling a cell whether it should take a charge or not
(write enable).
Other functions of the memory controller include a series of tasks that include
identifying the type, speed and amount of memory and checking for errors.
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Static RAM uses a completely different technology. In static RAM, a form of flipflop holds each bit of memory (see How Boolean Gates Work for detail on flip-flops). A
flip-flop for a memory cell takes 4 or 6 transistors along with some wiring, but never has
to be refreshed. This makes static RAM significantly faster than dynamic RAM.
However, because it has more parts, a static memory cell takes a lot more space on a chip
than a dynamic memory cell. Therefore you get less memory per chip, and that makes
static RAM a lot more expensive.
So static RAM is fast and expensive, and dynamic RAM is less expensive and
slower. Therefore static RAM is used to create the CPU's speed-sensitive cache, while
dynamic RAM forms the larger system RAM space.
In computer it uses DRAM (dynamic RAM) for the main memory. I have also
heard of static RAM. What is the difference, and why are there two kinds
Your computer probably uses both static RAM and dynamic RAM at the same
time, but it uses them for different reasons because of the cost difference between the two
types. If you understand how dynamic RAM and static RAM chips work inside, it is easy
to see why the cost difference is there, and you can also understand the names.
Dynamic RAM is the most common type of memory in use today. Inside a
dynamic RAM chip, each memory cell holds one bit of information and is made up of
two parts: a transistor and a capacitor. These are, of course, extremely small transistors
and capacitors so that millions of them can fit on a single memory chip. The capacitor
holds the bit of information -- a 0 or a 1 (see How Bits and Bytes Work for information on
bits). The transistor acts as a switch that lets the control circuitry on the memory chip read
the capacitor or change its state.
A capacitor is like a small bucket that is able to store electrons. To store a 1 in the
memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The problem
with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full
bucket becomes empty. Therefore, for dynamic memory to work, either the CPU or the
memory controller has to come along and recharge all of the capacitors holding a 1 before
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they discharge. To do this, the memory controller reads the memory and then writes it
right back. This refresh operation happens automatically thousands of times per second.
This refresh operation is where dynamic RAM gets its name. Dynamic RAM has
to be dynamically refreshed all of the time or it forgets what it is holding. The downside
of all of this refreshing is that it takes time and slows down the memory.
Static RAM uses a completely different technology. In static RAM, a form of flipflop holds each bit of memory (see How Boolean Gates Work for detail on flip-flops). A
flip-flop for a memory cell takes 4 or 6 transistors along with some wiring, but never has
to be refreshed. This makes static RAM significantly faster than dynamic RAM.
However, because it has more parts, a static memory cell takes a lot more space on a chip
than a dynamic memory cell. Therefore you get less memory per chip, and that makes
static RAM a lot more expensive.
So static RAM is fast and expensive, and dynamic RAM is less expensive and
slower. Therefore static RAM is used to create the CPU's speed-sensitive cache, while
dynamic RAM forms the larger system RAM space.
How Flash Memory Works
Electronic memory comes in a variety of forms, to serve a variety of purposes.
Flash memory is used for easy and fast information storage in such devices as digital
cameras and home video game consoles. It is used more as a hard drive than as RAM. In
fact, Flash memory is considered a solid state storage device. Solid state means that there
are no moving parts -- everything is electronic instead of mechanical.
Here are a few examples of Flash memory:
Your computer's BIOS chip
CompactFlash (most often found in digital cameras)
Smart Media (most often found in digital cameras)
Memory Stick (most often found in digital cameras)
PCMCIA Type I and Type II memory cards (used as solid-state disks in laptops)
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Memory cards for video game consoles

Flash memory is a type of EEPROM chip. It has a grid of columns and rows with
a cell that has two transistors at each intersection (Figure 1). The two transistors are
separated from each other by a thin oxide layer. One of transistors is known as a floating
gate and the other one is the control gate. The floating gate's only link to the row, or word
line, is through the control gate. As long as this link is in place, the cell has a value of "1".
To change the value to a "0" requires a curious process called Fowler-Nordheimtunneling.
Tunnelling is used to alter the placement of electrons in the floating gate. An electrical
charge, usually 10-13 volts, is applied to the floating gate. The charge comes from the
column, or bitline, enters the floating gate and drains to a ground.
This charge causes the floating gate transistor to act like an electron gun. The
excited electrons are pushed through and trapped on other side of the thin oxide layer,
giving it a negative charge. These negatively charged electrons act as a barrier between
the control gate and the floating gate. A special device called a cell sensor monitors the
level of the charge passing through the floating gate. If the flow through the gate is
greater than fifty percent of the charge, it has a value of "1". When the charge passing
through drops below the fifty percent threshold: the value changes to "0". A blank
EPROM has all of the gates fully open, giving each cell a value of "1".
Up to a point, adding RAM (Random Access Memory) will normally cause your
computer to feel faster on certain types of operations. The reason why RAM is important
because of an operating system component called the virtual memory manager.
When you run a program like a word processor or an internet browser, the
microprocessor in your computer pulls the executable file off the hard disk and loads it
into RAM. In the case of a big program like Microsoft Word or Excel, the EXE consumes
about 5 megabytes. The microprocessor also pulls in a number of shared DLLs (Dynamic
Link Libraries) - shared pieces of code used by multiple applications. The DLLs might
total 20 or 30 megabytes. Then the microprocessor loads in the data files that you want to
look at, which might total several megabytes if you are looking at several documents or
browsing a page with a lot of graphics. So a normal application needs between 10 and 30
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megabytes of RAM space to run. On my machine at any given time the following
applications running:
A word processor
A spreadsheet
A DOS prompt
An email program
A drawing program
3 or 4 browser windows
A Fax program
A Telnet session
Besides all of those applications, the operating system itself is taking up a good bit
of space. Those programs together might need 100 to 150 megabytes or RAM, but my
computer only has 64 megabytes of RAM installed.
The extra space is created by the virtual memory manager. The VMM looks at
RAM and finds sections of RAM that are not currently needed. It puts these sections of
RAM in a place called the swap file on the hard disk. For example, even though I have
my email program open, I haven't looked at email in the last 45 minutes. So the VMM
moves all of the bytes making up the email program's EXE, DLLs and data out to the
hard disk. That is called swapping out the program. The next time I click on the email
program, the VMM will swap in all of its bytes from the hard disk, and probably in the
process swap something else out. Because the hard disk is slow relative to RAM, the act
of swapping things in and out causes a noticeable delay.
If you have a very small amount of RAM (say 16 megabytes), then the VMM is
always swapping things in and out to get anything done. In that case your computer feels
like it is crawling. As you add more RAM you get to a point where you only notice the
swapping when you load a new program or change windows. If you were to put 256
megabytes of RAM in your computer the VMM would have plenty of room and you
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would never see it swapping anything. That is as fast as things get. If you added more
RAM it would have no effect.
Some applications (things like Photoshop, many compilers, most film editing and
animation packages, etc.) needs tons of RAM to do their job. If you run them on a
machine with too little RAM, they swap constantly and run very slowly. You can get a
huge speed boost by adding enough RAM to eliminate the swapping. Programs like these
may run 10 to 50 times faster once they have enough RAM.
2.4 RING COUNTER:
A ring counter is a type of counter composed of a circular shift register. The
output of the last shift register is fed to the input of the first register.
There are two types of ring counters:
A straight ring counter or Overbeck counter connects the output of the last shift
register to the first shift register input and circulates a single one (or zero) bit around the
ring. For example, in a 4-register one-hot counter, with initial register values of 1000, the
repeating pattern is: 1000, 0100, 0010, 0001, 1000... . Note that one of the registers must
be pre-loaded with a 1 (or 0) in order to operate properly.
A twisted ring counter (also called Johnson counter or Moebius counter) connects
the complement of the output of the last shift register to its input and circulates a stream
of ones followed by zeros around the ring. For example, in a 4-register counter, with
initial register values of 0000, the repeating pattern is: 0000, 1000, 1100, 1110, 1111,
0111, 0011, 0001, 0000... .
If the output of a shift register is fed back to the input. aringcounter results. The
data pattern contained within the shift register will recirculate as long as clock pulses are
applied. For example, the data pattern will repeat every four clock pulses in the figure
below. However, we must load a data pattern. All 0's or all 1's doesn't count.
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Fig
2.6: Ring Counter Using Shift
Register
We make provisions for loading data into the parallel-in/ serial-out shift register
configured as a ring counter below. Any random pattern may be loaded. The most
generally useful pattern is a single 1.
Fig 2.7: Ring counter In Parallel in Serial out Shift Register
Loading binary 1000 into the ring counter, above, prior to shifting yields a
viewable pattern. The data pattern for a single stage repeats every four clock pulses in our
4-stage example. The waveforms for all four stages look the same, except for the one
clock time delay from one stage to the next. See figure below.
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Fig 2.8: Ring Counter With SR Flip-Flops
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The above block diagram shows the power controlled Ring counter. First, total
block is divided into two blocks. Each block is having one SR FLIPFLOP controller
S
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Q(t-1)
0
1
1
1
1
1
0
1
Q
0
1
0
0
1
1
X
X
Table 2.2: SR Flip Flop Truth Table
3. PROPOSED DELAY BUFFERS
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Fig 3.1: Block Diagram For Proposed Delay Buffer

3.1 GATED DRIVER TREE:
Fig 3.2: Gated Driver Tree

Gated driver tree derived from the same clock gating signals of the blocks that
they drive. Thus, in a quad-tree clock distribution network, the gate signal of the gate
driver at the level (CKE ) should be asserted when the active DET ip-op.
3.2 MODIFIED RING COUNTER:
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Fig 3.3: Modified Ring Counter

DET (Double edge triggered) flip-flops:
Double-edge-triggered (DET) ip-ops are utilized to reduce the operating
frequency by half The logic construction of a double-edge-triggered (DET) flip-flop,
which can receive input signal at two levels the clock, is analyzed and a new
circuit design of CMOS DET In this paper, we propose to use double-edge-triggered
(DET) ip-ops instead of traditional DFFs in the ring counter to halve the operating
clock frequency. Double edge-triggered flip-flops are becoming a popular technique for
low-power designs since they effectively enable a halving of the clock frequency. The
paper by Hossainetal[1] showed that while a single-edge triggered flip-flop can be
implemented by two transparent latches in series, a double edge-triggered flip-flop can be
implemented by two transparent latches in parallel; the circuit in Fig. 1 was given for the
static flip-flop implementation. The clock signal is assumed to be inverted locally. In high
noise or low-voltage environments, Hossainetal noted that the p-type pass-transistors may
be replaced by n-types or that all pass-transistors may be replaced by transmission gates.
3.3 C ELEMENT:
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The Muller C-element, or Muller C-gate, is a commonly used asynchronous logic
component originally designed by David E. Muller. It applies logical operations on the
inputs and has hysteresis. The output of the C-element reflects the inputs when the states
of all inputs match. The output then remains in this state until the inputs all transition to
the other state. This model can be extended to the Asymmetric C-element where some
inputs only effect the operation in one of the transitions (positive or negative). The figure
shows the gate-level and transistor-level implementations and symbol of the C-element.
Here is the truth table for a 2-input c-gate. Yn 1 denotes a "no change" condition.
A
0
0
1
1
Fig 3.4: C- Element
B
0
1
0
1
Q
0
Q(t-1)
Q(t-1)
1
Table 3.1: Truth Table For C-Element
The C-element stores its previous state with two cross-coupled inverters, similar
to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be
overpowered by the pull-up and pull-down networks.
If both inputs are 0, then the pull-up network changes the latch's state, and the Celement outputs a 0. If both inputs are 1, then the pull-down network changes the latch's
state, making the C-element output a 1. Otherwise, the input of the latch is not connected
to either Vdd or ground, and so the weak inverter (drawn smaller in the diagram)
dominates and the latch outputs its previous state.
Muller C-element was first used in the arithmetic logic unit (ALU) of the
ILLIAC II supercomputer, proposed in 1958, and operational in 1962.
4. DEVICE SPECIFICATIONS
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The above figure indicates the device specifications
POWER REPORT:
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EXISTING:
POWER REPORT:
PROPOSED
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5. CONCLUSION AND FUTURE SCOPE
In this paper, we presented a low-power delay buffer architecture which adopts

several novel techniques to reduce power consumption. The ring counter with clock gated
by the C-elements can effectively eliminate the excessive data transition without
increasing loading on the global clock signal. The gated-driver tree technique used for the
clock distribution networks can eliminate the power wasted on drivers that need not be
activated. Another gated-demultiplexer tree and a gated-multiplexer tree are used for the
input and output driving circuitry to decrease the loading of the input and output data bus.
All gating signals are easily generated by a C-element taking inputs from some DET flipflop outputs of the ring counter. Measurement results indicate that the proposed
architecture consumes only about 13% to 17% of the conventional SRAM-based delay
buffers in 0.18- m CMOS technology. Further simulations also demonstrate its advantages
in nanometer CMOS technology.We believe that with more experienced layout techniques
the cell size of the proposed delay buffer can be further reduced, making it very useful in
all kinds of multimedia/communication signal processing ICs.
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BIBLIOGRAPHY
[1] W. Eberleet al., 80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital
OFDM transceiver ASICs for wireless local area networks in the 5-GHz band, IEEE J.
Solid-State Circuits, vol. 36, no. 11, pp. 18291838, Nov. 2001.
[2] M. L. Liou, P. H. Lin, C. J. Jan, S. C. Lin, and T. D. Chiueh, Designof an OFDM
baseband receiver with space diversity, IEE Proc. Commun., vol. 153, no. 6, pp. 894
900, Dec. 2006.
[3] G. Pastuszak, A high-performance architecture for embedded blockcoding in JPEG
2000, IEEE Trans. Circuits Syst. Video Technol., vol.15, no. 9, pp. 11821191, Sep.
2005.
[4] W. Li and L.Wanhammar, A pipeline FFT processor, in Proc. Workshop Signal
Process. Syst. Design Implement., 1999, pp. 654662.
[5] E. K. Tsern and T. H. Meng, A low-power video-rate pyramid VQ decoder, IEEE J.
Solid-State Circuits, vol. 31, no. 11, pp. 17891794, Nov. 1996.
[6] N. Shibata, M.Watanabe, and Y. Tanabe, A current-sensed high-speed and low-power
first-in-first-out memory using a wordline/bitline- swapped dual-port SRAM cell, IEEE
J. Solid-State circuits, vol. 37, no. 6, pp. 735750, Jun. 2002.
[7] R. Hosain, L. D. Wronshi, and A. albicki, Low power design using double edge
triggered flip-flop, IEEE Trans. Very Large Scale Integr. (VLSI ) Syst., vol. 2, no. 2, pp.
261265, Jun. 1994.
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[8] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N.Vallepalli, Y.Wang,
B. Zheng, and M. Bohr, SRAM design on 65-nm CMOS technology with dynamic sleep
transistor for leakage reduction, IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 895
901, Apr.2005
APPENDIX A
VHDL INTRODUCTION:
A design engineer in electronic industry uses hardware description language to
keep pace with the productivity of the competitors. With VHDL we can quickly describe
and synthesize circuits of several thousand gates. In addition VHDL provides the
capabilities described as follows:
Power and flexibility
VHDL has powerful language constructs with which to write succinct code
description of complex control logic. It also has multiple levels of design description for
controlling design implementation. It supports design
libraries and creation of
reusable components. It provides Design hierarchies to create modular designs. It is one

language fort design and simulation.
Device Independent design
VHDL permits to create a design without having to first choose a device foe
implementation. With one design description, we can target many device architectures.
Without being familiar with it, we can optimize our design for resource or performance. It
permits multiple style of design description.
Portability:
VHDL portability permits to simulate the same design description that we have
synthesized. Simulating a large design description before synthesizing can save
considerable time. As VHDL is a standard, design description can be taken from one
simulator to another, one synthesis tool to another; one platform to another-means
description can be used in multiple projects.
Benchmarking capabilities
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Deviceindependent design and portability allows benchmarking a design using
different device architectures and different synthesis tool. We can take a complete design
description and synthesize it, create logic for it, evaluate the results and finally choose the
device-a CPLD or an FPGA that fits our requirements.
ASIC Migration
The efficiency that VHDL generates, allows our product to hit the market quickly
if it has been synthesized on a CPLD or FPGA. When production value reaches
appropriate levels, VHDL facilitates the development of application specific integrated
circuit (ASIC). Sometimes, the exact code used with the PLD can be used with the ASIC
and because VHDL is a well-defined language, we can be assured that out ASIC vendor
will deliver a device with expected functionality.
VHDL DESCRIPTION
In the search of a standard design and documentation for the Very High Speed
Integrated Circuits (VHSIC) program, the United States Department of Defense (DOD) in
1981sponsored a workshop on Hardware Description Languages (HDL) at Woods Hole,
Massachusetts. In 1983, the DOD established requirements for a standard VHSIC
Hardware Description Language VHDL, its environment and its software was awarded to
IBM, Texas Instruments and Intermetrics corporations
VHDL 2.0 was released only after the project was begun. The language was
significantly improved correcting the shortcoming of the earlier versions; VHDL 6.0 was
released in 1984. VHDL 1078/1164 formally became the IEEE standard Hardware
Description Language in 1987.
A VHDL design is defined as an entity declaration and as an associated
architecture body. The declaration specifies its interface and is used by architecture
bodies of design entities at upper levels of hierarchy. The architecture body describes the
operation of a design entity by specifying its interconnection with other design entities
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structural description, by its behaviorbehavioral description, or by a mixture of
both. The VHDL language groups, sub programs or design entities by use of packages.
For customizing generic descriptions of design entities, configurations are used.
VHDL also supports libraries and contains constructs for accessing packages, design
entities or configurations from various libraries.
Entities and Architectures:
Entity Declaration:
The ENTITY declaration declares the name, direction and data type of each port of
component.
Syntax: entity name is
Part (
);
End name:
Architecture Declaration:
The ARCHITECTURE portion of a VHDL description describes the behavior of the
component.
Syntax: architecture [arch] <entity name > of <entity name> is
Begin
The begin that follows the signal declaration marks the start of the architecture
body. The follows a process declaration, marked by the keyword PROCESS and an
ensuring BEGIN.
The END statement ending the architecture must be accompanies by the name of
the architecture which must match the name shown in the first of the architecture.
Sequential Processing:
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Sequential statements are statements that execute serially, one after other. In
architecture for an entity, all statement are concurrent, in VHDL, the process statements
can exist in the architecture where all statements are sequential.
Syntax:
[process-label:] process [(sensitivity list)]
Process-declarative-part;
Begin
Process-statement-part::=
Sequential statements};
End process [process-label];
A process statement has a declaration section and a statement part in declaration
section types, variables, constants, subprograms, etc., can be declared. Statements part
contains only sequential statements which consist of CASE statements, IF THEN ELSE
statements, LOOP statements, etc.
Sensitivity list:
This list defines the signals that will cause the statements inside the process
statements to execute whenever one or more elements of the list change value, i.e., list of
signal that the process is sensitive to. Changes in the values of these signals will cause to
process to be invoked.
Sequential Statements:
Sequential statements exist inside the boundaries of a process statement, as well as
in sub programs. The sequential statements that are generally used are:
IF
CASE
LOOP
ASSERT
WAIT
IF statement
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Syntax:
IF (condition) THEN
Sequence_of_statements;
[ELSE condition THEN
Sequence of_ statements ;}
[ELSE
Sequence_of_statements;]
END IF;
The IF statement start with the keyword IF and ends with the keywords END IF.
There are also two optional clauses: they are the ELSEIF clause and the ELSE
clause. The conditional construct in all cases is a Boolean expression. This is an
expression that evaluates to either true or false. Whenever the condition evaluates to a
true value, the sequence of statements following are executed. IF condition is true or false
the sequence of statements for the ELSE clause is executed, if one exits. The IF statement
can have multiple ELSE IF statements parts, only one ELSE statement part, between each
statement part can exist more than one sequential statement.
CASE Statement:
The CASE statement is used whenever a single expression value can be used
to select between a numbers of actions.
Syntax:
CASE expression is
Case_statemant_alternative;
{Case_statemant_alternative ;}
END CASE;
Alternative:
WHEN choice=>
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Where
choice::=
simple_expression
discrete_range
element_simple _name
OTHERS
A CASE statement consists of the keyboard CASE followed by an expression and
the keyboard is. The expression will either return a value that matches one of the choices
in a WHEN statement part or a match an others clause. After these statements are
executed, control is transferred to the statements following the END CASE clause
The CASE statement will execute the proper statement depending on the value of
input instruction. If the value of instruction is one of the choices listed in the WHEN
clause is executed.
LOOP STATEMENT:
The LOOP statement is used whenever an operation needs to be operated. LOOP
statements are used when powerful iteration capability is needed to implement a model.
Syntax:
[Loop_label:][iteration_scheme]Loop
END LOOP [loop-label];
Where iteration_scheme:: =
WHILE condition
For loop_parametr_specification;
And
Loop_parameter_specification::=
Identifier IN discrete_range
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The loop statement has optional label, which can be used to identify the LOOP
statement has an optional iteration scheme that determines which kind of LOOP
statement is being used. The iteration scheme includes two types of LOOP statements, a
WHILE condition LOOP statement and a FOR identifier IN discrete range statement.
The FOR loop will loop as many times as specified in the discrete range, unless the loop
is excited from the WHILE condition LOOP statement will loop as long as the condition
expression is TRUE.
In some languages, the loop index can be assigned value inside its loop to change
its value. VHDL does not allow any assignment to the index. This also precludes the loop
index existing as the return value of a function, or an out in out parameter of the
procedure.
NEXT Statement:
There are cases when it is necessary to stop executing the statements inside
the loop for this iteration and go to the next iteration. VHDL includes a construct that will
accomplish this. The NEXT statement allows the designer to stop processing this iteration
and skip to the successor. When the NEXT statement is executed, processing of the model
stops at the current point and is transferred to the beginning of the loop statement.
Execution will begin with the first statement in the loop, but the loop variable will be
incremented to the next iteration value. If iteration limit has been reached, processing will
stop else the execution will continue.
EXIT Statement:
During the execution of the loop statement, it may be necessary to jump
out of the loop. This can occur because a significant error has occurred during the
execution of the model or all if he processing has already finished early. The VHDL EXIT
statement allows the designer to exit or jump out of a LOOP statement currently in
execution. The EXIT statement causes execution of halt at the location of the EXIT
statement. Execution will continue at the following the LOOP statement.
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The exit statement has three basic types of operations. The first involves an EXIT
statement without a loop label, or a WHEN condition. If these conditions are true, then
the EXIT statement will behave as follows: the EXIT statement will exit from the most
current LOOP statement encounters. If an exit statement is inside LOOP that is nested
inside a LOOP statement, the EXIT statement will exit only the inner LOOP statement.
Execution will still remain in the outer LOOP statement.
ASSERT Statement:
The ASSERT statement is a very useful statement for reporting textual
strings to the designer. The ASSERT statement checks the value of Boolean expression
for true or false. If the value is true, the statement does nothing. If the value is false, the
ASSERT statement will output a user-defined string to the standard output of the
terminal.
The designer can also specify a severity level with which the text string.
The four levels are, in increasing level of severity: note, warning, error and failure. The
severity level allows the designer the capability to classify messages into proper
categories.
The note category is full for relaying information to the user about what is
currently happening in the model. Assertions of category warning can be used to alert the
designer of conditions that can cause erroneous behavior. Assertions of severity level
error are used to alert the designer of the conditions that will cause the model to work
incorrectly, or not work at all. Assertions of severity level failure are used to alert the
designer of the conditions within the model that have disastrous effects.
The ASSERT statement is currently ignored by synthesis tools. Since the
ASSSERT statement is mainly for exception handling while writing a model, no hardware
is built.
Syntax:
ASSERT condition
[REPORT expression]
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[SEVERITY expression];
The keyword ASSERT is followed by a Boolean-valued expression called a
condition. The condition determines whether the text expression specified by the
REPORT clause is output or not. If false, the text expression is output; the text expression
is not output .
The REPORT and SEVERITY clauses are optional REPORT clause allows the
designer the capability to specify the value of a text expression to output. The SEVERITY
clause allows the designer to specify the severity level of the ASSERT statement. If the
report clause is not specified, the default value for the ASSERT statement is assertion
violation. if the severity clause is not specified, the default value is error.
WAIT Statement:
The WAIT statement allows the design the capability of suspending the
execution of process of subprogram. The conditions for resuming execution of the
suspended process or subprogram can be specified by three different means. These are:
WAIT on signal changes
WAIT UNTIL an expression is true
WAIT FOR a specific amount of time
WAIT statement can be used for number of different purposes. The most
common use is for specifying clock inputs to synthesize tools /the WAIT statement
specifies the clock for a process statement that is read by synthesis tool to create
sequential logic such as register and flip-flops. Other uses of WAIT are to delay process
execution for an amount of tome or to modify the sensitivity list of the process
dynamically.
WAIT ON signal:
The WAIT ON signal clause specifies a list of one for more signals upon which the
WAIT statement will waits for events.
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WAIT UNTIL expression:

The WAIT UNTIL Boolean-expression clause will suspend execution of the process
until the expression returns a value of true.
WAIT FOR time-expression
The WAIT UNTIL time-expression clause will suspend execution of the process
for the specified by the time expression. After the time specified in the time expression
has elapsed, execution will continue on the statement following the WAIT statement.
Multiple WAIT statement:
A single statement can include an ON signal, UNTIL expression and FOR timeexpressions clauses.
Subprograms
In many programming languages, subprograms are used to simplify
coding, modularity, and readability of descriptions. VHDL uses subprograms for these
applications for these applications as well as for those that are more specific to hardware
descriptions. Regardless of the application, behavior softwarelike constructs are allowed
in subprograms. VHDL allows two forms of subprograms, functions and procedures.
Functions return value cannot alter the values of the parameters. A procedure, on the other
hand, is used as a statement, and can after the values of the parameters.
Functions can be declared in VHDL by specifying:
1.
2.
3.
4.
The name of the function

The input parameters, if any
The type of returned value
Any declarations required by computation of the returned value.
Producers can also be written in VHDL. A procedure is declared by specifying:

1. The name of the procedure.
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2. The input and output parameters, if any
3. Any declaration required by the procedure itself.
4. An algorithm
The main difference between a function and a procedure is that the procedure
argument list will mostly likely have a direction associated with each parameter, while the
function argument list does not, in a procedure, some of the arguments can be made IN,
OUT or INOUT while in a function all arguments are of mode IN by default can be
default and can be of mode IN.
Side effects :
Procedures have an interesting problem that is not shared by their functions
counterparts. Procedures can cause side effects to occur a side effect is the result of
changing the value of an object inside a procedure when that object was not an argument
to the procedure.
Packages:
The primary purpose of a package is to encapsulate elements that can be shared
(globally) among two or more decision units. A package is common storage area used to
hold data to be shared among number of entities. Declaring data inside of a package
allows the data to be referenced by other entities; thus, the data can be shared.
A package consists of two parts: a package declaration section and a package
body. The package declaration defines the interface for the package, much the way that
the entity defines the interface for a model. The body specifies the actual behavior of the
package in the same method that the architecture statement does for a mode.
The package declaration section can contain the following declarations:
#Subprogram declaration
#Type, subtype declaration
#Constant, deferred constant declaration
#Signal declaration, creates a global signal
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#File declaration
#Alias declaration
#Component declaration
#Attribute declaration, a user-defined attribute
#Disconnection specification
#Use clause
All of the items declared in the package declaration section are visible to any
design that uses the package with a USE clause. The interface to a package consists of
any subprograms or deferred constants declared in the package declaration. The
subprogram and deferred constant must have a corresponding subprogram body and
deferred constants value in the package body or an error will result.
Data Objects:
A data objects holds a value of a specified type. Every data objects belong to one of
the following three classes:
Constants:
The object of a constant class can hold a single value of a given type. This value is
assigned before simulation and cannot be changed during the course of simulation.
Syntax: constant identifier: type: =value;
Variables:
An object variable class can also hold a single value of a given type. However,
different values can be assigned to the object at different times. Variable can be declared
only inside a process.
Syntax: variable identifier: type[:=value];
Signals:
An object of the signal class has a past history of values, a current value, and a set
of future values. Signal objects are typically used to model wires and flip-flops which
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variables and constants are used to model the behavior of the circuit. Signals cannot be
declared in a process statement.
Syntax:syntax identifier: type [: =value];
Files:
Files contain values of a specified type. We use files to read in stimulus and to write
data when using test benches.
Data types:
Every object in VHDL belongs to a certain type. A type is a name that has
associated with it a set of values and a set of operations. All the possible types that can
exist in the language can be categorized into three major categories, which are described
next.
APPENDIX B
XILINX:
Xilinx, Inc. (NASDAQ: XLNX) is the world's largest supplier of programmable
logic devices, the inventor of the field programmable gate array (FPGA) and the first
semiconductor company with a fabless manufacturing model
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IN the Xilinx software we can do simulation and synthesis .The entire processor
will be implemented using the Xilinx FPGAs so you won't have to spend time wiring up
that part of the circuit. You will, however, have to wire the switches and lights that are
used to control the processor, and have to wire the Xilinx part itself to the switches and
lights, but this shouldn't be too bad. You will also use the backplane bus in your lab kit so
that the Triscuit will be built on two boards: one for the Xilinx chip, and one for the
switches and lights.
The HDL Editor feature provides extensive edit and search capabilities with
language-specific color coding of keywords, as well as integrated on-line syntax checking
to scan VHDL code for errors. The Language Assistant feature speeds design entry by
providing a lookup list of typical language constructs and commonly used synthesis
modules like counters, accumulators, and adders.
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Low-Power SRAM-Based Delay Buffer Using Gated Driver Tree

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SRAM BASED DELAY BUFFER USING GATED DRIVER

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

1.5.3 MEMORY CHANNEL

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

2.2 EXISTING TECHNIQUE:

Fig 2.2: Existing Block Of Memory Organisation

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

Fig 2.3: InputBuffer

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

Fig 2.4: Design Of RAS

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

Fig 2.5: Decoder Design

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

SRAM BASED DELAY BUFFER USING GATED DRIVER

Your computer's BIOS chip

CompactFlash (most often found in digital cameras)

Smart Media (most often found in digital cameras)

Memory Stick (most often found in digital cameras)

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

Memory cards for video game consoles

SRAM BASED DELAY BUFFER USING GATED DRIVER

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

Fig 2.7: Ring counter In Parallel in Serial out Shift Register

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SRAM BASED DELAY BUFFER USING GATED DRIVER

Fig 2.8: Ring Counter With SR Flip-Flops

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SRAM BASED DELAY BUFFER USING GATED DRIVER

Table 2.2: SR Flip Flop Truth Table

3. PROPOSED DELAY BUFFERS

Sri Sunflower College Of Engineering & Technology

SRAM BASED DELAY BUFFER USING GATED DRIVER

Fig 3.1: Block Diagram For Proposed Delay Buffer

Fig 3.2: Gated Driver Tree