Process Variation Compensation of a

2.4GHz LNA in 0.18um CMOS Using Digitally

Switchable Capacitance
Yike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang,
Yongming Li, Zhihua Wang

Patrick Chiang
School of Electrical Engineering and Computer Science
Oregon State University
Corvallis, OR, USA
pchiang@eecs.oregonstate.edu

Institute of Microelectronics (IMETC)

Tsinghua University
Beijing, China
chibylxc@tsinghua.edu.cn
AbstractA 0.18um CMOS 2.4GHz LNA (Low Noise
Amplifier) with digitally switchable capacitance has been
designed to investigate its ability to compensate for
performance variation across worst case process conditions.
The effects of transistor model and passive component
variation are first simulated to quantify the range of
performance uncertainty. The use of various methods of
switchable capacitance is then investigated at multiple LNA
nodes to observe the effect on S11, S21, and NF. After
calibration, the new design allows for 300MHz of frequency
tuning and improvements in S11 by 7.2dB, S21 by 2.4dB, and
NF by 0.6dB.

I. INTRODUCTION
While continual scaling of transistor dimensions has
improved the performance and density of digital circuits,
analog and more specifically RF circuits have not found
similar benefit. For a number of reasons, RF circuit design
has become harder to design in deep submicron CMOS. The
major difficulty in these technologies is the issue of process
variability and modeling inaccuracy. As technologies
become more advanced, the ability to model and accurately
predict how the circuit will behave becomes increasingly
difficult. For example, transistor length variation and
threshold voltage mismatch are expected to be more
unpredictable below 130nm CMOS [4]. In addition,
manufacturing foundries currently have a difficult time
predicting the process skew and variation of the devices, as
typically the process needs time to mature. This leads to an
unstable and constantly updating design kit for RF circuit
designers to use, making accurate design simulation
extremely difficult.
The situation is considerably worse if we also consider
the difficulty RF designers have in extracting, estimating and
simulating the passive devices and the associated parasitics.
For example, characterizing on-chip spiral inductors requires
special 3D field solvers to estimate parasitics.

1-4244-0921-7/07 $25.00 2007 IEEE.

Another passive component that cannot be predetermined

with simulation is bond-wire length variation, making it even
more challenging for RF designers to meet the tolerances
necessary for increased variability.
In order to compensate for deep submicron CMOS
process variation and inaccurate parasitic/device modeling,
this paper proposes a digitally switchable capacitance
scheme on a 2.4GHz LNA to calibrate its frequency match
(S11) and power gain (S21). First, the performance variability
of a 0.18um CMOS, 2.4GHz LNA is characterized across
numerous process corners, parasitic values, and bond-wire
variation. After understanding the magnitude of the problem,
two different methods of switchable capacitance are
compared and explored for optimum use in frequency tuning.
Finally, a new LNA is proposed with digitally switchable
capacitance, exhibiting improvements in S11 by 7.2dB, S21 by
2.4dB, and NF by 0.6dB @ 2.4GHz, across worst case
process conditions and 40% bond-wire variation.
A. Circuit Block Diagram

RFin

Pad

Bandpass
filter

Pad

Mixer

Vdd1
Vdd2

Pad
LNAin

LNA

LNAout

Gnd2
Gnd1

Pad

Pad

Fig. (1) Simple LNA circuit

The metrics for designing an LNA include ensuring good
input impedance match (S11), minimizing the noise figure
(NF), and providing sufficient gain (S21) and third-order

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intercept (IP3), while dissipating low power. However, a

good input match (S11) is even more critical because a
preselect filter often precedes the LNA. The performance of
this off-chip filter is extremely sensitive to the match of its
terminating impedance [2] [5].
Fig. (1) shows a traditional LNA circuit mentioned in
[1][2]. Cascode transistor M2 reduces the Miller effect by
ensuring a low impedance at the drain of the amplifying
device. The source-degeneration inductor generates a real
part 50 ohm real-part for the input impedance. This narrowband approach achieves the best noise performance of any
architecture; however, using this technique results in an
input impedance that is extremely sensitive to process
variation. A simple analysis of the input impedance shows
that:
Z in = s ( Ls + L g ) +

g
1
+ m1 Ls wT Ls
sCgs Cgs

(1)

Since the fT is more that 10 GHz and the Ls is less than

1nH, the gate inductance Lg, which is used to set the
resonance frequency, is about 8 nH in this 0.18um CMOS
process. Due to the inaccuracy ( 20%) of bond-wire
inductance, an on-chip spiral Lg is adopted here at the price
of increased thermal resistor noise. Another on-chip
inductance Ld is used as the load of the LNA to increase the
maximum output voltage compared with resistor load. Ld
resonates with the load capacitance and provide a load
impedance for the LNA as
Rld = Ld Qld (2)
Normally the LNA drives the input capacitance of a
subsequent mixer, meaning that the output impedance (and
S-parameters) cannot be simulated. For ease of design
simulation, we used a buffer with wide-band 50 Ohm output
impedance at the LNA output.
B. Simulation Across Process Corners
There are four main realistic variations: Onchip
inductance and capacitor corners (max,typ,min); Bond-wire
inductance variation (1nH20%); Temperature variation
(-30 to 70); and Transistor corner (ff,tt,ss). The former
two variations are the main contributors to operating
frequency deviation while the latter two mainly cause gain
degradation. The simulation results are shown in Fig. (2),
for 5mA current consumption. When the former two
variations are simulated together, the worst case S11
frequency deviation is about 320MHz, while S22 keeps fairly
stable, as show in Fig. (2). The simulations across process
variation show as much as a 2.2 dB decrease in S21, 0.3dB
increase in NF, and more than a 10 dB increase in S11. As
mentioned in section A, the worst problem of these is the
mismatch of the input impedance by >10dB, seriously
affecting the preceding stage preselect filter.
If the last two variations are considered (temperature
and transistor corner), S21 is seen to vary by 2dB. S22 is
relatively unchanged due to the wideband impedance of the
output buffer.

Fig. (2) Worst case performance variability

II.

SWITCHABLE CAPACITORS

A. Capacitive Compensation of Input Match

As mentioned previously, the S11 frequency match is very
significant for the entire RF system performance. According
to Eq. (1), there are three possible match locations (Ls, Lg
and Cgs) at the input node. Because of the limited value of
Ls, it is not feasible to change Ls for calibration. In addition,
Cgs is also unchangeable after die fabrication. It may appear
that only Lg can be used for input match tuning, as described
in [6]. However, this method suffers disadvantages such as
added switch resistor noise resulting in increased NF, and
difficulty in simulating the inductance variation from the
number of spiral inductor turns. Nevertheless, we can
deliberately add a new variable to calibrate S11--a shunt
capacitance (Cg) between node A and ground as shown in
Fig. (5).

Fig. (3) Input section of LNA

Reference [3] explores the effect caused by the parasitic
capacitance Cpad, consisting of the pad and ESD
capacitance. The analysis method of our introduced Cg is
similar to the one in [3]. The equivalent source impedance
seen to the left of reference plane A is given by Rb+jwLb,
where
Lg C g (02 L2g + Rs2 )
,
(3)
Rs

Rb =

02C g2 Rs2 + (1 02Cg Lg )

Lb =

02C g2 Rs2 + (1 02C g Lg )

It can be seen that variation in Lg can change both the

2563

real and imaginary parts. As shown in Fig (4), sweeping Cg

through the two process extremes can also adjust S11 across
the real axis of the Smith chart, calibrating the input
impedance variation by counteracting its imaginary part
while also changing its real part.

For an inversion MOS capacitance, the Source/Drain

nodes are connected to a digitally controlled register. Due to
the C-V characteristic of a MOSFET, such as a PMOS
device, when Source and Drain are set to GND, the
capacitance is smaller than when Source/Drain are set to
VDD. Since there is no series MOS switch, the NF should
be better when compared with the other switched capacitor
topology. However, the poor on/off capacitance ratio of the
inversion MOS capacitance limits its utility for match
tuning.
For the NMOS linearly in series with the MIM cap, the
main consideration is the noise source introduced by the
1
(8)
switches. For R = L
on

Fig. (4) Sweep Cg under three situations

While it has been shown that this variable capacitance
technique can help calibrate the input S11 match, this
method also introduces some possible negative effects when
compared with the traditional LNA performance. Equation
(3) shows that the introduction of Cg will increase the
equivalent source resistance Rb. For

W K (Vgs VT )

The scaling down of both Vt and L in deep submicron

CMOS will improve the noise performance of this MOS
switch. Also, the smaller area of future CMOS transistors
will result in less parasitic capacitance, thereby emulating an
ideal switch. Fig (6) shows the effect of NMOS switch
width on S11, S21, and NF. Larger width means smaller NF,
but the larger parasitic capacitance affects the match tuning
range. The optimum value of the switch width is set to 18u.

T2
Rb
(5)
2 Rb Cgs
2 ( Rb + Rin )2

2
(6)
NF 1 + ( o ) 2 g m Rb + ( o )2
+
T
T g m Rb

Qin =

(4)

PCC = 4

This increase in Rb will decrease Qin according to equation

(4), suggesting worse noise performance but better linearity
under the same power consumption. According to equation
(6), there is an optimum value of Rb to attain the best noise
performance; for PCC(power to current gain) in (5),
resistance mismatch (Rb>Rin) would improve power gain.
This trade-off between various performances needs to be
considered carefully when adding this capacitor Cg.
B. Description of Switchable Capacitance
The former analysis proves the feasibility of changing
capacitance to calibrate S11 and S21. Note that in equation (4)
increasing Cg will seriously decrease Qin; therefore, the
maximum Cg should be limited to a certain value.
Furthermore, in order to calibrate the specific S11 variation,
the range of Cg must be between 100fF to 500fF. As diodes
and MOS varactors have high minimum capacitances
(400fF), they are not suitable for use in a switchable
capacitance bank. However, we still can use two kinds of
switchable capacitance: a NMOS switch in series with a
MIM cap, and a NMOS (or PMOS) in inversion mode.

Fig. (6) Performance vs. switch width

C. New LNA Topology
In order to compensate for the 320MHz S11 frequency
variation at the input, as well as the S21 gain reduction at the
output, we designed a LNA with switchable capacitance on
node A and B as shown in Fig (7). C1 is digitally controlled
MOS capacitance while C2 consists of 100fF MIM
capacitance in series with a MOS switch. The two methods
are combined together for S11 calibration to attain wide
tuning range and accurate tuning steps. Since the S21
variation is not as severe as S11, only the MIM capacitance
method is used at node B.

Fig. (5) Types of switchable capacitances

Fig. (7) LNA with switchable capacitance

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III.

SIMULATION RESULTS / DISCUSSION

Fig. (8) S11 tuning range under typical situation

Fig (8) shows a S11 center frequency tuning range of
320MHz across the entire switch capacitor range,
maintaining S11 below -13dB. Fig. (9) shows the
performance before calibration across process corners; Fig.
(10) shows the performance after optimum capacitive
calibration. It is shown that the center frequency has a well
centered, improved frequency match. However, due to the
additional capacitive loading, the gain and NF has
degenerated by 0.2dB in the worst case. The results under
different process variation are shown in Table (1). It is
interesting to note that performance has not changed
significantly from the classical, non-calibrated LNA of Fig.
(2) while S11 match has improved substantially. (NF increase
of 0.3dB, S21 decrease of 0.6dB)

Fig. (10) Calibration results under extreme situations

IV. CONCLUSION
This paper proposes a digitally switchable capacitance
scheme on a 2.4GHz LNA to calibrate its frequency match
and power gain. The simulation results show improvements
in S11 by 7.2dB, S21 by 2.4dB, and NF by 0.6dB @ 2.4GHz,
across worst case process conditions and 40% bond-wire
variation. Furthermore, the improvement in center frequency
deviation of S11 suggests a significant benefit to the complete
RF system performance.
ACKNOWLEDGEMENTS
This research was partly supported by National Natural Science Foundation
of China (No. 90407006), and by the US National Science Foundation,
East Asia and Pacific Summer Institute Program.
REFERENCES
[1]

[2]

[3]

[4]

Fig. (9) Variation with typical Cg load LNA

Process
S11(dB)
S22(dB)
S21(dB)
NF
Calibrate

Classic
LNA
Worst
-9.9
-12.5
18.4
2.8

[5]

Switch capacitance LNA

Typ
-15.5
-13.0
20.2
2.6

-11.0
-13.0
20.2
2.6
before

Max
-18.2
-16.0
22.6
2.0
after

Min
-9.5
-11.0
17.9
3.0
before

-13.2
-12.0
17.8
3.1
after

[6]

Table (1)

2565

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