Birla Institute of Technology and Science, Pilani

MEL G623 Advanced VLSI Design

Mid semester Test (Open book) I Semester 2013-2014
Max. Marks=25
Time: 90 min.

Date: 05-10-2013

NOTE: Answers should be clear, concise and legible. Specify your assumptions clearly. Do all parts of same question together.
Diagrams should be neat. NO MARKS for unnecessary theoretical explanation. Justify your answers

Q1. Consider the pipeline shown in fig 1. The minimum and maximum delays through the logic are annotated on the
figure, and the flip-flops are pulsed registers and have the following properties: tclk-q = 300ps, tsetup = -50ps, and
thold = 300ps. You can assume that the clock has no jitter, and tskew1 and tskew2 are positive.
Clk3
TSKEW 2
CL 3
Tpmax= 0.83ns, tpmin=0.2ns

CL 1

TSKEW 1

Fig 1

CL 2
tpmax 0.8ns, tpmin=0.15ns

Tpmax= 1ns, tpmin=0.25ns

Clk

Clk2

a) Determine the width of the pulse/ glitch in flipflops

b) What is the minimum clock cycle time if tskew1 = 100ps and tskew2 = 150ps? Will pipeline
operate? What should be highest value of tskew1 before this pipeline fails a hold-time constraint?
c) Given minimum clk cycle time is 2000 ps with 50% duty cycle , determine maximum slack
borrowing possible if flipflops are replaced by level sensitive latches with following parameters----td-q= 70ps, tsu=50ps, thold= 50ps, tclk-q=80ps. Assume skew values are as given in part (b)
(7)
Q2. Consider the circuit shown in fig. 2.

Fig 2

To connect a processor to an external memory an off -chip connection is necessary. The copper wire on the
board is 15 cm long and acts as a transmission line with a characteristic impedance of 100. The memory
input pins present very high impedance which can be considered infinite. The bus driver is a CMOS inverter
consisting of very large devices: (50/0.25) for the NMOS and (150/0.25) for the PMOS, where all sizes are in
um. The minimum size device, (0.25/0.25) for NMOS and (0.75/0.25) for PMOS, has the on resistance 35
k. The wire inductance per unit length equals 75*10-8 H/m.

a) Determine the time it takes for a change in the signal to propagate from source to destination (time
of flight).
b) Determine how long it will take the output signal to stay within 10% of its final value.. Assume a
supply and step voltage of 2.5V. Draw the lattice diagram for the transmission line.
c) Determine for each of the statements below if it is true, false, or undefined, and explain in one line
your answer.
i. When driving a small fan-out, increasing the driver transistor sizes raises the short-circuit power
dissipation.
ii. Reducing the supply voltage, while keeping the threshold voltage constant decreases the short-circuit
power dissipation.
iii. Moving to Copper wires on a chip will enable us to build faster adders.
iv. Making a wire wider helps to reduce its RC delay.

v.

Going to dielectrics with a lower permittivity will make RC wire delay more important

[7]
Q3. For design style shown in fig. 3,
a) Describe the operation of this gate in terms of its
Fig 3

behavior during the pre-charge phase.

b) Write only one major [delay or power ] advantage and

disadvantage of using this logic style in comparison to
the DCVSL logic style
c) Use this logic to design a 3 bit shift register using
asynchronous pipeline 4 phase dual rail approach.
Sketch the pipeline and draw the circuits of shift
register. Completion signal generation unit
[6]

Q4. For the register circuit shown in fig. 4

a) Briefly describe the operation of the circuit.
b) If all the NMOS transistors are of the same size, and all
of the PMOS transistors are of the same size (two times
wider than the NMOS), roughly sketch the timing
diagram showing transitions at each node as data
changes from logic 0 to logic 1
c) Explain the purpose of data transition lookahead circuit

Fig 4

[5]

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