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Figure 1: Samsung 3x DDR3 SDRAM Die Photo
Next we did a bevel-section of the part to take a look at the cell array. We were surprised with what we found. The capacitors
are laid out in a square array instead of the more usual hexagonal pattern (see below), and the wordline (WL) and bitline (BL)
pitches are both about 96 nm. The usual method of determining DRAM node is to take half the minimum WL or BL pitch. That
places this DRAM at the 48 nm process node, the same as the previous Samsung generation (at 48 nm). So why does the die
size look like it should be a smaller technology? The answer lies in the cell.
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Figure 3: 8F architecture
Figure 4: 6F architecture
show that they both have very similar layouts. The angle of the active silicon (diffusion) direction is about the same. The active
areas are ovals. Each diffusion has two wordlines crossing it. There is a gap in all the active stripes, such that a third WL does
not cross active on this diagonal active stripe.
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This new DRAM therefore has a very similar cell layout to the previous one. In both cases the wordlines do not have a transistor
under them at every possible location that a transistor would fit. Rather, one of every three possible transistor locations is filled
with a break in the diffusion stripe. In our opinion this is a critical factor in identifying a 6F cell, that in a 6F architecture 2/3 of
the WL/BL intersections are filled with storage cells. As we noted above, a 4F cell really should have transistors at every
possible transistor location. When we look at the pitch of the diffusions in this new DRAM, we see it is much tighter. In fact,
along the WL direction the diffusion pitch is now 64 nm, whereas in the 48 nm SDRAM this pitch was 96 nm. So if you take half
the minimum pitch in the chip as the node, this is a 32-nm part (ITRS 2009 still defines F as half the contacted M1 pitch, which
would be 48 nm).
Conclusion
So, do we have a 32 nm node, and a 6F architecture? Maybe. The only issue is that if we use 32 nm as F, then when we plug
that into the 6F equation we get 0.0061 um as the cell size. However, the cell size is actually 0.0092 um. If we use that
number and use the equation to calculate F we find that F=39nm. So do we call this a 32 nm or a 39 nm node? It depends
how you calculate it either way its a 3x! So, although its a little disappointing that I dont think we can announce the worlds
first 4F DRAM, we can announce the worlds smallest node, 32 or 39 nm, production 6F DRAM. Samsung have had to put in a
few process tweaks to squeeze the cells into the much smaller area, mostly at the transistor and STI level. Were still looking at
it, so we may not have the whole story yet, but some of what weve seen so far is:
Ti-? (likely TiN)-gate buried wordline transistors
STI filled with nitride in the array
Bitlines at the same level as peripheral transistors.
See available Circuit Analysis and Process Analysis Reports on the Samsung K4B2G0846D-HCH9.
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