Report

VISVESVARAYA TECHNOLOGICAL UNIVERSITY
Jnana Sangama, Belgaum - 580 014
A
Project Report
on
LAYOUT OPTIMAZATION OF LOW
DROP-OUT,HIGH PSRR LDO FOR RF
APPLICATION
Submitted in Partial Fulfillment for the award of the Degree
Master of Technology
in
VLSI DESIGN AND TESTING

Submitted By
Ms.JYOTHI.M.H
(USN:2BV12LDT02)
Under the guidance of
Prof. Sujata Kotabagi
B. V. BHOOMARADDI COLLEGE OF
ENGINEERING AND TECHNOLOGY HUBLI-31
2013-2014
B.V.BHOOMARADDI COLLEGE OF
ENGINEERING AND TECHNOLOGY HUBLI-31
CERTIFICATE
This is to certify that the Project report entitled LAYOUT OPTIMIZATION OF LOW DROP-OUT, HIGH PSRR LDO FOR RF
APPLICATION is a bonafide work carried out by Ms.JYOTHI.M.H
bearing (USN:2BV12LDT02) as a part of VISVESVARAYA TECHNOLOGICAL UNIVERSITY M.Tech in VLSI DESIGN AND TESTING at B.
V. Bhoomaraddi College of Engineering and Technology, Vidyanagar, Hubli
for the academic year 2013-2014.
Prof. Sujata Kotabagi

Guide
Dr. Uma Mudenagudi

Head of the Department
Dr. Ashok Shettar

Principal
External Viva
Name of Examiners
Signature with date
1) ..................
2)..................
ABSTRACT
In this paper we present a design of a cmos amplifier with the buffer

configuration which operates at 1.8V power supply. Here we are making to
design the op amp as a buffer which drives a 2pf capacitive load. The proposed design produces an open loop gain of 50dB and Unity Gain Bandwidth
of 10MHz in UMC 0.18micron technology. The op amp designed is a single
stage differential amplifier. The differential amplifier plays an excellent performance as input amplifier and application with the possibility of feedback
to the input. The differential amplifier circuit is characterised in terms of
self bias capability, common mode rejection, voltage gain and the unity gain
bandwidth product.
ACKNOWLEDGMENTS
The sense of contentment and elation that accompanies the successful

completion of our project and its report would be incomplete without mentioning the names of the people who helped us in accomplishing this.
We sincerely thank our Guide Prof. Sujata S. Kotabagi for their
inspiring guidance and promising support they gave during the course of
completion.
We take this opportunity to thank our principa Dr. Ashok Shettar, for
providing healthy environment in the college, which helped in concentrating
on the task. We express a deep sense of gratitude to our H.O.D. Dr.Uma
Mudengudi for providing the inspiration required for taking the project to
its completion.
Last but not the least we like to thank all the staff members, teaching
and non - teaching staff for helping us during the course of the project.
Ms.Jyothi.M.H
Contents
1 INTRODUCTION
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Problem statement . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 LITERATURE SURVEY
2.1 Understanding The Schematic Connectivity
2.2 Layers And Connectivity . . . . . . . . . . .
2.3 Transistor Layout . . . . . . . . . . . . . . .
2.4 Bulk Connections . . . . . . . . . . . . . . .
2.5 Process Design Rules . . . . . . . . . . . . .
2.6 vertical Connnection Diagram . . . . . . . .
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4 RESULT
4.1 The Layout Design Of LDO Regulator . . . . . . . . . . . . .
4.1.1 Design of Low Dropout linear regulator . . . . . . . . .
4.1.2 Optimized Layout Design . . . . . . . . . . . . . . . .
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3 GENERAL GUIDELINES FOR LAYOUT

3.1 Guidelines For The Layout Of Power Lines . .
3.2 Guidelines For The Layout Of Signals . . . . .
3.3 Guidelines For The Layout Of The Transistors
3.4 Multifinger Transistors . . . . . . . . . . . . .
3.5 Symmetry . . . . . . . . . . . . . . . . . . . .
3.6 Resistors . . . . . . . . . . . . . . . . . . . . .
3.7 Capacitors . . . . . . . . . . . . . . . . . . . .
3.8 Electromigration . . . . . . . . . . . . . . . .
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5 CONCLUSION AND FUTUREWORK

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5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 Futurework . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of Figures
1.1
Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
2.2
2.3
2.4
2.5
2.6
Example Of Cross-Section Process Steps . . . .

PMOS and NMOS Transistors . . . . . . . . . .
Simple PMOS Transistor Layout . . . . . . . .
Simple NMOS Transistor Layout . . . . . . . .
Wafer Cross-Section Showing Bulk Connections
Vertical Diagram Of Connectivity For A DRAM
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3.1
3.2
3.3
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3.16
3.17
Routing Line Width Considerations And Routing Direction

Example Cell Template . . . . . . . . . . . . . . . . . . . .
Fingering Of Transistors . . . . . . . . . . . . . . . . . . .
Example Of Fingering A NAND Gate . . . . . . . . . . . .
Transistor Power Sharing Example . . . . . . . . . . . . .
Example Of Soft Connections . . . . . . . . . . . . . . . .
(a)Simple Foldinh Of A MOSFET,(b) Multiple Fingers . .
Differential Pair . . . . . . . . . . . . . . . . . . . . . . . .
Layout Of MO And M1 With Different Orientation . . . .
Layout With Gate-Aligned Devices . . . . . . . . . . . . .
Layout With Parallel-Gate Devices . . . . . . . . . . . . .
Layout Of Lager Resistors . . . . . . . . . . . . . . . . . .
Serpentine Topology . . . . . . . . . . . . . . . . . . . . .
Layout Of Capacitor . . . . . . . . . . . . . . . . . . . . .
Simple Examples Of Bent Gates . . . . . . . . . . . . . . .
Bent Transistor To Minimize Area . . . . . . . . . . . . . .
Electromigration Currrents . . . . . . . . . . . . . . . . . .
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4.1
4.2
Basic Structure Of LDO Regulator . . . . . . . . . . . . . . . 26

LDO Schematic . . . . . . . . . . . . . . . . . . . . . . . . . 27
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LDO Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 1
INTRODUCTION
During the past two decades, the electronics industry has grown very fast
both in size and in complexity. Designers began talking about chip design
only 25 years ago. At the beginning, the idea was to design chips to reduce
the computer size. Instead of room-sized computers, we have now ended up
with PCs running at a speed that back then was considered impossible to
imagine. The application of IC technology has exploded into many parts of
our lives This was a long and laborious task. The market demands and advances in technology brought about an immediate need to develop software
and hardware solutions to improve the time-to-market of the chip designs and
especially to automate the entire process. Accuracy of the final masks was
also a driving force in the computerization of layout design. The first platforms were custom built to ensure that graphics applications ran quickly and
had sufficient capabilities. Companies such as CALMA (Data General) built
mainframe-sized machines and developed specialized software for printed circuit board (PCB) and integrated circuit (IC) applications. The fundamental
concepts behind producing quality layout are based on physical and electrical properties that never change.This report is organized as follows,sectionII
presents literature survey.In sectionIII presents genaral guidelines for layout
and Finally, conclusions are summarized in section IV.
1.1
Motivation
An approach for developing a component-level use of a layout compiler

which results in a circuit layout along with a user-specified performance .
1
Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Application
The methodology is based on sensitivities of the circuit performance with
respect to layout interconnect parasitics and recognition rules of various configurations and topologies. The parasitic effects, which are important from
an analog layout point of view,as to be examined using different methods to
minimize them.
The layout is an important concern for the global performance of any LDO
circuit. It is highly affected by the mismatch that occurs during the process
fabrication between the parameters of an equally group designed. The mismatch not only affects the DC performance, where it causes nonzero offset
voltage, but also affects high frequencies reducing the PSRR performance.
Moreover the interconnect crossovers in the amplifier design can produce parasitic or undesired capacitance. This problem can be solved with a careful
design and shielding of the amplifier inputs with metal lines connected to
the ground. Moreover the design of transistors with translational symmetry
(i.e. each transistor is a copy of the other without rotation), reduces the
capacitance.
The mismatch of the input transistors of the amplifier can be reduced with
methods commonly used in conventional amplifier design, such as placing
these input transistors with commoncentroid method and designing them in
large width.
1.2
Problem statement
layout optimization of low drop-out,high PSRR LDO for RF application.
1.3
Methodology
The scaling of feature size in VLSI circuits, both digital and analog,
has been one of the strongest driving forces toward the rapid development of
electronics technology. Layout is the process of specifying the physical placement of and interconnections between all of the devices in a circuit. The
accomplished layout is used to generate the entire mask layers used for chip
fabrication.fig 1 shows the design flow of the layout.The IC layout design is
assembled by using cell layouts from the cell library; this assembled IC design
layout is ready for submission for fabrication.
Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Application
The target layout must be passed Design Rule Check (DRC) and Layout
versus Schematic (LVS). Optionally, if desired, the designer may also undertake a SPICE-level simulation of the interconnected functional cells before
and after the layout step. Low Dropout regulator (LDO) is an analog chip
and its function is providing stable output voltage when the input voltage
fluctuations. Even if we input the same signals to LDO regulator the output results from different layout also have some differences. Therefore, this
requires us to optimize the layout to achieve more accuracy output results.
Figure 1.1: Methodology
Chapter 2
LITERATURE SURVEY
2.1
Understanding The Schematic Connectivity
In implementing the layout of any schematic, there is more to the final design
than is explicitly shown. Connections appear on a schematic as a simple line
drawn from point A to point B, or a simple connection of two transistors in
series or in parallel. In reality, a line represents a signal path that needs to
be physically implemented and optimized. The gates and transistors should
look familiar, and the different transistor representations of the various gates
have been described. The challenge now is to understand the connectivity of
the devices.
2.2
Layers And Connectivity
Let us simplify the types of layers that are used and introduce the concept
of mask layers and drawn layers. If we analyze most CMOS processes, we
find that there are four basic layer types and shown in figure2.1
1. Conductors: These layers are conducting layers in that they are capable of carrying signal voltages. Diffusion areas, metal and polysilicon
layers, and well layers fall into this category. Layers and Connectivity
2. Isolation layers: These layers are the insulator layers that isolate each
conductor layer from each other in vertical and horizontal directions.
4

Application
This isolation is required in both the vertical and horizontal direction

to avoid short circuits between separate electrical nodes.
3. Contacts or vias: These layers define cuts in the insulation layer that
separates conducting layers and allow the upper layer to contact down
through the cut or contact hole. Metal vias or contacts are examples of
these. Openings in the passivation layer for bonding pads are another
example of a contact layer.
4. Implant layers: These layers do not explicitly define a new layer or
contact, but customize or change existing conductor propriety. For
example, diffusion or active areas for PMOS and NMOS transistors are
defined simultaneously. A P+ mask is used to create P+ implant areas
that define certain diffusion areas to P-type by the use of a P-type
implant.
Figure 2.1: Example Of Cross-Section Process Steps
2.3
Transistor Layout
Before we start to discuss the layout of transistors The top half of Figure
2.2 shows the basic symbol representations of both PMOS and NMOS transistors. The length and width of the transistors are shown. Also remember

Application
that the bulk connection is there, but is hidden from view to avoid cluttering
the schematic.The amount of current flow is determined by the device size.
We hinted that the current flow is increased as the width of the device is
increased or the length of the device is decreased. Lets see why this is by
understanding the physical characteristics of the transistor as determined by
the layout of the device.Figure 2.3 shows a simple MOS transistor layout
All four terminals of the transistor are shown and labeled. The gate of the
transistor is defined by a polygon of polysilicon.
1. Areas of active or diffusion adjacent to the gate of the transistor define
the source and drain areas. Note that the source and drain labels are
in fact interchangeable.
2. This transistor happens to be a PMOS transistor and the active areas
are doped P-type by the P+ implant layer.
3. This PMOS transistor is located in an N-type well called an N-well.
This forms the transistor bulk node. An N-type active area (without
the P+ implant layer) forms a connection to the N-well because the
N-well and active areas are of the same type (N-type).
4. The source, drain, and well connection are themselves connected by
another contact layer. This contact layer would typically be the contact
layer for the first layer of metal.
5. The width and length are labeled correctly. The width is greater than
the length! The length and width of transistor are the two most important dimensions of a transistor that we need to fully understand.
As we stated previously, when people in the industry talk about the
gate size of a specific technology, they are referring to the minimum
gate length. Note the following: In terms of layout design, the length
of the transistor is the distance between the source and the drain of a
transistor. This may not be intuitive, because the physical dimension
of the transistor length is smaller than the width.
6. In terms of transistor performance, the length of the transistor is the
distance electrons have to travel when the gate is on or open to produce
a measurable current flow. Remember, it is the gate voltage that controls the flow of current. If the distance between the source and drain
is reduced, the gate voltage has a stronger influence in enabling current

Application
flow. The bottom line is that in the same process technology, if two
transistors have the same width but different lengths, the transistor
with the shorter gate length will produce more current. More current
conceptually means faster performance.
7. The length of a transistor in terms of manufacturing capabilities is the
narrowest possible piece of polysilicon (poly) that can be manufactured
reliably. Smaller poly dimensions and thus smaller transistors results
in smaller ICs, so it is attractive to use the minimum gate length to
minimize chip area. Lets now consider the width of a transistor. The
width of a transistor should be thought of as the number of parallel
channels that are available for current to pass from the source to the
drain. Wider transistors have more channels available; more channels
mean more current. Once again comparing two transistors, this time
each having identical gate lengths but different gate widths, the transistor with the larger gate width will produce more current. To help
you remember the convention of transistor length and width, think of
a transistor like a bridge.
8. The length of the bridge is the distance between the two sides of the
river and the width of the bridge is the number of lanes of traffic that
the bridge can accommodate. The amount of traffic that can cross the
bridge is limited by the length and width of the bridge in the same way
that current is limited by the length and width of the transistor If the
design of the bridge is to allow 100 cars to cross over in 1 minute, then
the bridge needs to be made wide enough to achieve this goal. In most
cases the length of the bridge is fixed (similar to the minimum allowable
gate length) and the only degree of freedom we have to achieve our goal
is to adjust the width.
9. One last concept to consider. There are cases when we might want a
slow or weak transistor! This is easily achieved by minimizing the width
of the transistor and/or increasing the transistor gate length. Delay
elements or weak feedback devices are examples where slow transistors
are desired. It may turn out that in these cases the gate length does
turn out to be greater than the width (Figure 2.3). The first important
thing to remember is the difference between the length and width of a
transistor and how to apply this to transistor layout! For completeness,
Figure 2.4 shows the layout of an NMOS transistor.

Application
10. This NMOS transistor is not located in any type of well and thus sits
in the bare substrate. In this case, the substrate can be deduced to be
P-type. The substrate forms the transistor bulk node.
11. A P-type active area (with the P+ implant layer) forms a connection
to the substrate because the substrate and active areas are of the same
type (P-type).
Figure 2.2: PMOS and NMOS Transistors
Figure 2.3: Simple PMOS Transistor Layout

Application
Figure 2.4: Simple NMOS Transistor Layout
2.4
Bulk Connections
Now that we know how the two basic kinds of transistors work and look,
lets review the bulk connection node and see how it is connected. This is
most easily understood by understanding a cross-section of the wafer and
transistor
Note that a layout designer can only understand this concept and cannot
influence its design. Most (but not all!) raw silicon wafers these days are
P-type, so of the two transistor types, an NMOS transistor is the easier to
design. The transistor layout is simply implemented in the bare substrate
shown in figure 2.5. To generate PMOS transistors we need to create a separate bulk node and therefore need another layer. This is typically called an
N-well; when implemented, it forms an island of N-type substrate. Implementing P-type active regions within this N-well creates a PMOS transistor
with a bulk connection as defined by the N-well .An NMOS transistor design that has a different bulk node than that of the substrate. P-type well
(P-well) has been implemented in the N-well. This region creates a separate
P-type bulk node for the transistors implemented within this region. This
is an example of substrate connection in a DRAM process. In the case of
an N-type wafer, the polarities of the transistor connections are simply the
reverse of those shown previously.

Application
Figure 2.5: Wafer Cross-Section Showing Bulk Connections
2.5
Process Design Rules
Design rules are the rules that have to be respected when a given design is
laid out. There are design rules for all of the components we have been introduced to: polygons and paths, transistors, and contacts. Fundamentally,
these design rules represent the physical limits of the manufacturing process.
Within a company that has the capability to manufacture integrated circuits, there is a group of people who define and optimize the manufacturing
process. This processing group defines the design rules by trading off the
cost-to-manufacture and yield, among other things, against the minimum
feature size that is manufacturable by the equipment and processing steps.
Other factors that influence the definition of design rules could be the maturity of the manufacturing tools and process or the market requirements for
an IC or foundry service. Overall, design rules are put in place to help layout
designers understand and account for physical three-dimensional limitations
and manufacturing tolerances within the CAD and layout tool environment.
2.6
vertical Connnection Diagram
In the majority of ASIC processes there are very straightforward rules for
connectivity. An ASIC process has one poly for the gate and three to six
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Application
Figure 2.6: Vertical Diagram Of Connectivity For A DRAM Process

metals. That means that we have to work with one contact type and two to
five types of vias. The connectivity is easy to understand because to connect
from active to metal6 we need all the possible contacts and vias. In more
complicated processes, it is advisable to generate a vertical diagram of layer
connectivity so the layout designer can fully understand the connectivity
scheme. Figure 2.6 shows a DRAM process that is made with four poly
layers and three metal layers. In this type of process there are restrictions
on layer uses and connection rules.
11
Chapter 3
GENERAL GUIDELINES
FOR LAYOUT
3.1
Guidelines For The Layout Of Power Lines
Power supply lines have to be determined before starting the layout of any
cell. Specific guidelines for power lines include the following:
1. Determine line width based on the following: Does the line provide
power only for internal use, or is there a requirement for the line to
feed other cells and be a part of the chips power grid? This is critical
information that can be determined from the layout floor plan. Use resistivity information of the different layers to determine the appropriate
width of the lines.
2. Use lowest level of metal for power for transistor level cells. It is important to consider that using higher layers of metal for power requires
vias and local interconnect polygons to connect transistors to supplies.
This will take space and limit the porosity of the cell. Generally use
the lowest level of metal for power that the process and design allows.
3. Avoid notching power lines. Power lines carry large amounts of current;
therefore, it is important to make sure that they are routed with a consistent width and never notched. Any notches in a line create potential
fuses that may break the power line under high current conditions.
4. Avoid over the cell power routing. Unless the power is routed using
12

Application
automated tools, it is not advisable to run power supply lines over

the cell. Keep the power lines inside the cell to ensure that the cell
is correct by construction. Power routing outside the cell is ideally
limited to connections between cells.
3.2
Guidelines For The Layout Of Signals
The following is a list of guidelines specifically for routed signals. More details
on each of these concepts are presented in later chapters.
1. Choose routing layers based on process parameters and circuit requirements. For each process a standardized list of routing layers should be
determined based on layer resistance and capacitance. Layers such as
N-well, active, and high-resistance poly gate are not used for routing.
Priorities between routing layers can also be standardized using the
same criteria.
2. Minimize the width of input signals. Minimizing the routing of the
signals within the design is also important. This reduces the input
capacitance for the signal. This is important for signals that are part
of cells that are used many times. An example of this would be a clock
signal within a cell.
3. Choose routing width carefully. The choice of the width of a routing
signal should be made judiciously. It is tempting to simply use the
minimum design rule line width as the routing width. This is not
practical in all cases because connections must be made to every line.
These connection points require a via or contact, and as you can see in
Figure 3.1, the space required for a via or contact is generally wider than
the minimum width rule for the routing layer.It is perhaps more efficient
to use a width of line that accommodates both a via and contact. This
line would be wider but is much easier to manage and maintain as it
avoids jogging other signals around the contact point.
4. Maintain a consistent routing direction within a cell or block . Then,
when a layout designer wants to change signal direction, it will take
only one type of via and it will not interfere with the porosity of the
cell. In general it makes sense to keep a consistent metal direction for
13

Application
each layer and alternate the direction from layer to layer. For example,
if metal1, metal3, and metal5 are routed horizontally, then metal2,
metal4, and metal6 should be routed vertically.
5. Label all important signals. This is very important for the layout verification process, especially LVS. Error diagnosis, short isolation, and
LVS run time are all easier when nodes are labeled.
6. Determine the minimum number of contacts for every connection. Dont
assume that a single contact or via for every connection is enough.
Some memories, for example, are using double contacts everywhere
possible to increase reliability.
Figure 3.1: Routing Line Width Considerations And Routing Direction
14

Application
3.3
Guidelines For The Layout Of The Transistors
The following is a list of guidelines specifically for a cell-level design environment.

1. Use a predefined template for PMOS and NMOS transistor placement.
The architecture of a cell should be defined beforehand, and this template should encapsulate the basic floorplan of a group of cells. Figure
3.2 shows an example of a cell template Use transistor fingering for
large and critical transistors. A cell template similar to Figure 3.2 defines the maximum width of a transistor by the cell height. How do we
lay out a transistor that exceeds this height? The solution is to finger
the transistor into multiple transistors that are connected in parallel.
Figure 3.3 shows three equivalent layout designs of a transistor that is
100mm wide.
2. There is an advantage with an even number of fingers: the active capacitance is less, because the drain region is surrounded with gate poly
instead of field. Another reason to use fingering is to optimize the
resistance of the gate poly along the width of the transistor. Since
the gate poly is driven from one end and gate poly is resistive, there
may be reason to have a guideline that states the maximum width of
a single finger. Fingering is the only way to meet this guideline for
large transistors. Fingering multiple transistors that are connected in
series is trickier. Figure 3.4 shows an example of fingering a two-input
NAND gate. Fingering the PMOS devices is straightforward; however,
fingering the series NMOS devices is more difficult because the order
of connectivity of the devices must be maintained.
3. Share power supply nodes to save area. Sharing nodes whenever possible is a concept that is easy to understand. Power supply nodes are
most easily shared because they are very common and easy to connect.
Very significant area savings can be achieved. The main reason that
area is saved is that both sides of a row of contacts are used and there
is no need to space two active regions apart from each other. Figure
3.5 illustrates this technique. Note that power nodes can be shared between transistors of different widths with a slight overhead of inserting
a poly to active space at the end of the smaller transistor.
15

Application
4. Determine minimum number of contacts for source and drain connections. One simple rule might be to fit as many as you can using the
minimum design rule between two contacts. This guideline is most reliable and maximizes the performance of the transistor. The downside
of this approach is that the routability over the transistor is limited. If
increased routability is required and accounted for in the circuit design,
fewer than the maximum number of contacts may be optimal for the
overall layout design. This approach must be considered carefully and
accounted for in the circuit design process.
Figure 3.2: Example Cell Template
Figure 3.3: Fingering Of Transistors
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Application
Figure 3.4: Example Of Fingering A NAND Gate
Figure 3.5: Transistor Power Sharing Example
3.4
Multifinger Transistors
Wide transistors are usually folded so as to reduce both the S/D junction
area and the gate resistance. A simple folded structure such as that in
Fig.3.7 (a) may prove inadequate for very wide devices necessitating the use
of multiple fingers[Fig.3.7 (b)]. As a rule of thumb, the width of each
finger is chosen such that the resistance of the finger is less than the inverse
transconductance associated with the finger .In low-noise applications, the
gate resistance must be one-fifth to one-tenth of .
17

Application
Figure 3.6: Example Of Soft Connections
Figure 3.7: (a)Simple Foldinh Of A MOSFET,(b) Multiple Fingers
3.5
Symmetry
Symmetry must be applied to both the devices of interest and their surrounding environment. Symmetries in fully differential circuits introduce
input referred offsets, thus limiting the minimum signal level that can be detected. While some mismatch is inevitable inadequate attention to symmetry
in the layout may result in large offsets. Symmetry also suppresses the effect of common-mode noise and even-order nonlinearity. Let us consider the
differential pair of Fig.3.8 (a) as the starting point. If, as depicted in Fig.3.9
(b), the two transistors are laid out with different orientations, the matching greatly suffers because many steps in lithography and wafer processing
behave differently along different axes. Thus, one of the configurations in
18

Application
Fig3.10(c) and Fig3.11(d) provides a more better solution.
Figure 3.8: Differential Pair
Figure 3.9: Layout Of MO And M1 With Different Orientation
19

Application
Figure 3.10: Layout With Gate-Aligned Devices
Figure 3.11: Layout With Parallel-Gate Devices
3.6
Resistors
Polysilicon resistors using a silicide block exhibit high linearity, low capacitance to the substrate, and relatively small mismatches. The linearity of
these resistors in fact depends on their length, necessitating accurate measurement and modeling for high-precision applications .
As with other devices, the matching of polysilicon resistors is a function
of their dimensions. For example, resistors having a length of 5um and
width of 3um display typical mismatches on the order of 0.2For large values, resistors are usually decomposed into shorter units that are laid out in
parallel and connected in series[Fig.3.12(a)] From the viewpoint of matching
and repro-ducibility, this structure is preferable to serp-entine Topologies
20

Application
[Fig.3.13(b)] , where the corners contribute significant resistance.
Figure 3.12: Layout Of Lager Resistors
Figure 3.13: Serpentine Topology
21

Application
3.7
Capacitors
Use square geometries for precisely matched capacitors. Peripheral variations are a major source of random mismatch in capacitors. The smaller the
periphery-to-area ratio is, the higher the obtainable degree of matching can
be got. The square has the lowest periphery-to-area ratio of any rectangular
geometry and therefore yields the best matching. Rectangular capacitors
with moderate aspect ratios (2:1 or 3:1) can be used to construct moderately matched capacitors, but precisely matched capacitors should always be
square(as Fig.3.14).Oddly shaped geometries should be avoided because it is
difficult to predict the magnitude of their peripheral variations.
Figure 3.14: Layout Of Capacitor
3.8
Electromigration
Electromigration is defined as the molecular displacement of atoms caused

by the flow of electrons over extended periods of time. What this really
means is that metal lines will eventually break and create an open circuit
by this effect. Poorly designed parts will fail in the field after a period of
flawless operation because of a high degree of susceptibility to electromigration. With decreasing scales of integrated circuits, concern has grown over
the susceptibility of metal lines, operating with high current densities and
elevated temperature, to degradation due to electromigration. Electromigration is most prevalent in aluminum and aluminum-alloy interconnect layers.
22

Application
This is one reason why new metals are being introduced into the manufacturing process that will have no electromigration limitations (i.e., tungsten,
copper, etc.) and very low resistance.
Electromigration failures are avoided simply by increasing the width of currentcarrying metal lines so that an open circuit is avoided. As electromigration
is dependent on the amount of current flowing within a conductor, a set of
guidelines is used to guide layout designers to address this issue effectively
without incurring significant area overhead. There are three basic scenarios
to be considered for the application of electromigration guidelines: (a) DC
current, (b) AC current where the electrons nominally flow in one direction
only, and (c) true AC current (electron flow is bidirectional).
In the ideal scenario, the engineer designing a circuit evaluates electromigration susceptibility for every signal. The schematic is annotated for the layout
designer indicating the signals that require special attention. However, this
method is not very practical, as it is work intensive and is prone to oversights
and omissions. In an attempt to simplify compliance with electromigration
guidelines, most companies prefer to generate a simple table for the layout
designers reference. Before we start using such a table, it is important to
understand what is a unidirectional and a bidirectional current as it pertains
to a circuit design.
This knowledge is necessary to let us implement the layout appropriately
based on reading a schematic. Figure 3.15shows a inverter schematic and
a corresponding layout that are annotated with the flow of current. The
areas of unidirectional and bidirectional currents are also indicated. Please
take the time to understand the direction of the current flow in the PMOS
and NMOS transistors. As we can see, the assumption is that the output
connection will be made to the hashed polygon or to the bolded rectangle on
the right side of the output polygon. Areas that are especially susceptible
to electromigration would be very larger drivers such as output buffers and
clock generators or buffers.
23

Application
Figure 3.15: Simple Examples Of Bent Gates
Figure 3.16: Bent Transistor To Minimize Area
Figure 3.17: Electromigration Currrents

24
Chapter 4
RESULT
4.1
4.1.1
The Layout Design Of LDO Regulator

Design of Low Dropout linear regulator
As is shown in Fig.4.1 is the basic structure of LDO regulator. The feedback

system formed by RF1 and RF2 of which function is sampling the LDO
regulators output voltage and then put the feedback voltage to the input
of error amplifier to compare with the reference voltage. Bandgap voltage
reference provides the reference voltage (Vref) to the error amplifier, and its
accuracy directly affects the precision of LDO regulators output results. The
function of error amplifier is to compare the feedback voltage VFb with the
reference voltage Vref. The output voltage generated by error amplifier adjust
the Power Transistors gate voltage and then change the current flowing
through power transistor for the purpose of stabilizing output voltage.
25

Application
Figure 4.1: Basic Structure Of LDO Regulator
4.1.2
Optimized Layout Design
Error amplifier of proposed LDO formed by differential pairs as shown in

Fig.4.2.M0, M1 MOSFET of differential pairs using multi-finger structure.
Due to the voltage of VF and VREF processed by differential pairs, thus, we
should use symmetry structure. The layout of the differential pair is shown
in Fig.4.3.The optimized layout of differential pairs ensured the accuracy of
input and feedback signal transmission and processing .The resistor layout
of LDO assembled by using three series-wound equal-valued resistors. And
shorter units are laid out in paralle.The shape layout of capacitors we use is
square geometries. The whole layout design of LDO manually uses Cadence
tool,UMC180PDK in 180nm CMOS technology.
26

Application
Figure 4.2: LDO Schematic
27

Application
Figure 4.3: LDO Layout
28
Chapter 5
CONCLUSION AND
FUTUREWORK
5.1
Conclusion
This report presents some optimized layout design methods and optimized
layout of LDO regulator using the Cadence tool,UMC180PDK in 180nm
CMOS technology . It is highly affected by the mismatch that occurs during
the process fabrication between the parameters of an equally group designed.
The mismatch not only affects the DC performance, where it causes nonzero
offset voltage, but also affects high frequencies reducing the PSRR performance. Moreover the interconnect crossovers in the amplifier design can
produce parasitic or undesired capacitance. This problem can be solved with
a careful design and shielding of the amplifier inputs with metal lines connected to the ground. Moreover the design of transistors with translational
symmetry (i.e. each transistor is a copy of the other without rotation), reduces the capacitance.The mismatch of the input transistors of the amplifier
can be reduced with methods commonly used in conventional amplifier design, such as placing these input transistors with commoncentroid method
and designing them in large width.Through the analysis of theses several optimized methods we can know that reasonable and scientific design approach
is necessary and for more complex analog circuits, physical design is also one
of the factors affecting their operating performance.However, the realization
of a good layout requires more work experience of a physical design engineer.
29

Application
5.2
Futurework
the layout can be still be optimized by using newer technology and also
considering other parameters
30
Bibliography
[1] Peng Xiao-hong, Lv Ben-qiang, Li Xiao-qing, Zhu Zhi-ding, Dong Limin.The Layout Design and Optimization of A Low Dropout Regulator2011 International Conference on Computer Science and Information Technology (ICCSIT 2011)
[2] Seong K. Hong [ I ] and Phillip E. Allen [21a. ANALOG CIRCUIT
LAYOUT WITH OPTIMIZED PERFORMANCE
[3] Alan Hastings. The Art of Analog Layout (Sencond Edition), 2007.
[4] Behzad Razavi, . Design of Analog CMOS Integreated Circuits, 2001.
[5] Dan Clein.CMOS IC LAYOUT Concepts, Methodologies, and Tools

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VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Jnana Sangama, Belgaum - 580 014

VLSI DESIGN AND TESTING

Prof. Sujata Kotabagi

Prof. Sujata Kotabagi

Dr. Uma Mudenagudi

Dr. Ashok Shettar

Signature with date

In this paper we present a design of a cmos amplifier with the buffer

The sense of contentment and elation that accompanies the successful

3 GENERAL GUIDELINES FOR LAYOUT

5 CONCLUSION AND FUTUREWORK

Example Of Cross-Section Process Steps . . . .

Routing Line Width Considerations And Routing Direction

Basic Structure Of LDO Regulator . . . . . . . . . . . . . . . 26

An approach for developing a component-level use of a layout compiler

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

layout optimization of low drop-out,high PSRR LDO for RF application.

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Figure 1.1: Methodology

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Understanding The Schematic Connectivity

Layers And Connectivity

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

This isolation is required in both the vertical and horizontal direction

Figure 2.1: Example Of Cross-Section Process Steps

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Figure 2.2: PMOS and NMOS Transistors

Figure 2.3: Simple PMOS Transistor Layout

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Figure 2.4: Simple NMOS Transistor Layout

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Figure 2.5: Wafer Cross-Section Showing Bulk Connections

Process Design Rules

vertical Connnection Diagram

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Figure 2.6: Vertical Diagram Of Connectivity For A DRAM Process

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Guidelines For The Layout Of Power Lines

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

automated tools, it is not advisable to run power supply lines over

Guidelines For The Layout Of Signals

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Figure 3.1: Routing Line Width Considerations And Routing Direction

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Guidelines For The Layout Of The Transistors

The following is a list of guidelines specifically for a cell-level design environment.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Figure 3.2: Example Cell Template

Figure 3.3: Fingering Of Transistors

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF

Figure 3.4: Example Of Fingering A NAND Gate

Figure 3.5: Transistor Power Sharing Example

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31.

Layout Optimization Of Low Drop-Out,High PSRR LDO For RF