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Library of Congress Cataloging-in-Publication Data
The VLSI handbook / edited by Wai-Kai Chen.

p. cm.
Includes bibliographical references and index.
ISBN 0-8493-8593-8 (alk. paper)
1. Integrated circuits--Very large scale integration.
I. Chen,Wai-Kai, 1936
TK7874.75.V573 1999
621.395dc21
99-047682
CIP
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Preface
Purpose
The purpose of The VLSI Handbook is to provide in a single volume a comprehensive reference work
covering the broad spectrum of VLSI technology. It is written and developed for the practicing electrical
and computer engineers in industry, government, and academia. The goal is to provide the most upto-date information in IC technology, devices and their models, circuit simulations, amplifiers, logic
design, memory, registers and system timing, microprocessor and ASIC, test and testability, design
automation, and design languages. The handbook is not an all-encompassing digest of everything taught
within an electrical and computer engineering curriculum on VLSI technology. Rather, it is the engineer's
first choice in looking for a solution. Therefore, full references to other sources of contributions are
provided. The ideal reader is a B.S.-level engineer with a need for a one-source reference to keep abreast
of new techniques and procedures as well as review standard practices.
Background
The handbook stresses fundamental theory behind professional applications. In order to do so, it is
reinforced with frequent examples. Extensive development of theory and details of proofs have been
omitted. The reader is assumed to have a certain degree of sophistication and experience. However, brief
reviews of theories, principles and mathematics of some subject areas are given. These reviews have been
done concisely with perception. The handbook is not a textbook replacement, but rather a reinforcement
and reminder of material learned as a student. Therefore, important advancement and traditional as well
as innovative practices are included.
Since the majority of professional electrical engineers graduated before powerful personal computers
were widely available, many computational and design methods may be new to them. Therefore,
computers and software use are thoroughly covered. Not only does the handbook use traditional references to cite sources for the contributions, it also contains all relevant sources of information and tools
that would assist the engineer in performing his/her job. This may include sources of software, databases,
standards, seminars, conferences, etc.
Organization
Over the years, the fundamentals of VLSI technology have evolved to include a wide range of topics and
a broad range of practice. To encompass such a wide range of knowledge, the handbook focuses on the
key concepts, models, and equations that enable the electrical or computer engineer to analyze, design
and predict the behavior of very large-scale integrated circuits. While design formulas and tables are
listed, emphasis is placed on the key concepts and theories underlying the applications.
The information is organized into 13 major sections, which encompass the field of VLSI technology.
Each section is divided into chapters, each of which was written by a leading expert in the field to enlighten
and refresh knowledge of the mature engineer, and to educate the novice. Each chapter contains introductory material, leading to the appropriate applications, and references. The references provide a list of
useful books and articles for following reading.
Locating Your Topic

Numerous avenues of access to information contained in the handbook are provided. A complete table
of contents is presented at the front of the book. In addition, an individual table of contents precedes
each of the thirteen sections. Finally, each chapter begins with its own table of contents. The reader is
urged to look over these tables of contents to become familiar with the structure, organization, and
content of the book. For example, see Section VIII: Microprocessor and ASIC, then Chapter 61: Microprocessor Design Verification, and then Section 61.8: Emulation. This tree-like structure enables the
reader to move up the tree to locate information on the topic of interest.
A combined subject and author index has been compiled to provide means of accessing information.
It can also be used to locate definitions; the page on which the definition appears for each key defining
term is given in this index.
The VLSI Handbook is designed to provide answers to most inquiries and direct inquirers to further
sources and references. We trust that it will meet your needs.
Acknowledgments
The compilation of this book would not have been possible without the dedication and efforts of the
Editorial Board of Advisors, the section editors, the publishers, and most of all the contributing authors.
I wish to thank them all and also my wife, Shiao-Ling, for her patience and understanding.
Wai-Kai Chen
Editor-in-Chief
Editor-in-Chief
Wai-Kai Chen, Professor and Head of the Department of Electrical

Engineering and Computer Science at the University of Illinois at
Chicago, teaches graduate and undergraduate courses in electrical
engineering in the fields of circuits and systems. He received his B.S.
and M.S. in electrical engineering at Ohio University where he was
later recognized as a Distinguished Professor. He earned his Ph.D.
in electrical engineering at the University of Illinois at UrbanaChampaign.
Professor Chen has extensive experience in education and industry
and is very active professionally in the fields of circuits and systems.
He has served as a visiting professor at Purdue University and the
University of Hawaii at Manoa. He was Editor of the IEEE Transactions on Circuits and Systems, both Series I and II and President of
the IEEE Circuits and Systems Society. Currently, he is Editor-inChief of the Journal of Circuits, Systems and Computers and Editor
of the Advanced Series in Electrical and Computer Engineering, Imperial College Press. He received the
Lester R. Ford Award from the Mathematical Association of America, the Alexander von Humboldt Award
from Germany, the Ohio University Alumni Medal of Merit for Distinguished Achievement in Engineering
Education, the Senior University Scholar Award from University of Illinois at Chicago, the Distinguished
Alumnus Award from the University Illinois at Urbana-Champaign, and the Society Meritorious Service
Award and the Education Award from IEEE Circuits and Systems Society. He also received more than a
dozen honorary professor awards from major institutions in China.
A Fellow of the Institute of Electrical and Electronics Engineers and the American Association for the
Advancement of Science, Professor Chen is widely known in the profession for his Applied Graph Theory
(North-Holland), Theory and Design of Broadband Matching Networks (Pergamon Press), Active Network
and Feedback Amplifier Theory (McGraw-Hill), Linear Networks and Systems (Brooks/Cole), Passive and
Active Filters: Theory and Implementations (John Wiley), Theory of Nets (John Wiley), and The Circuits
and Filters Handbook (Editor-in-Chief, CRC Press).
Advisory Board
Professor Steve M. Kang

Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Urbana, Illinois
Professor Saburo Muroga

Computer Science Department
University of Illinois at Urbana-Champaign
Urbana, Illinois
Dr. Bing J. Sheu

Avant! Corporation
Fremont, California
Contributors
Ramachandra Achar
Victor Boyadzhyan
Daniel A. Connors
Carleton University
Ottawa, Ontario, Canada
Jet Propulsion Laboratory

Pasadena, California
University of Illinois
Urbana, Illinois
James H. Aylor
Charles E. Chang
Donald Cottrell
University of Virginia
Charlottesville, Virginia
Conexant Systems, Inc.

Newbury Park, California
Silicon Integration Initiative,

Inc. (Si2, Inc.)
Austin, Texas
R. Jakob Baker
Wai-Kai Chen
University of Idaho
Boise, Idaho
Chicago, Illinois
David L. Barton
Kuo-Hsing Cheng
Intermetrics, Inc.
Vienna, Virginia
Andrea Baschirotto
Universit di Pavia
Pavia, Italy
Charles R. Baugh
C. R. Baugh and Associates
Bellevue, Washington
J. Bhasker
Cadence Design Systems
Allentown, Pennsylvania
David Blaauw
Motorola, Inc.
Austin, Texas
Marc Borremans
Katholieke Universiteit Leuven
Leuven-Heverlee, Belgium
Tamkang University
Tamsui, Taipei Hsien, Taiwan
John Choma, Jr.

University of Southern
California
Los Angeles, California
John D. Cressler
Auburn University
Auburn, Alabama
Sorin Cristoloveanu
Institut National Polytechnique
de Grenoble
Grenoble, France
Bram De Muer
Katholieke Universiteit Leaven
Amy Hsiu-Fen Chou

National Tsing-Hua University
Hsin-Chu, Taiwan
Geert A. De Veirman
Silicon Systems, Inc.
Tustin, California
Moon Jung Chung

Michigan State University
East Lansing, Michigan
Maria del Mar

Hershenson
David J. Comer
Stanford University
Stanford, California
Brigham Young University

Provo, Utah
Allen M. Dewey
Donald T. Comer
Duke University
Durham, North Carolina
Brigham Young University

Provo, Utah
Abhijit Dharchoudhury
Peter J. Hesketh
Dimitri Kagaris
Motorola, Inc.
Austin, Texas
The Georgia Institute

of Technology
Atlanta, Georgia
Southern Illinois University

Carbondale, Illinois
Karl Hess
Urbana, Illinois
Steve M. Kang
Donald B. Estreich
Hewlett-Parkard Company
Santa Rosa, California
Urbana, Illinois
Nick Kanopoulos
John W. Fattaruso
Texas Instruments,
Incorporated
Dallas, Texas
Charles Ching-Hsiang
Hsu
Hsinchu, Taiwan
Tanay Karnik
Eby G. Friedman
University of Rochester
Rochester, New York
Jen-Sheng Hwang
National Science Council
Hsinchu, Taiwan
Stantanu Ganguly
Intel Corp.
Austin, Texas
Yosef Gavriel
Virginia Polytechnic Institute
and State University
Blacksburg, Virginia
Intel Corporation
Hillsboro, Oregon
Yasuhiro Katsumata
Thad Gabara
Lucent Technologies
Murray Hill, New Jersey
Atmel, Multimedia and

Communications
Morrisville, North Carolina
Wen-mei Hwu
Urbana, Illinois
Toshiba Corporation
Isogo-ku, Yokohama, Japan
Pankaj Khandelwal
Kazumi Inoh
Toshiba Corporation
Chicago, Illinois
John M. Khoury
Hidemi Ishiuchi
Toshiba Corporation
Lucent Technologies
Heechul Kim
Royal Institute of Technology

Kista-Stockholm, Sweden
The Ohio State University

Columbus, Ohio
Hankuk University of Foreign

Studies
Yongin, Kyung Ki-Do, Korea
Rajesh K. Gupta
Hiroshi Iwai
Hideki Kimijima
Jan V. Grahn
University of California
Irvine, California
Sumit Gupta
Irvine, California
Mohammed Ismail
Toshiba Corporation
Toshiba Corporation
Vikram Iyengar
Isik C. Kizilyalli
Urbana, Illinois
Johan Janssens
Lucent Bell Laboratories

Orlando, Florida
Robert H. Klenke
Martin Margala
Michel S. Nakhla
Virginia Commonwealth
University
Richmond, Virginia
University of Alberta
Edmonton, Alberta, Canada
Carleton University
Ottawa, Ontario, Canada
Samuel S. Martin
Zainalabedin Navabi
Ivan S. Kourtev
Lucent Technologies
Northeastern University
Boston, Massachusetts
Erik A. McShane
Philip G. Neudeck
Chicago, Illinois
NASA Glenn Research Center

Cleveland, Ohio
Shin-ichi Minato
Kwok Ng
University of Idaho
Moscow, Idaho
NTT Network Innovation

Laboratories
Yokosuka-shi, Japan
Lucent Technologies
Chi-Hung Lin
Sunderarajan S. Mohan
University of Pittsburgh
Pittsburgh, Pennsylvania
Thomas H. Lee
Stanford University
Harry W. Li
The Ohio State University

Columbus, Ohio
Frank Ruei-Ling Lin

Hsin-Chu, Taiwan
John W. Lockwood
Washington University
St. Louis, Missouri
Stephen I. Long
Santa Barbara, California
Flavio Lorenzelli
ST Microelectronics, Inc.
San Diego, California
Ashraf Lotfi
Lucent Technologies
Joseph W. Lyding
Urbana, Illinois
Hideaki Nii
Stanford University
Toshiba Corporation
Tatsuya Ohguro
Hisayo S. Momose
Toshiba Corporation
Toshiba Corporation
Mikael stling
Eiji Morifuji
Toshiba Corporation
Royal Institute of Technology

Kista-Stockholm, Sweden
Alice C. Parker
Toyota Morimoto
Toshiba Corporation
California
Saburo Muroga
Alison Payne
Urbana, Illinois
Imperial College
University of London
London, England
Akio Nakagawa
Toshiba Corporation
Saiwai-ku, Kawasaki, Japan
Yuichi Nakamura
NEC Corporation
Miyamae-ku, Kawasaki, Japan
Massoud Pedram
California
J. Gregory Rollins
Naofumi Takagi
Wayne Wolf
Antrim Design Systems

Scotts Valley, California
Nagoya University
Nagoya, Japan
Princeton University
Princeton, New Jersey
Elizabeth M. Rudnick
Donald C. Thelen
Chung-Yu Wu
Urbana, Illinois
Analog Interfaces
Bozeman, Montana
National Chiao Tung University

Hsinchu, Taiwan
Kirad Samavati
Chris Toumazou
Evans Ching-Song Yang
Stanford University
Imperial College
University of London
London, England

Hsinchu, Taiwan
Rolf Schaumann
Portland State University
Portland, Oregon
Rick Shih-Jye Shen

Hsinchu, Taiwan
Spyros Tragoudas
Southern Illinois University
Carbondale, Illinois
Yuh-Kuang Tseng
Krishna Shenai
Industrial Research and

Technology Institute
Chutung, Hsinchu, Taiwan
Chicago, Illinois
Meera Venkataraman
Bing J. Sheu
Troika Networks, Inc.

Calabasas Hills, California
Avant! Corporation
Suhrid A. Wadekar
Bang-Sup Song
IBM Corp.
Hopewell Junction, New York
La Jolla, California
Chorng-kuang Wang
Michiel Steyaert
National Taiwan University

Taipei, Taiwan

R. F. Wassenaar
Haruyuki Tago
University of Twente
Enschede, The Netherlands
Toshiba Semiconductor
Company
Saiwai-ku, Kawasaki-shi, Japan
Louis A. Williams III

Texas Instruments,
Incorporated
Dallas, Texas
Kazuo Yano
Hitachi Ltd.
Kokubunji, Tokyo, Japan
Kung Yao
Ko Yoshikawa
NEC Corporation
Fuchu, Tokyo, Japan
Kuniyoshi Yoshikawa
Toshiba Corporation
Takashi Yoshitomi
Toshiba Corporation
Min-shueh Yuan
National Taiwan University
Taipei, Taiwan
C. Patrick Yue
Stanford University
Contents
SECTION I
VLSI Technology: A System Perspective

Erik A. McShane
1.1
1.2
1.3
1.4
Introduction
Contemporary VLSI Systems
Emerging VLSI Systems
Alternative Technologies
Introduction
CMOS Technology
BiCMOS Technology
Future Technology
Summary
Bipolar Technology
3.1
3.2
3.3
3.4
3.5
Krishna Shenai and
CMOS/BiCMOS Technology Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi

Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota
Morimoto, Hisayo S. Momose, Kuniyoshi Yoshikawa, Hidemi Ishiuchi, and
Hiroshi Iwai
2.1
2.2
2.3
2.4
2.5
VLSI Technology
Jan V. Grahn and Mikael stling
Introduction
Bipolar Process Design
Conventional Bipolar Technology
High-Performance Bipolar Technology
Advanced Bipolar Technology
Silicon on Insulator Technology

4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Introduction
Fabrication of SOI Wafers
Generic Advantages of SOI
SOI Devices
FullyDepleted SOI Transistors
Partially Depleted SOI Transistors
ShortChannel Effects
SOI Challenges
Conclusion
Sorin Cristoloveanu
SiGe Technology
5.1
5.2
5.3
5.4
5.5
SiC Technology
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Akio Nakagawa
Introduction
Intelligent Power ICs
High-Voltage Technology
High-Voltage Metal Interconnection
High-Voltage SOI Technology
High-Voltage Output Devices
Sense and Protection Circuit
Examples of High-Voltage SOI Power ICs with LIGBT Outputs
SOI Power ICs for System Integration
High-Temperature Operation of SOI Power ICs
Noise in VLSI Technologies

and Kwok Ng
9.1
9.2
9.3
9.4
9.5
9.6
10
Ashraf Lotfi
Magnetic Components
Air Core Inductors
Resistors
Capacitors
Power IC Technologies
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Philip G. Neudeck
Introduction
Fundamental SiC Material Properties
Applications and Benefits of SiC Electronics
SiC Semiconductor Crystal Growth
SiC Device Fundamentals
SiC Electronic Devices and Circuits
Further Recommended Reading
Passive Components
7.1
7.2
7.3
7.4
John D. Cressler
Introduction
SiGe Strained Layer Epitaxy
The SiGe Heterojunction Bipolar Transistor (HBT)
The SiGe Heterojunction Field Effect Transistor (HFET)
Future Directions
Samuel S. Martin, Thad Gabara,
Introduction
Microscopic Noise
Device Noise
Chip Noise
Future Trends
Conclusions
Micromachining
Peter J. Hesketh
10.1 Introduction
10.2 Micromachining Processes
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
11
Microelectronics Packaging
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
12
Pankaj Khandelwal and Krishna Shenai
Introduction
Packaging Hierarchy
Package Parameters
Packaging Substrates
Package Types
Hermetic Packages
Die Attachment Techniques
Package Parasitics
Package Modeling
Packaging in Wireless Applications
Future Trends
Multichip Module Technologies

12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
12.12
13
Bulk Micromachining of Silicon

Surface Micromachining
Advanced Processing
CMOS and MEMS Fabrication Process Integration
Wafer Bonding
Optical MEMS
Actuators for MEMS Optics
Electronics
Chemical Sensors
Victor Boyadzhyan and John Choma, Jr.
Introduction
Multi-Chip Module Technologies
Materials for HTCC Aluminum Packages
LTCC Substrates
Aluminum Nitride
Materials for Multi-layered AlN Packages
Thin Film Dielectrics
Carrier Substrates
Conductor Metallization
Choosing Substrate Technologies and Assembly Techniques
Assembly Techniques
Summary
Channel Hot Electron Degradation-Delay in MOS Transistors Due

to Deuterium Anneal Isik C. Kizilyalli, Karl Hess, and Joseph W. Lyding
13.1
13.2
13.3
13.4
13.5
Introduction
Post-Metal Forming Gas Anneals in Integrated Circuits
Impact of Hot Electron Effects on CMOS Development
The Hydrogen/Deuterium Isotope Effect and CMOS Manufacturing
Summary
SECTION II
14
Bipolar Junction Transistor (BJT) Circuits

and Donald T. Comer
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
15
Introduction
Physical Characteristics and Properties of the BJT
Basic Operation of the BJT
Use of the BJT as an Amplifier
Representing the Major BJT Effects by an Electronic Model
Other Physical Effects in the BJT
More Accurate BJT Models
Heterojunction Bipolar Junction Transistors
Integrated Circuit Biasing Using Current Mirrors
The Basic BJT Switch
High-Speed BJT Switching
Simple Logic Gates
Emitter-Coupled Logic
Introduction
Fractal Capacitors
Spiral Inductors
On-Chip Transformers
SECTION III
Circuit Simulations
Analog Circuit Simulation

16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
17
David J. Comer
RF Passive IC Components Thomas H. Lee, Maria del Mar Hershenson,

Sunderarajan S. Mohan, Kirad Samavati, and C. Patrick Yue
15.1
15.2
15.3
15.4
16
Devices and Their Models
J. Gregory Rollins
Introduction
Purpose of Simulation
Netlists
Formulation of the Circuit Equations
Modified Nodal Analysis
Active Device Models
Types of Analysis
Verilog-A
Fast Simulation Methods
Commercially Available Simulators
Interconnect Modeling and Simulation

and Ramachandra Achar
17.1 Introduction
17.2 Interconnect Models
Michel S. Nakhla
17.3 Distributed Transmission Line Equations

17.4 Interconnect Simulation Issues
17.5 Interconnect Simulation Techniques
18
Power Simulation and Estimation in VLSI Circuits

18.1
18.2
18.3
18.4
18.5
18.6
18.7
SECTION IV
19
Massoud Pedram
Introduction .
Software-Level Power Estimation
Behavioral-Level Power Estimation
RT-Level Power Estimation
Gate-Level Power Estimation
Transistor-Level Power Estimation
Conclusion
Amplifiers
CMOS Amplifier Design

Donald C. Thelen
Harry W. Li, R. Jakob Baker, and
19.1 Introduction
19.2 Biasing Circuits
19.3 Amplifiers
20
Bipolar Amplifier Design

20.1
20.2
20.3
20.4
20.5
20.6
20.7
21
High-Frequency Amplifiers
21.1
21.2
21.3
21.4
21.5
21.6
21.7
22
Geert A. De Veirman
Introduction
Single-Transistor Amplifiers
Differential Amplifiers
Output Stages
Bias Reference
Operational Amplifiers
Conclusion
Chris Toumazou and Alison Payne
Introduction
The Current Feedback Op-Amp
RF Low-Noise Amplifiers
Optical Low-Noise Preamplifiers
Fundamentals of RF Power Amplifier Design
Applications of High-Q Resonators in IF-Sampling Receiver Architectures
Log-Domain Processing
Operational Transconductance Amplifiers

Mohammed Ismail, and Chi-Hung Lin
22.1 Introduction
22.2 Noise Behavior of the OTA
R. F. Wassenaar,
22.3
22.4
22.5
22.6
An OTA with an Improved Output Swing

OTAs with High Drive Capability
Common-Mode Feedback
Filter Applications with Low-Voltage OTAs
SECTION V Logic Design
23
Expressions of Logic Functions

23.1
23.2
23.3
23.4
24
Saburo Muroga
Introduction to Basic Logic Operations

Truth Tables
Karnaugh Maps
Binary Decision Diagrams
Basic Theory of Logic Functions
Saburo Muroga
24.1 Basic Theorems

24.2 Implication Relations and Prime Implicants
25
Simplification of Logic Expressions

25.1
25.2
25.3
25.4
25.5
26
Binary Decision Diagrams

26.1
26.2
26.3
26.4
26.5
27
Saburo Muroga
Minimal Sums
Derivation of Minimal Sums by Karnaugh Map
Derivation of Minimal Sums for a Single Function by Other Means
Prime Implicates, Irredundant Conjunctive Forms, and Minimal Products
Derivation of Minimal Products by Karnaugh Map
Shin-ichi Minato and Saburo Muroga
Basic Concepts
Construction of BDD Based on a Logic Expression
Data Structure
Ordering of Variable for Compact BDDs
Remarks
Logic Synthesis with AND and OR Gates in Two Levels

Saburo Muroga
27.1 Introduction
27.2 Design of Single-Output Minimal Networks with AND
and OR Gates in Two Levels
27.3 Design of Multiple-Output Networks with AND and OR Gates in Two Levels
28
Sequential Networks with AND and OR Gates

28.1
28.2
28.3
28.4
28.5
Saburo Muroga
Introduction
Flip-Flops and Latches
Sequential Networks in Fundamental Mode
Malfunctions of Asynchronous Sequential Networks
Different Tables for the Description of Transitions of Sequential Networks
28.6 Steps for the Synthesis of Sequential Networks

28.7 Synthesis of Sequential Networks
29
Logic Synthesis with AND and OR Gates in Multi-levels

Yuichi Nakamura and Saburo Muroga
29.1
29.2
29.3
29.4
30
Logic Networks with AND and OR Gates in Multi-levels

General Division
Selection of Divisors
Limitation of Weak Division
Logic Properties of Transistor Circuits
Saburo Muroga
30.1 Basic Properties of Connecting Relays.

30.2 Analysis of Relay-Contact Networks
30.3 Transistor Circuits
31
Logic Synthesis with NAND (or NOR) Gates in Multi-levels

Saburo Muroga
31.1 Logic Synthesis with NAND (or NOR) Gates
31.2 Design of NAND (or NOR) Networks in Double-Rail Input Logic
by the Map-Factoring Method
31.3 Design of NAND (or NOR) Networks in Single-Rail Input Logic
31.4 Features of the Map-Factoring Method
31.5 Other Design Methods of Multi-level Networks
with a Minimum Number of Gates
32
Logic Synthesis with a Minimum Number of Negative Gates

Saburo Muroga
32.1 Logic Design of MOS Networks
32.2 Algorithm DIMN
33
Logic Synthesizer with Optimizations in Two Phases

and Saburo Muroga
34
Logic Synthesizer by the Transduction Method

34.1
34.2
34.3
34.4
35
Saburo Muroga
Technology-Dependent Logic Optimization

Transduction Method for the Design of NOR Logic Networks
Various Transduction Methods
Design of Logic Networks with Negative Gates by the Transduction Method
Emitter-Coupled Logic
35.1
35.2
35.3
35.4
Ko Yoshikawa
Saburo Muroga
Introduction
Standard ECL Logic Gates
Modification of Standard ECL Logic Gates with Wired Logic
ECL Series-Gating Circuits
36
CMOS
36.1
36.2
36.3
36.4
36.5
36.6
37
Saburo Muroga
CMOS (Complementary MOS)

Logic Design of CMOS Networks
Logic Design in Differential CMOS Logic
Layout of CMOS
Pseudo-nMOS
Dynamic CMOS
Pass Transistors
Kazuo Yano and Saburo Muroga
37.1 Introduction
37.2 Electronic Problems of Pass Transistors
37.3 Top-down Design of Logic Functions with Pass-Transistor Logic
38
Adders Naofumi Takagi, Haruyuki Tago, Charles R. Baugh,

and Saburo Muroga
38.1
38.2
38.3
38.4
38.5
38.6
38.7
38.8
39
Multipliers
39.1
39.2
39.3
39.4
39.5
40
Naofumi Takagi, Charles R. Baugh, and Saburo Muroga
Introduction
Sequential Multiplier
Array Multiplier
Multiplier Based on Wallace Tree
Multiplier Based on a Redundant Binary Adder Tree
Dividers
40.1
40.2
40.3
40.4
40.5
41
Introduction
Addition in the Binary Number System
Serial Adder
Ripple Carry Adder
Carry Skip Adder
Carry Look-Ahead Adder
Carry Select Adder
Carry Save Adder
Naofumi Takagi and Saburo Muroga
Introduction
Subtract-And-Shift Dividers
Higher Radix Subtract-And-Shift Dividers
Even Higher Radix Dividers with a Multiplier
Multiplicative Dividers
Full-Custom and Semi-Custom Design
Saburo Muroga
41.1 Introduction
41.2 Full-Custom Design Sequence of a Digital System
42
Programmable Logic Devices

42.1 Introduction
42.2 PLAs and Variations
Saburo Muroga
42.3
42.4
42.5
42.6
43
Logic Design with PLAs

Dynamic PLA
Advantages and Disadvantages of PLAs
Programmable Array Logic
Gate Arrays
Saburo Muroga
43.1 Mask-Programmable Gate Arrays

43.2 CMOS Gate Arrays
43.3 Advantages and Disadvantages of Gate Arrays
44
Field-Programmable Gate Arrays

44.1
44.2
44.3
44.4
45
Saburo Muroga
Introduction
Basic Structures of FPGAs
Various Field-Programmable Gate Arrays
Features of FPGAs
Cell-Library Design Approach
Saburo Muroga
45.1 Introduction
45.2 Polycell Design Approach
45.3 Hierarchical Design Approach
46
Comparison of Different Design Approaches

46.1
46.2
46.3
46.4
SECTION VI
47
48
Memory, Registers, and System Timing
System Timing
47.1
47.2
47.3
47.4
47.5
Ivan S. Kourtev and Eby G. Friedman
Introduction
Synchronous VLSI Systems
Synchronous Timing and Clock Distribution Networks
Timing Properties of Synchronous Storage Elements
A Final Note
Appendix
ROM/PROM/EPROM
Jen-Sheng Hwang
48.1 Introduction
48.2 ROM
48.3 PROM
49
Saburo Muroga
Introduction
Design Approaches with Off-the-Shelf Packages
Full-and Semi-Custom Design Approaches
Comparison of All Different Design Approaches
SRAM
Yuh-Kuang Tseng
49.1 Read/Write Operation
49.2 Address Transition Detection (ATD) Circuit for

Synchronous Internal Operation
49.3 Decoder and Word-Line Decoding Circuit
49.4 Sense Amplifier
49.5 Output Circuit
50
Embedded Memory
50.1
50.2
50.3
50.4
50.5
50.6
51
Flash Memories Rick Shih-Jye Shen, Frank Ruei-Ling Lin, Amy Hsiu-Fen
Chou, Evans Ching-Song Yang, and Charles Ching-Hsiang Hsu
51.1
51.2
51.3
51.4
51.5
51.6
51.7
51.8
52
Introduction
Review of Stacked-Gate Non-volatile Memory
Basic Flash Memory Device Structures
Device Operation
Variations of Device Structure
Flash Memory Array Structures
Evolution of Flash Memory Technology
Flash Memory System
Dynamic Random Access Memory

52.1
52.2
52.3
52.4
52.5
52.6
52.7
52.8
52.9
53
Chung-Yu Wu
Introduction
Merits and Challenges
Technology Integration and Applications3,5
Design Methodology and Design Space3,5
Testing and Yield3,5
Design Examples
Low-Power Memory Circuits

53.1
53.2
53.3
53.4
53.5
53.6
53.7
Kuo-Hsing Cheng
Introduction
Basic DRAM Architecture
DRAM Memory Cell
Read/Write Circuit
Synchronous (Clocked) DRAMs
Prefetch and Pipelined Architecture in SDRAMs
Gb SDRAM Bank Architecture
Multi-level DRAM
Concept of 2-bit DRAM Cell
Martin Margala
Introduction
Read-Only Memory (ROM)
Flash Memory
Ferroelectric Memory (FeRAM)
Static Random-Access Memory (SRAM)
Dynamic Random-Access Memory (DRAM)
Conclusion
SECTION VII
54
Nyquist-Rate ADC and DAC

54.1
54.2
55.3
54.4
54.5
54.6
54.7
55
Introduction
Technology
The Receiver
The Synthesizer
The Transmitter
Towards Fully Integrated Transceivers
Conclusions
PLL Circuits
57.1
57.2
57.3
57.4
58
Introduction
Basic Theory of Operation
Alternative Sigma-Delta Architectures
Filtering for Sigma-Delta Modulators
Circuit Building Blocks
Practical Design Issues
Summary
RF Communication Circuits Michiel Steyaert, Marc Borremans,

Johan Janssens, and Bram De Muer
56.1
56.2
56.3
56.4
56.5
56.6
56.7
57
Bang-Sup Song
Introduction
ADC Design Arts
ADC Architectures
ADC Design Considerations
DAC Design Arts
DAC Architectures
DAC Design Considerations
Oversampled Analog-to-Digital and Digital-to-Analog Converters

John W. Fattaruso and Louis A. Williams III
55.1
55.2
55.3
55.4
55.5
55.6
55.7
56
Analog Circuits
Min-shueh Yuan and Chorng-Kuang Wang
Introduction
PLL Techniques
Building Blocks of the PLL Circuit
PLL Applications
Continuous-Time Filters
58.1
58.2
58.3
58.4
58.5
John M. Khoury
Introduction
State-Variable Synthesis Techniques
Realization of VLSI Integrators
Filter Tuning Circuits
Conclusion
59
Switched-Capacitor Filters
59.1
59.2
59.3
59.4
59.5
59.6
59.7
59.8
59.9
SECTION VIII
60
63
Tanay Karnik
Introduction
Layout Problem Description
Manufacturing
Chip Planning
Architecture
63.1
63.2
63.3
63.4
Vikram Iyengar
Introduction
Design Verification Environment
Random and Biased-Random Instruction Generation
Correctness Checking
Coverage Metrics
Smart Simulation
Wide Simulation
Emulation
Conclusion
Microprocessor Layout Method

62.1
62.2
62.3
62.4
Abhijit Dharchoudhury,
Introduction
Static Timing Analysis
Noise Analysis
Power Grid Analysis
Microprocessor Design Verification

and Elizabeth M. Rudnick
61.1
61.2
61.3
61.4
61.5
61.6
61.7
61.8
61.9
62
Microprocessor and ASIC
Timing and Signal Integrity Analysis

David Blaauw, and Stantanu Ganguly
60.1
60.2
60.3
60.4
61
Andrea Baschirotto
Introduction
Sampled-Data Analog Filters
The Principle of SC Technique
First-Order SC Stages
Second-Order SC Circuit
Implementation Aspects
Performance Limitations
Compensation Technique (Performance Improvements)
Advanced SC Filter Solutions
Daniel A. Connors and Wen-mei Hwu
Introduction
Types of Microprocessors
Major Components of a Microprocessor
Instruction Set Architecture
63.5 Instruction Level Parallelism

63.6 Industry Trends
64
ASIC Design
64.1
64.2
64.3
64.4
64.5
64.6
64.7
64.8
64.9
64.10
64.11
64.12
64.13
64.14
64.15
64.16
65
Logic Synthesis for Field Programmable Gate Array (FPGA) Technology

John Lockwood
65.1
65.2
65.3
65.4
65.5
65.6
65.7
Introduction
FPGA Structures
Logic Synthesis
Look-up Table (LUT) Synthesis
Chortle
Two-Step Approaches
Conclusion
SECTION IX
66
Sumit Gupta and Rajesh K. Gupta
Introduction
Design Styles
Steps in the Design Flow
Hierarchical Design
Design Representation and Abstraction Levels
System Specification
Specification Simulation and Verification
Architectural Design
Logic Synthesis
Physical Design
I/O Architecture and Pad Design
Tests After Manufacturing
High-Performance ASIC Design
Low Power Issues
Reuse of Semiconductor Blocks
Conclusion
Test and Testability
Testability Concepts and DFT
Nick Kanopoulos
66.1 Introduction: Basic Concepts

66.2 Design for Testability
67
ATPG and BIST
Dimitri Kagaris
67.1 Automatic Test Pattern Generation

67.2 Built-In Self-Test
68
CAD Tools for BIST/DFT and Delay Faults

68.1 Introduction
68.2 CAD for Stuck-at Faults
68.3 CAD for Path Delays
Spyros Tragoudas
SECTION X Compound Semiconductor Digital Integrated

Circuit Technology
69
Materials
69.1
69.2
69.3
69.4
70
Compound Semiconductor Devices for Digital Circuits

Donald B. Estreich
70.1
70.2
70.3
70.4
71
Stephen I. Long
Introduction
Compound Semiconductor Materials
Why III-V Semiconductors?
Heterojunctions
Introduction
Unifying Principle for Active Devices: Charge Control Principle
Comparing Unipolar and Bipolar Transistors
Typical Device Structures
Logic Design Principles and Examples
Stephen I. Long
71.1 Introduction
71.2 Static Logic Design
71.3 Transient Analysis and Design for Very-High-Speed Logic
72
Logic Design Examples

and Stephen I. Long
Charles E. Chang, Meera Venkataraman,
72.1 Design of MESFET and HEMT Logic Circuits

72.2 HBT Logic Design Examples
SECTION XI
73
Internet Based Micro-Electronic Design Automation (IMEDA) Framework

Moon Jung Chung and Heechul Kim
73.1
73.2
73.3
73.4
73.5
73.6
73.7
74
Design Automation
Introduction
Functional Requirements of Framework
IMEDA System
Formal Representation of Design Process
Execution Environment of the Framework
Implementation
Conclusion
System-Level Design Alice C. Parker, Yosef Tirat-Gefen,

and Suhrid A. Wadekar
74.1
74.2
74.3
74.4
74.5
Introduction
System Specification
System Partitioning
Scheduling and Allocating Tasks to Processing Modules
Allocating and Scheduling Storage Modules
74.6
74.7
74.8
74.9
74.10
75
Synthesis at the Register Transfer Level and the Behavioral Level

J. Bhasker
75.1
75.2
75.3
75.4
75.5
75.6
75.7
75.8
76
Introduction
The ADEPT Design Environment
A Simple Example of an ADEPT Performance Model
Mixed-Level Modeling
Conclusions
Introduction
Uses of Microprocessors
Embedded System Architectures
Hardware/Software Co-Design
Design Automation Technology Roadmap

78.1
78.2
78.3
78.4
Donald Cottrell
Introduction
Design Automation An Historical Perspective
The Future
Summary
SECTION XII
79
James H. Aylor
Embedded Computing Systems and Hardware/Software Co-Design

Wayne Wolf
77.1
77.2
77.3
77.4
78
Introduction
The Two HDLs
The Three Different Domains of Synthesis
RTL Synthesis
Modeling a Three-State Gate
An Example
Behavioral Synthesis
Conclusion
Performance Modeling and Analysis in VHDL

and Robert H. Klenke
76.1
76.2
76.3
76.4
76.5
77
Selecting Implementation and Packaging Styles for System Modules

The Interconnection Strategy
Word Length Determination
Predicting System Characteristics
A Survey of Research in System Design
Algorithms and Architects
Algorithms and Architectures for Multimedia and Beamforming

Communications Flavio Lorenzelli and Kung Yao
79.1 Introduction
79.2 Multimedia Support for General Purpose Computers
79.3 Beamforming Array Processing and Architecture
SECTION XIII
80
Design Languages
80.1
80.2
80.3
80.4
80.5
80.6
80.7
80.8
80.9
81
Design Languages
David L. Barton
Introduction
Objects and Data Types
Standard Logic Types
Concurrent Statements
Sequential Statements
Simultaneous Statements
Modular Designs
Simulation
Test Benches
Hardware Description in Verilog: An Introductory Tutorial

Zainalabedin Navabi
81.1
81.2
81.3
81.4
81.5
81.6
81.7
Elements of Verilog
Basic Component Descriptions
A Complete Design
Controller Description
Gate and Switch Level Description
Test Bench Descriptions
Summary

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The VLSI handbook / edited by Wai-Kai Chen.

2000 by CRC Press LLC

Locating Your Topic

2000 by CRC Press LLC

Wai-Kai Chen, Professor and Head of the Department of Electrical

2000 by CRC Press LLC

Professor Steve M. Kang

Professor Saburo Muroga

Dr. Bing J. Sheu

2000 by CRC Press LLC

Jet Propulsion Laboratory

Conexant Systems, Inc.

Silicon Integration Initiative,

2000 by CRC Press LLC

John Choma, Jr.

Amy Hsiu-Fen Chou

Moon Jung Chung

Maria del Mar

Brigham Young University

Brigham Young University

The Georgia Institute

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Atmel, Multimedia and

Royal Institute of Technology

The Ohio State University

Hankuk University of Foreign

2000 by CRC Press LLC

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NASA Glenn Research Center

NTT Network Innovation

The Ohio State University

Frank Ruei-Ling Lin

2000 by CRC Press LLC

Royal Institute of Technology

Antrim Design Systems

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Evans Ching-Song Yang

National Tsing-Hua University

Rick Shih-Jye Shen

Industrial Research and

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National Taiwan University

Katholieke Universiteit Leuven

2000 by CRC Press LLC

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VLSI Technology: A System Perspective

Krishna Shenai and

CMOS/BiCMOS Technology Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi

Jan V. Grahn and Mikael stling

Silicon on Insulator Technology

2000 by CRC Press LLC

Noise in VLSI Technologies

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2000 by CRC Press LLC

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Multichip Module Technologies

Bulk Micromachining of Silicon

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Channel Hot Electron Degradation-Delay in MOS Transistors Due

2000 by CRC Press LLC

Bipolar Junction Transistor (BJT) Circuits

Analog Circuit Simulation