1

FULL BRIDGE DC-DC CONVERTER WITH HIGH

VOLTAGE GAIN
C.Anupriya, D.Maheswari
Finalyear, EEE
J.P.CollegeOf Engineering, Tenkasi
priya.anu5001@gmail.com
Abstract-In this paper a dc-dc converter
suitable for high step-up application is
presented. Asymmetrical pulse width
modulation technique is implemented for
the control of the converter. Soft
switching techniques such as Zero voltage
switching (ZVS), Zero current switching
(ZCS)are used. ZVS of all power switches
and ZCS of the output diodes are
achieved. The converter provides high
voltage gain and the voltage across the
semiconductor devices are effectively
clamped. A suitable control strategy
including asymmetric pulse width
modulation (APWM) is developed and
simulation results are presented in order
to
know
about
the
important
characteristic features of the proposed
system.
Index terms- Zero voltage switching
(ZVS), Zero current switching (ZCS),
high voltage gain.

1. INTRODUCTION
High efficiency
dcdc converters with
high-voltage gain are required as an
interface system between the low voltage
sources and the load which requires higher
voltage in many applications such as electric
vehicles, uninterruptible power supplies,
fuel cells, and photovoltaic systems . A

conventional boost converter is often used in

step-up applications due to its simple
structure and low cost. However, it is not
suitable for high step-up applications. The
requirement of extreme duty cycle to obtain
high voltage gain is a major limitation. Also,
degradation of system performance due to
reverse recovery problem of the output
diodes.
In order to remedy these problems,
synthesis of tapped inductor converters
have been suggested. However, they have
parasitic oscillations across the switches and
diodes.This is due to a resonance between
the leakage inductance of a coupled inductor
and
parasitic
capacitances
of
the
semiconductor devices. Also, there exists a
need for galvanic isolation between the input
and output stages of the power converters.
In high step-up applications the current-fed
converters are often used. However, the
voltage stresses of the switches are serious
in them. The voltage-fed converters such as
phase-shift full-bridge (PSFB) converters,
which are widely used
have some
drawbacks including large conduction loss
due to circulating current, duty cycle loss,
and the voltage spikes across output
rectifiers. To remedy these problems, the
topologies that have been proposed had

increased the complexity and the overall

cost. Also the system efficiency decreases.
In order to overcome these problems,
an asymmetrical full bridge dc-dc converter
with high-voltage is proposed. Fig. 1 shows
the proposed converter. The asymmetric
pulse width modulation (APWM) technique
is applied to the proposed converter. This
eliminates switching losses and maintain
low conduction loss. The APWM technique
has various advantages such as zero
switching loss, no conduction loss penalty,
and fixed switching frequency. High-voltage
gain, fixed switching frequency, softswitching operations of all power switches
and output diodes, and clamped voltages
across power switches and output diodes are
features of the proposed converter. The
additional inductor at the secondary side
alleviates the reverse recovery problem of
the output diodes. Thus, the proposed
converter shows high efficiency and it is
suitable for high-voltage applications.
II. PRINCIPLE OF OPERATION
A. Circuit Description
Fig. 1 shows the circuit diagram
of the proposed dc-dc converter with highvoltage gain. The proposed converter has
four power switches S1 through S 4 . C C
is the clamping capacitor between top side
switches S1 and S 3 of two switch bridges.
The voltages across the switches S1

and

S 2 in the first bridge are confined to the

input voltage Vin . The clamping capacitor

CC

can clamp the voltages across the

switches S 3 and S 4 in the second bridge.

The output stage of the proposed converter

has a voltage doubler structure that consists

of the secondary winding N 2 of the
transformer T, the serial inductor LS , the
output capacitors C 01 and C 02 , and the
output diodes D01 and D02 .According to
the voltage doubler structure, the voltage
gain increases. Also, the voltage stresses of
the output diodes are confined to the output
voltage V0 without any auxiliary circuits.
Fig.2 shows the equivalent circuit of the
proposed converter. The diodes D1 through
D4 are the intrinsic body diodes of all

switches. Their parasitic output capacitances

are represented through the capacitors C1
through C 4 .The transformer T is modeled
as the magnetizing inductance Lm and the
ideal transformer that has a turn ratio of 1:n

N2
.
N 1

Its

leakage

inductance

is

included in the serial inductor LS . The

output capacitor voltages are assumed to be
constant as V01 and V02 , respectively. The

switch S1 S 4
and the switch S 2 S 3
are operated asymmetrically and the duty
cycle D is based on the switch S1 S 4 . A
small delay between driving signals for S1

S4

and S 2 S 3 is a dead time for the

switches. This prevents cross conduction
and allows ZVS. Fig. 3 shows the theoretical
waveforms of the proposed converter.

B. Modes of Operation
During a switching period Ts the operation
of the proposed converter is divided into
four modes. This is illustrated in Fig. 4.
Before t 0 , the switches S 2 an
Fig. 1 Circuit diagram of proposed converter

d S 3 , and the output diode

D01

are

conducting.
Mode 1: The switches S 2 and S 3

are

turned OFF at t 0 . Then, the energy stored

in the magnetic components starts to
charge/discharge the parasitic capacitances
C1 through C 4 . Thus, the voltages VS 2
Fig.2 Equivalent circuit of proposed
converter

and VS 3 start to rise from zero. Similarly,

the voltage VS 4 starts to fall from
Vin VC and the voltage VS 1 starts to fall

from Vin . When the voltages VS 1 and

VS 4 arrive at zero, their body diodes D1
and D4 are turned ON. Then, the gate
signals are applied to the switches S1 and
S 4 . Since the currents have already flown

through

D1 and D4

and the voltages

VS 1 and VS 4 are clamped as zero before

the switches S1 and S 4 are turned ON,

zero-voltage turn-ON of S1 and S 4 is
achieved. With the turn-ON of S1 and S 4 ,
the primary voltage V p across Lm is Vin .
Then, the magnetizing current is given by
im t I m 2

Fig.3 Theoretical waveforms

Vin
t t0
Lm

(1)

The voltage VLs across Ls is nVin V01 .

The secondary current is increases
follows:

i s t I D 01

nVin V01 t t 0
Ls

as

( 2)

Mode 4

In this mode, the switch currents i s1 and

i s 4 can be written by

Fig. 4 Modes of Operation

Vin n nVin V01
t t 0

Ls
Lm

is1 t is 4 t I m 2 nI D 01

(3)

Mode 2: At t1 , the currents i s and i D 01

arrive at zero and the diode D01 is turned
OFF. Then, the output diode D02 is turned
ON and its current increases linear. The
serial inductor Ls controls the current
changing rate of D01 .Thus its reverserecovery problem is significantly alleviated.
Since the voltage VLS is nVin V02 in
this mode, the current is are given by

Mode 1

nVin V02
Ls

is t

t t1

(4)

The voltage V p is not changed. In this

mode, the switch current i s1 and i s 4 can
be written by
Mode 2

V
n nVin V02
t t1
iS 1 t iS 4 t in
Ls
Lm

(5)

Mode 3: This mode is similar to mode 1.

The switches S1 and S 4 are turned OFF a
t 2 . The parasitic capacitors C1 and C 4

start to be charged from zero and the

parasitic capacitors C 2 and C3 start to be
Mode 3

discharged

from Vin

and Vin Vc

respectively. After the parasitic capacitors

are fully charged and discharged, the
voltages VS 2 and VS 3 become zero and
the body diodes D2 and D3 are turned ON.
Then, the gate signals are applied to the
switches S 2 and S 3 . Since the currents
D2 and D3

have already flown through

significantly alleviated. Since the voltage

V LS is

nVin VC V01 , the current i

is given by
is t

nVin Vc V01
Ls

t t3

(9)

and the voltages VS 2 and VS 3 are clamped

The voltage VP is not changed in this

as zero, zero-voltage turn-ON of S 2 and S 3

mode. In this mode, the switch currents i S 2

is achieved. Thus, the voltage VP across

and i s 3 can be written by

Lm is Vin VC . Then, the current im

decreases as follows:
Vin Vc
Lm

im t I m1

The

voltage

t t 2

(6)

V LS

nVin VC V02 .

across
The

Vin Vc n nVin Vc V01

t

Lm
Ls

is 2 t is 3 t im t3

LS

current

(10)
is
C. Calculation of voltage gain

iS

decreases as follows:

The volt-second balance law gives

nVin VC V02
t t 2
Ls

iS t I D 02
(7)

In this mode, the switch currents i S 2 and

Vin DTS Vin VC 1 D TS 0

From
(11)
(11), the clamping capacitor voltage VC is
obtained by

is 3 can be written by

VC

Vin Vc n nVin Vc V02

t t 2

Lm
Ls

is 2 t is 3 t I m1 nI D 02

(8)
Mode 4: This mode is similar to mode 2.The
currents i S and i D 02 arrive at zero and the
diode D02 is turned OFF at t 3 . Then, the
output diode D01 is turned ON and its
current increases linearly. The current
changing rate of D02 is controlled by LS
and thus, its reverse-recovery problem is

2D 1
Vin
1 D

(12)

From (2) and (9) the maximum diode

current I D 01 can be written as follows

nVin VC V01
1 D d 2 TS
LS
(13)
From (12) and (13) the voltage V01 is
obtained by
I D 01

V01

D
d2
1 D
nVin
1 D d1 d 2

D d1

From (4) and (7) the maximum diode

current I D 02 can be written as follows

nVin VC V02
d 2TS
LS
can be obtained

by

V02

V0
n 1 2 k D

Vin D 1 2 D k 1 D 1 2 D k

III. SIMULATION CIRCUIT

(15)
From (12) and (15) V02

(20)
Using (14), (16),(18),(19), the voltage gain
M of the proposed converter is obtained by

(14)

I D 02

8 Ls I 0
1
1 1

2
nDVinTs

D
d2
1 D
nVin
D d1 d 2

D d1

(16)
The secondary current i S is the sum of the
current flowing through the output
capacitors C 01 and C 02 .Therefore, the

Simulation is done using MATLAB.

MATLAB is a software package for
computation in engineering, science, and
applied mathematics. Simulink (Simulation
and Link) is an extension of MATLAB by
Math works Inc. It works with MATLAB to
offer modeling, simulating, and analyzing of
dynamical systems under a graphical user
interface (GUI) environment.
The table below shows the components list
for the simulation circuit:

average value of i S should be zero. As a

result, the average values of the diode
currents i D 01 and i D 02 are equal to the
output current I 0 and the following relation
can be

I0

D d1 d 2 I D02
2

(17)

From (13) and (17), the values of d1 and

d 2 is obtained by
d1 kD

(18)

d 2 k 1 D

(19)

Fig.5 shows the simulation circuit of

full- bridge dc-dc converter with high
voltage gain. The full bridge circuit formed

by switches S1 , S 2 , S 3 , S 4 acts as a single

phase inverter which converts DC voltage
into AC component. Here MOSFET is used
as the power switches because of its low
switching loss and high input impedance.
The switch S1 S 4
and the switch S 2

S3

duty cycle D is based on the switch S1 S 4

. A small delay between driving signals for
S1 S and S 2 S 3 is a dead time for the
4

switches. It prevents cross conduction and

allows ZVS.

are operated asymmetrically and the

Fig.5 Simulation circuit

IV. SIMULATION RESULTS
The voltages across the switches go to
zero before the gate pulses are applied to the
switches. Since the switch voltages are
clamped as zero before the gate pulses are
applied, the ZVS turn-ON of the switches is
achieved. The ZVS operation of the power
switch S 3 is shown in Fig.6. In ZVS
switches are turned on and off at zero
voltage. Thus switching losses are
eliminated. Here switching of MOSFET S 3
is shown.

VS 3

Time
VgS 3

Time
Fig.6 Zero Voltage Switching
Simulation result of output voltage
waveform is shown in Fig.7. An input dc
voltage of 48 V is given to inverter and
output is stepped up. Then fed to voltage
doubler which rectifies it and increases the
dc output and an output of 400V is obtained.
V0

high efficiency and it is suitable for highvoltage applications.

In the proposed system ZVS
of all power switches and ZCS of the output
diodes are achieved. The proposed converter
is able to provide a high efficiency and highvoltage gain with relatively low transformer
turn ratio. Also, without any auxiliary
circuits, the voltages across the switches and
the output diodes are effectively clamped.
Therefore, the proposed converter is suitable
for high-voltage applications. The voltage
gain is 8.3 with the transformer turn ratio of
4. It provides a high efficiency of 95.3% at
full load.
VI. REFERENCES

Time
Fig.7 Output Voltage Waveform

V . CONCLUSION
The APWM technique is applied to the
proposed converter to eliminate switching
losses and maintain low conduction loss.
The limitation of the maximum duty cycle
disappears in the proposed topology. The
proposed converter features high-voltage
gain, fixed switching frequency, softswitching operations of all power switches
and output diodes, and clamped voltages
across power switches and output diodes.
The reverse recovery problem of the output
diodes is significantly alleviated due to an
additional inductor at the secondary side.
Therefore, the proposed converter shows

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