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BasicsofCISC
andRISCmachines
171005EmbeddedSystems
Lecture3
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CISCProcessordetails
Beforedecidingwhichprocessor,designershouldthinkwhich
architecturefortheprocessortobeselected?
CISCandRISCarethepopulararchitecturewithmeritsand
demerits.
CISCwereprovidingakindofinstructionsthathelpedincompiler
designeasy!Andthatswhytheinstructionsetwassupportedwith
instructionsforcomplextaskandhencethetaskofcompileris
simplertoconverthighlevellanguageintomachinecodes!
Henceprocessorsweresoldearlierbasedonthecomplexitiesthey
canhandlewithinstructions,addressingmodesanddatatypes.
Butthisrequireshighernumberofgatesonthedietoimplement
complexinstructions.
Eventheexecutiontimeforalltheinstructionsarenotremaining
same!

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ThekindofactivitieshandledbyourCPUare:
InstructionandDatamovementbetweenCPUand
memory.
Executionofinstructions
ALUoperations
DatamovementbetweenCPUandmemoryasapartof
executionoftheinstructions.
DatamovementsbetweenregistersintheCPU

Wemustconsiderthedynamicuseofinstructions
inourprogram.

DynamicInstructionUsage

Around33%instructionsforALUoperationsand67%for
DatamovementandControlflowoperation!
Thistellsthatthemostimportantinstructionstooptimize
arethosewhicharedealingwithdatamovement.

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TypicalSequenceofOperationinCPU

Pipelining
WhatisPipelining?
Pipelininghelpsinfasterexecutionofthe
instructions.

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Read WritePipelineHazard

BranchPipelineHazard

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Problemsinpipeliningduringbranch
instructions.
Pipeliningprovesbetterifexecutiontimeofall
instructionsareuniform.
Itisdifficulttoimplementpipeliningforthe
complexinstructions.
HenceCISCarchitectureisnotinfavorof
achievingfasterexecutiononarchitecture
level.

Tobringuniformityinexecutiontimeforthesupportofpipelining:
Allinstructionweredesignedofbeingfixedlengthinamodified
architecture
Allinstructionsweredesignedsuchthattheyallexecuteinsametime
thatissinglecycleexecutionforpipelinebenefits.Thisleadtoavoiding
Complexinstructionandusingsimpleinstructions(Thatiswhy
ReducedInstructionSet).
Itisnotpossibletoachieveakindofexecutionwherememorydatais
read,processedandagainmodifiedinasinglecycleexecution.
HenceLoad StoreArchitecturewasdesignedwhichsupports
instructionswhichloadsamemorydataintoCPUorstoresCPU
registertomemoryinseparateinstructions.
Largeregisterwindowbankswasrequiredtooperateload store
instructionsefficiently.
Thewholedesignwascarriedoutbasedon32bitarchitecture.

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RISCAdvantages
CISCrequiredhighernumberofgatesondielevelfor
complexinstructionexecution.ButRISCsupports
simplerinstructionset.Henceitdealswithsmalldie
size.
Thishelpsinachievingreducedpowerconsumption.
Shorterdevelopmenttimeforthecpu.
Asimplerprocessorallowshighclockrateonthe
board;whileaCISCkindofmachineisrestrictedfor
theirhigherfrequencyofoperations.
CISCmachinesarehavingmicrocodeROMstodecode
theinstruction;whileRISCprocessorusingHardwired
logicwhichismuchfaster.

DisadvantagesofRISC
PoorcodedensityascomparedtoCISC.So,
highermemoryrequirementswillbetherein
turnhighermemorypowerconsumption.
X86codesarenotportable.

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ARMArchitecture
AcornRISCMachine(ARM)utilizedtheRISCarchitectureforembedded
applicationdevelopment.
FeaturesusedfromRISCarchitecture
ALoadstoreArchitecture
Fixedlength32bitinstructions
3addressinstructionformat(eg.addr0,r1,r2)

FeaturesRejected

RegisterWindows
DelayedBranches
Singlecycleexecutionofallinstruction(Thisisfoundtobepossibleonlyif
dataandinstructionmemoriesareseparate.InitiallyARMwasdesignedwith
VonNeuman Architecturewheredataandinstructionmemoriesare
different)

Featuresadded

ThumbInstructionsettoachievehighercodedensity