Topic: Timer and Counter of dsPIC30F4011

Group 2
Members:
1.Nguyn Vit Hng
2.Phm Quang i
3.Phm Vn Hiu
4.Ng Trng Linh

October 9th, 2014

1. Introduction

dsPIC30F4011 has five 16-bit timers/counters; optionally pair 16-bit

timers into 32-bit timer modules.

The 16-bit timers are classified into three types to account for their
functional differences:
Type A time base
Type B time base
Type C time base

Timer1 is a Type A timer.

Timer2 and Timer4 are TypeB timer.
Timer3 and Timer5 are TypeC timer.

Each timers/counters consists those following readable/writable

registers:
TMRx: 16-bit timer count register
PRx: 16-bit period register associated with the timer
TxCON: 16-bit control register associated with the timer

Each timer module also has the associated bits for interrupt control:
Interrupt Enable Control bit (TxIE)
Interrupt Flag Status bit (TxIF)
Interrupt Priority Control bits (TxIP<2:0>)

2.Timer 16 bits:
Type A Timer:
A Type A timer has the following unique features over other types:
can be operated from the device Low Power 32 kHz Oscillator.
Low-Power 32 kHz Crystal Oscillator
The LP or Secondary oscillator is designed specifically for low power operation
with a 32 kHz crystal. The LP oscillator is located on the SOSCO and SOSCI
device pins and serves as a secondary crystal clock source for low power
operation. The LP oscillator can also drive Timer1
for a real-time clock application.

can be operated in an Asynchronous mode from an external clock

source.

2.1.Timer A block diagram:

2.2 Control Register:

bit 15 TON:Timer On Control bit

1= Starts the timer
0= Stops the timer

bit 13 TSIDL:Stop in Idle Mode bit

1= Discontinue timer operation when device enters Idle mode
0= Continue timer operation in Idle mode

bit 6 TGATE:Timer Gated Time Accumulation Enable bit

1= Gated time accumulation enabled
0= Gated time accumulation disabled
(TCS must be set to 0 when TGATE = 1. Reads as 0 if TCS = 1)

bit 5-4 TCKPS<1:0>:Timer Input Clock Prescale Select bits

11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value

bit 2 TSYNC:Timer External Clock Input Synchronization Select bit

When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored. Read as 0. Timer1 uses the internal clock when
TCS = 0.

bit 1 TCS:Timer Clock Source Select bit

1= External clock from pin TxCK
0= Internal clock (FOSC/4)

2.3.Modes of Operation
Timer A module can operate in one of the following modes:
As a synchronous timer
As a synchronous counter
As a gated timer
As an asynchronous counter (Type A time base only)

2.3.1. Timer Mode

In Timer mode, the input clock to the timer is provided from the internal
system clock (FOSC/4). In the 16-bit Timer mode, the timer increments
on every instruction cycle up to a match value, preloaded into the period
register PR1, then resets to 0 and continues to count.

2.3.2Synchronous Counter Mode Using External Clock Input:

When the TCS control bit (TxCON<1>) is set, the clock source for the
timer is provided externally and the selected timer increments on every
rising edge of clock input on the TxCK pin which is synchronized with
the internal phase clocks.

2.3.3. Type A Timer Asynchronous Counter Mode Using External Clock

Input

In the 16-bit Asynchronous Counter mode, the timer increments on

every rising edge of the applied external clock signal. The timer counts
up to a match value preloaded in PR1, then resets to 0 and continues.

2.3.4. Gated Time Accumulation Mode:

The Gated Time Accumulation mode allows the internal timer register to
increment based upon the duration of the high time applied to the TxCK
pin. In the Gated Time Accumulation mode, the timer clock source is
derived from the internal system clock.

3. Timer 32 bit
Timer 2/3 module:
A 32-bit timer module can be formed by combining a Type B and a
Type C 16-bit timer module.
The Type C time base becomes the MSWord of the combined timer and
the Type B time base is the LSWord.
The control bits for the Type B time base control the operation of the 32bit timer.
For interrupt control, the combined 32-bit timer uses the interrupt
enable, interrupt flag and interrupt priority control bits of the Type C
time base.

The following configuration settings assume Timer3 is a Type C time

base and Timer2 is a Type B time base:
TON (T2CON<15>) = 1.
T32 (T2CON<3>) = 1.
TCKPS<1:0> (T2CON<5:4>) are used to set the Prescaler mode for
Timer2
(Type B time base).
The TMR3:TMR2 register pair contains the 32-bit value of the timer
module; the TMR3
(Type C time base) register is the Most Significant Word, while the
TMR2 (Type B time base) register is the Least Significant Word of the
32-bit timer value.
The PR3:PR2 register pair contains the 32-bit period value that is used
for comparison with the TMR3:TMR2 timer value.
T3IE (IEC0<7>) is used to enable the 32-bit timer interrupt for this
configuration.
T3IF (IFS0<7>) is used as a status flag for the timer interrupt.
T3IP<2:0> (IPC1<14:12>) sets the interrupt priority level for the 32bit timer.
T3CON<15:0> are dont care bits

3.1 Timer mode:

3.2 Synchronous counter mode:

3.3 Gated time accumulation mode:
3.4 ADC Event Trigger:
On each device variant, one Type C time base has the capability to
generate a special A/D conversion trigger signal on a period match, in
both 16 and 32-bit modes. The timer module provides a conversion start
signal to the A/D sampling logic.
If T32=0, when a match occurs between the 16-bit timer register
(TMRx) and the respective 16-bit period register (PRx), the A/D special
event trigger signal is generated.
If T32=1, when a match occurs between the 32-bit timer
(TMRx:TMRy) and the 32-bit respective combined period register
(PRx:PRy), the A/D special event trigger signal is
generated.

4. Input capture:
The Input Capture module has multiple Operating modes, which are
selected via the ICxCON register. The Operating modes include:
Capture timer value on every falling edge of input applied at the ICx
pin
Capture timer value on every rising edge of input applied at the ICx pin
Capture timer value on every fourth rising edge of input applied at the
ICx pin
Capture timer value on every 16th rising edge of input applied at the
ICx pin
Capture timer value on every rising and every falling edge of input
applied at the ICx pin

The Input Capture module has a four-level FIFO buffer. The number of
capture events required to generate a CPU interrupt can be selected by
the user.

4.1 Input capture register:

ICxCON: Input Capture Control Register

ICxBUF: Input Capture Buffer Register

+bit 13 ICSIDL:Input Capture Module Stop in Idle Control bit

1= Input capture module will halt in CPU Idle mode
0= Input capture module will continue to operate in CPU Idle mode

+bit 7 ICTMR:Input Capture Timer Select bits

1= TMR2 contents are captured on capture event
0= TMR3 contents are captured on capture event

+bit 6-5 ICI<1:0>:Select Number of Captures per Interrupt bits

11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event

+bit 4 ICOV:Input Capture Overflow Status Flag (Read Only) bit

1= Input capture overflow occurred
0= No input capture overflow occurred

+bit 3 ICBNE:Input Capture Buffer Empty Status (Read Only) bit

1= Input capture buffer is not empty, at least one more capture value can
be read
0= Input capture buffer is empty

+bit 2-0 ICM<2:0>:Input Capture Mode Select bits

111= Input Capture functions as interrupt pin only, when device is in
Sleep or Idle mode
(Rising edge detect only, all other control bits are not applicable.)
110= Unused (module disabled)
101= Capture mode, every 16th rising edge
100= Capture mode, every 4th rising edge
011= Capture mode, every rising edge
010= Capture mode, every falling edge
001= Capture mode, every edge (rising and falling)
(ICI<1:0> does not control interrupt generation for this mode.)

000= Input capture module turned off

5. Output compare:
The Output Compare module has the ability to compare the value of a
selected time base with the value of one or two compare registers
(depending on the Operation mode selected). Furthermore, it has the
ability to generate a single output pulse, or a train of output pulses, on a
compare match event. Like most dsPIC peripherals, it also has the ability
to generate interrupts-on- compare match events.

5.1 Output Compare Registers

Each output compare channel has the following registers:
OCxCON: the control register for the channel
OCxR: a data register for the output compare channel
OCxRS: a secondary data register for the output compare channel
The control registers for the 8 compare channels are named OC1CON
through OC8CON. All 8
control registers have identical bit definitions. They are represented by a
common register
definition below. The x in OCxCON represents the output compare
channel number.

bit 13 OCSIDL:Stop Output Compare in Idle Mode Control bit

1= Output compare x will halt in CPU Idle mode
0= Output compare x will continue to operate in CPU Idle mode

bit 4 OCFLT:PWM Fault Condition Status bit

1= PWM Fault condition has occurred (cleared in HW only)
0= No PWM Fault condition has occurred
(This bit is only used when OCM<2:0> = 111.)

bit 3 OCTSEL:Output Compare Timer Select bit

1= Timer3 is the clock source for compare x
0= Timer2 is the clock source for compare x

bit 2-0 OCM<2:0>:Output Compare Mode Select bits

111= PWM mode on OCx, Fault pin enabled
110= PWM mode on OCx, Fault pin disabled
101= Initialize OCx pin low, generate continuous output pulses on OCx
pin
100= Initialize OCx pin low, generate single output pulse on OCx pin
011= Compare event toggles OCx pin
010= Initialize OCx pin high, compare event forces OCx pin low

001= Initialize OCx pin low, compare event forces OCx pin high
000= Output compare channel is disabled.

5.2.1.Compare Mode Output Driven High

To configure the output compare module for this mode, set control bits
OCM<2:0> = 001. The compare time base should also be enabled.
Once this Compare mode has been enabled, the output pin, OCx, will be
initially driven low and remain low until a match occurs between the
TMRy and OCxR registers.

5.2.2.Compare Mode Output Driven Low:

To configure the output compare module for this mode, set control bits
OCM<2:0> = 010. The compare time base must also be enabled. Once
this Compare mode has been enabled, the output pin, OCx, will be
initially driven high and remain high until a match occurs between the
Timer and OCxR registers.

5.2.3.Single Compare Mode Toggle Output:

To configure the output compare module for this mode, set control bits
OCM<2:0> = 011. In addition, Timer 2 or Timer 3 must be selected
and enabled. Once this Compare mode has been enabled, the output pin,
OCx, will be initially driven low and then toggle on each and every
subsequent match event between the Timer and OCxR registers.

Homeworks:
1. Write an initialization code for timer 2 functioning in Gated Time
Accumulation Mode.
2. Write a program using timer/counter for toggling a led 0.7s on
0.3s off.
3. Write a program varying the brightness of led using timer/counter.