EC 1354 VLSI Design (As per Trichy Anna University

syllabus)

May/June 2012 Question paper :< /H2>

Part-A:
1. Design a NOR gate using basic CMOS technology.
2. Write a note on channel-length modulation.
3. How do the problem of latch up prevented?
4. Write a brief note on transmission gates.
5. What is the link between the shapes and resistance?
6. When the MOS characteristics is in the stage of accumulation, depletion
and inversion,draw the capacitance effect?
7. Write a brief note on two phase clocking.
8. Design a simple half adder circuit.
9. What is the function of assert statement?
10. What is meant by overloading?

Part-B:
11. a) (i) Discuss in detail the behavior of NMOS devices under the influence of
different terminal voltages? (8)
(ii) Derive an expression for Threshold voltage. (8)
(or)
b) (i) Give a brief note on
1. Body effect
2. Mobility variation
3. Fowler Nordhum Tunneling
4. Impact Ionization
(ii) Derive and draw the necessary equations for a small signal model of an MOS
transistor. (6)
12. a) Discuss in detail the characteristics of CMOS INVERTER circuit. Also draw the

layout diagram and stick diagram for an inverter. (16)

(Or)
b) Write a detailed note on the following
(i) Pseudo NMOS Inverter
(ii) Saturated load Inverter
(iii) Cascade inverter
(iv) TTL interface inverter (5 + 5 + 3 + 3 )
13. a) With equation and necessary diagram explain in detail the capacitance
estimation of MOS Device. (16)
(or)
b) For a CMOS inverter, draw the equivalent circuit and obtain. (16)
(i) Fall delay
(ii) Rise delay
(iii) Delay delay
(iv) Gate delay
(v) Switch level RC model.
14. a) Design the following circuits using VLSI design.
(i)Multiplexers (ii) Multiplier (iii) Full adder.
(or)
b) Draw a neat layout, circuit diagram and explain with necessary equations for the
following circuit.
(i) Bit serial adder
(ii) Carry save adder
(iii) Transmission gate adder
(iv) Carry look ahead adder.
15. a) Discuss elaborately the various data types with examples. (8)
(or)
b) Explain in detail the various levels of modeling with suitable example. (8)

Anna university
Department of Electronics and Communication Engineering.
subject code : EC 1401
subject name : VLSI DESIGN
Year : 4th
sem : 7th
(Common to B.E.(Part-Time) Sixth Semester Regulation 2005)
(Regulation 2004)
B.E/B.Tech Degree Examination,November/December 2009.
Part A-(10*2=20 marks)
1.What are the different MOS layers?
2.What are the two types of layout design rules?
3.Define rise time and fall time.
4.What is a pull down device?
5.What are the difference between task and function?
6.What is the difference between === and == ?
7.What is CBIC ?
8.Draw an assert high switch condition if input = 0 and input =1.
9.What do you mean by DFT?
10.Draw the boundary scan input logic diagram.
Part B - (5*16=80 marks)
11.a) Discuss the steps involved in IC fabrication process.(16)
Or
b) Describe n-well process in detail.(16)
12.a)i)Explain the DC characteristics of CMOS inverter with neat sketch.(8)
ii)Explain channel length modulation and body effect.(8)
Or
b)i)Explain the different regions of operation in a MOS transistor.(10)
ii)Write a note on MOS models.(6)
13.a)Explain in detail any five operators used in HDL .(16)
Or
b)i)Write the verilog code for 4 bit ripple carry full adder.(10)
ii)Give the structural description for priority encoder using verilog.(6)

14.a)Explain in detail the sequence of steps to design an ASIC.(16)

Or
b)Describe in detail the chip with programmable logic structures.(16)
15.a)Explain in detail Scan Based Test Techniques.(16)
Or
b)Discuss the three main design strategies for testability.(16)

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/ DECEMBER 2007

Seventh semester
(Regulation 2004)
Electronics and Communication Engineering
EC 1401 VLSI DESIGN
(Common to B.E. part time) sixth Semester Regulation 2005)
Answer all questions
PART A (10*2=20marks)
1. What are the advantages of SOI CMOS process?
2. Distinguish electrically alterable and non-electrically alterable ROM.
3. Compare nMOS and pMOS.
4. Compare enhancement and depletion mode devices.
5. What is meant by continuous assignment statement in Verilog HDL?
6. What is a task in Verilog?
7. Give the application of PLA.
8. What is meant by a transmission gate?
9. What is the aim of adhoc test techniques?
10. Distinguish functionality test and manufacturing test.
PART B (5*16=80 marks)
11. (a) (i) Draw and explain the n-well process.
(ii) Explain the twin tub process with a neat diagram.
OR
(b) (i) Discuss the origin of latch up problems in CMOS circuits with necessary diagrams.
Explain the remedial measures.
(ii) Draw and explain briefly the n-well CMOS design rules.
12. (a) (i) Derive expressions for the drain to source current in the nonsaturated and
saturated regions of operation of an nMOS transistor.
(ii) Define and derive the transconductance of nMOS transistor.
OR
(b) (i) Discuss the small signal model of an nMOS transistor.
(ii) Explain the CMOS inverter DC characteristics.

13. (a) (i) Give a verilog structural gate level description of a bit comparator.
(ii) Give a brief account of timing control and delay in verilog.
OR
(b) (i) Give a verilog structural gate level description of a ripple carry adder.
(ii) Write a brief note on the conditional statements available in verilog.
14. (a) (i) Compare the different types of ASICs.
(ii) Discuss the operation of a CMOS latch.
OR
(b) Explain the ASIC design flow with a neat diagram. Enumerate clearly the different steps
involved.
15. (a) Explain the chip level test techniques.
OR
(b) Explain the system level test techniques.