Stratix II GX SI Structure

1. Introduction:
This document contains the description of the ArmstrongGX SI directory structure, links, and spice files. It contains 3
different spice templates for TX, RX. The TX by itself has a TX driver with 100-ohm internal termination resistor. The RX
by itself has a RX receiver with 100-ohm internal resistor; a sample backplane and ideal driver is included.

2. Directory Structure:

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There are 4 directories under armGX/. Inc directory contains all files called by spice files. Tx, rx, and tx_rx directories contains
spice template that can be modified depending on the application.
./inc/ : this directory contains the following:
include files (parameters, options,)
patterns (input, ouput, prbs, ), and script to generate data input pattens
spice netlists of drivers/receivers
./tx/ : contains the spice template to run TX block.

./rx/ : contains the spice template to run RX block.

3. Spice simulation:

a. Files under ../inc/ directory:

- Netlist:

i. tx.cir:
ii. rx.cir:

TX driver netlist
RX receiver netlist

- Process Corner:
i. 2sgx_tt.inc : Typical / Typical process corner
ii. 2sgx_ff.inc : Fast / Fast process corner
iii. 2sgx_ss.inc : Typical / Typical process corner
- Data input
i. tx_data_input: TX input data
- Scripts:
i.
ii.
iii.
iv.
v.
vi.

tx_ingen: generates the spice input patterns for TX. Type tx_ingen in ./inc/ directory for instruction.
d0_gen, d1_gen, d2_gen, & d3_gen: sub-scrips of tx_ingen.
rx_ingen: generates the spice input patterns for RX.
rgen: a sub-script of rx_ingen
prbs7.bit: a sample of prbs7 binary bits.
Example: When executing the command tx_ingen prbs7.bit inside the inc directory , a tx_data_input file
will be generated. Prbs7.bit can be replaced with any other binary file with 0100101011 pattern.

- Control setting files:

i. tx_setting.inc: library to control all TX setttings
ii. rx_setting.inc: library to control all RX settings.
- Probing nodes:
i. tx_probe.inc: probing nodes of TX blocks
ii. rx_probe.inc: probing nodes of RX blocks

b. TX Driver:

VCCHX

VID

VCCHTX

VCCTX

Below (figure 1) is the TX driver block diagram. The left has one TX input signal (VID) and the rest are RAM bits to control
the eye opening, the pre-emphasis, the slew rate, the termination resistor, and the common mode voltage. The top has the
power pins and the bottom has the ground pins. The right has the near-end output pins (TXP_NEAR/TXN_NEAR). See the
pin description for more detail of every pin.

TX_VOD_SEL[2:0]
TX_PRE_EM_1T[3:0]
TXP_NEAR
TX_PRE_EM_2T[2:0]

TX
Driver

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TX_PRE_EM_PT[2:0]
TX_SIGINV_2T

TXN_NEAR

TX_SIGINV_PRE
TX_R_SLEW

VSSX

TX_TERM_SEL[1:0]
TX_VTT[1:0]

Figure 1: A simplify TX driver

Pin description:

i. TX data input
a. VID: TX data input. Data input can be any data pattern.

ii. Output voltage control:

a. TX_VOD_SEL[2:0]: Control the current at the output control the output voltage

TX_VOD_SEL[2:0]
000
001
010
011
100
101
110
111

Table1: VOD settings

Output Current
2mA
4mA
6mA
8mA
10mA
12mA
14mA
Reserved

Hspice Setting
vod_2ma
vod_4ma
vod_6ma
vod_8ma
vod_10ma
vod_12ma
vod_14ma
vod_reserve

iii. Pre-emphasis:
a.

TX_PRE_EM_1T[3:0]: current switching control for the pre-emphasis 1st tap.

Table2: First tap pre-emphasis settings
TX_PRE_EM_1T[3:0]
Output Current
0000
Disable the pre-emphasis 1st tap
0001
0.5mA
0010
1.0mA
0011
1.5mA

Hspice Setting
tx_1tap0
tx_1tap0p5
tx_1tap1p0
tx_1tap1p5

0100
0101
0110
0111
1000
1001
1010
1011
1100
b.

2.0mA
2.5mA
3.0mA
3.5mA
4.0mA
4.5mA
5.0mA
5.5mA
6.0mA

tx_1tap2p0
tx_1tap2p5
tx_1tap3p0
tx_1tap3p5
tx_1tap4p0
tx_1tap4p5
tx_1tap5p0
tx_1tap5p5
tx_1tap6p0

TX_PRE_EM_2T[2:0]: current switching control for the pre-emphasis 2nd tap.

Table3: Second tap pre-emphasis settings
Output Current
Hspice Setting
Disable the pre-emphasis 2nd tap
tx_2tap0
0.25mA
tx_2tap0p25
0.50mA
tx_2tap0p5
0.75mA
tx_2tap0p75
1.00mA
tx_2tap1p0
1.25mA
tx_2tap1p25
1.50mA
tx_2tap1p5
2.00mA
tx_2tap2p0

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TX_PRE_EM_2T[2:0]
000
001
010
011
100
101
110
111

c.

TX_PRE_EM_PT[2:0]: current switching control for the pre-emphasis pre-tap.

TX_PRE_EM_PT[2:0]
000
001
010
011
100
101
110
111

Table4: Pre-tap pre-emphasis settings

Output Current
Hspice Setting
Disable the pre-emphasis pre-tap
tx_prtap0
0.25mA
tx_prtap0p25
0.50mA
tx_prtap0p5
0.75mA
tx_prtap0p75
1.00mA
tx_prtap1p0
1.25mA
tx_prtap1p25
1.50mA
tx_prtap1p5
2.00mA
tx_prtap2p0

d.

TX_SIGINV_2T: polarity control of the pre-emphasis 2nd post-tap.

0:
Default (normal operation)
1:
Inverted (invert the pre-emphasis current flow)

e.

TX_SIGINV_PRE: polarity control of the pre-emphasis pre-tap.

0:
Default (normal operation)
1:
Inverted (invert the pre-emphasis current flow)

iv. Slew rate control:

TX_R_SLEW: Slew rate control for TX.
0:
Slew rate OFF (Default)
1:
Slew rate ON

v. Internal termination resistor:

TX_TERM_SEL[1:0]: controlled signal for TX differential output termination resistor
The internal termination resistance values vary depending on the process corner and temperature.

TX_TERM_SEL[1:0]
00

Table 5: Internal Termination Resistance settings

Termination Resistance
Hspice Setting
r150_tt
150 Ohms (Default)
r150_ff
r150_ss

01

120 Ohms

10

100 Ohms

11

External Resistor (open drain)

r120_tt
r120_ff
r120_ss
r100_tt
r100_ff
r100_ss
rext

vi. Common mode voltage control:

TX_VTT[1:0]: controlled signals for common-mode termination voltage
Table 6: Internal Termination Resistance settings
Common mode voltage level
Hspice Setting
Tri-state
pd
VCM=0.6v for PCI-E
vcm_op6
VCM=0.7v (not for PCI-E)
vcm_op7
Reserved bit
vcm_op55

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TX_VTT[1:0]
00
01
10
11

vii. Power and Ground:

VCCTX: 1.2v power supply
VCCHTX: 1.5v power supply
VCCHX : 3.3v power supply
VSSX:
Common ground

viii. TX data output:

TXP_NEAR: Positive differential output pin
TXN_NEAR: Negative differential output pin

Spice templates description:

i. <tx_spice_file>.spi : TX spice template which can be modified depending on the application.

ii. Netlist:
.include ../inc/tx.cir

iii. Hspice options:

.options badchr co=132 scale=1e-6 acct ingold=2 nomod probe captab=0
*.options badchr co=132 scale=1e-6 acct post=1 nomod probe captab=0
The first option line is for Viewtrace display, the second one is for Awave display.
badchr
$ warns if a nonprintable character in input
co=132
$ Set number of columns of output
scale=1e-6
$ Linear scaling factor for L & W dimensions (um)
acct
$ generate a detail accounting/statistic report.
ingold=2
$ Define output format as exponential
nomod
$ Suppress model parameter output
probe
$ Suppress post-analysis output to only variables in
$.probe, .print, .plot, & .graph statements
captab=0
$ 1=Report node capacitances at each operating point
csdf=2
$ Set output for Viewtrace element templates display
post=1
$ Set output for Awave element template display
accurate
$ 1= Sets timestep to give better TRAN accuracy
See spice manuals for more options.
iv. Process corner
.inc ../inc/2sgx_tt.inc

$ Typical/Typical corner
$ For Fast/Fast corner, change 2sgx_tt.inc to 2sgx_ff.inc
$ For Slow/Slow corner, change 2sgx_tt.inc to 2sgx_ss.inc

v. Power/ground:

.param pwrq=1.2v
.param pwrqh=3.3v
.param pwrqm=1.5v
vcchx vcchx 0 pwrqh
vcchtx vcchtx 0 pwrqm
vcctx vcctx 0 pwrq
vssx vssx 0 0
vi. Temperature:
.temp 85

$ Typical temperature

$ Operating data rate. This number is at 6.5Gbps

$ Rise/fall time of TX data input
$ Simulation time in term of number of data bits
$ Data input for TX. Spice data input can be converted
$ from any random data pattens 01010001 by using
$ tx_ingen script under ../inc/ directory.

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vii. Input data pattern

.param tdrate=6.5e9
.param trfx=30ps
.param bit_num=300
.inc ../inc/tx_data_input

$ Low voltage power supply

$ High voltage power supply
$ Medium voltage power supply
$ 3.3v power supply
$ 1.5v power supply
$ 1.2v power supply
$ Ground

viii. Pre-emphasis setup:

.lib ../inc/tx-setting.inc tx_prtap0 $ Turn off the pre-tap pre-emphasis. See table 4 for more settings.
.lib ../inc/tx_setting.inc tx_1tap0 $ Turn off the 1st tap pre-emphasis. See table 2 for more settings.
.lib ../inc/tx_setting.inc tx_2tap0 $ Turn off the 2nd tap pre-emphasis. See table 3 for more settings.
ix. Termination resistor:
.lib ../inc/tx_setting.inc r100_tt

$ Internal termination resistor setting. See table 5 for more settings.

x. Common mode voltage source:

.lib ../inc/tx_setting.inc vcm_0p6 $ Common mode voltage. Vcm=0.6v. See table 6 for more settings.
xi. Output voltage opening control:
.lib ../inc/tx_setting.inc vod_8ma $ Output voltage control. Output current = 8ma.
$ See table 1 for more settings.
xii. Slew rate control:
Vtx_slew tx_r_slew vssx 0

$ Slew rate control. Slew rate is turned OFF.

$ Turn ON (change 0 to pwrq).

xiii. Pre-emphasis sign inversion control:

Vsiginv_pre tx_siginv_pre vssx 0 $ Pre-tap polarity control. Positive = 0, negative = pwrq.
Vsiginv_2t tx_siginv_2t vssx 0 $ Pre-tap polarity control. Positive = 0, negative = pwrq.
xiv. External termination for RX representation:
Rext txp_near txn_near 100
$ Set the external matching resistor to 100 ohms.
xv. Eye diagram generation & probing nodes:
Eye veye 0 VOL=1e09*(TIME-dperc*int(TIME/dperc))
Reye veye 0 10k.
.inc ../inc/tx_probe.inc
$ Probe TX interested nodes for viewing.

c. RX Receiver:

VCCRX

Below (figure 2) is the RX driver block diagram. The left has two TX input signals (RX_INP/RX_INN) and the rest are
RAM bits to control the equalizer, the dc gain, the common mode voltage, and the termination resistor. The top has the
power pins and the bottom has the ground pins. The right has RX output pins (RXP/RXN) to the CDR. See the pin
description for more detail of every pin.

RX_INP
RX_INN
RXP

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RX_EQ (see table 7)

RX
Driver

RXN

RX_RBIT_DC[1:0]
RX_VTT[2:0]

VSSX

RX_TERM[1:0]

Figure 2: A simple RX driver

Pin description:

i. RX data input
a. RX_INP: positive RX data input.
b. RX_INN: negative RX data input

ii. Equalizer gain:

a. RX_EQ: table 7 shows 16 available equalizer settings for RX driver

Gain level
Bypass (0dB)
Low Gain
(3-7dB)

Med Gain
(8-12dB)

High Gain
(12-16dB)

Table7: Equalizer settings

Equalizer Gain
Bypass
Low 0
Low 1
Low 2
Low 3
Low 4
Med 0
Med 1
Med 2
Med 3
Med 4
High 0
High 1
High 2
High 3
High 4

Hspice Setting
eq_bp
eq_l0
eq_l1
eq_l2
eq_l3
eq_l4
eq_m0
eq_m1
eq_m2
eq_m3
eq_m4
Eq_h0
Eq_h1
Eq_h2
Eq_h3
Eq_h4

iii. DC gain level:

RX_RBIT_DC[1:0]: Programmable DC gain setting for the equalizer.
Table8: Equalizer DC gain settings
RX_RBIT_DC[1:0]
DC gain level
00
0 dB
01
3 dB
10
3 dB
11
6 dB

Hspice Setting
dc_gain0
dc_gain1
dc_gain2
dc_gain3

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iv. Common mode voltage control:

RX_VTT[2:0]: Common mode voltage level control for RX. Support only 3 level settings: tri-state, 0.9v,
and 1.2v.
Table9: Common mode voltage level settings
RX_VTT[2:0]
Voltage level
Hspice Setting
110
Tri-state
Vcm_tri
010
0.9v
Vcm_0p9
011
1.2v
Vcm_1p2

v. Internal termination resistor:

RX_TERM[1:0]: controlled signal for RX differential input termination resistor
The internal termination resistance values vary depending on the process corner and temperature.

RX_TERM[1:0]
00

01

10
11

Table 10: Internal Termination Resistance settings

Termination Resistance
Hspice Setting
r150_tt
150 Ohms (Default)
r150_ff
r150_ss
r120_tt
120 Ohms
r120_ff
r120_ss
r100_tt
100 Ohms
r100_ff
r100_ss
External Resistor (open drain)
rext

vi. Power and Ground:

VCCRX: 1.2v power supply for RX driver
VSSX:
Common ground
vii. RX data output to the CDR:
RXP: Positive differential output pin
RXN: Negative differential output pin

Spice templates description:

To test the RX driver, the user can use a ideal driver or a real driver to drive the RX receiver directly or through a
backplane. The RX spice template is built for figure 3 which is a ideal driver driving a backplane, an AC cap, and a
real Altera RX receiver.

Inputs Must Start from a

common point

AC Coupled
RXIPPAD

PORT1

BP

INPP

RXP

RX_INP

Ideal
Driver

Rx
PORT3

BP

INNN

RX_INN

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RXINPAD

RXN

DC Block
(AC cap)
Encrypted

Figure 3: A ideal driver drives Altera RX receiver through a backplane and an AC cap.
i. <rx_spice_file>.spi : RX spice template which can be modified depending on the application.
ii. Netlist:
.include ../inc/rx.cir

iii. Hspice options:

.options badchr co=132 scale=1e-6 acct ingold=2 nomod probe captab=0
*.options badchr co=132 scale=1e-6 acct post=1 nomod probe captab=0
The first option line is for Viewtrace display, the second one is for Awave display.
badchr
$ warns if a nonprintable character in input
co=132
$ Set number of columns of output
scale=1e-6
$ Linear scaling factor for L & W dimensions (um)
acct
$ generate a detail accounting/statistic report.
ingold=2
$ Define output format as exponential
nomod
$ Suppress model parameter output
probe
$ Suppress post-analysis output to only variables in
$.probe, .print, .plot, & .graph statements
captab=0
$ 1=Report node capacitances at each operating point
csdf=2
$ Set output for Viewtrace element templates display
post=1
$ Set output for Awave element template display
accurate
$ 1= Sets timestep to give better TRAN accuracy
See spice manuals for more options.
iv. Process corner
.inc ../inc/2sgx_tt.inc

v. Power/ground:
.param pwrq=1.2v
vccrx vccrx 0 pwrq
vvssx vssx 0 0
vi. Temperature:

$ Typical/Typical corner
$ For Fast/Fast corner, change 2sgx_tt.inc to 2sgx_ff.inc
$ For Slow/Slow corner, change 2sgx_tt.inc to 2sgx_ss.inc

$ Low voltage power supply

$ 1.2v power supply
$ Ground

.temp 85
vii. Input data pattern
.param tdrate=6.5e9
.param trfx=10ps
.param vlox=-0.3v
.param vhix=0.3v
.param vcom=0v
.param bit_num=300
.inc ../inc/rx_data_input

$ Typical temperature

$ Operating data rate. This number is at 6.5Gbps

$ Rise/fall time of ideal driver
$ Input voltage low of ideal driver
$ Input voltage high of ideal driver
$ Common input voltage of ideal driver
$ Simulation time in term of number of data bits
$ Data input to ideal driver. Spice data input can be converted
$ from any random data pattens 01010001 by using
$ rx_ingen script under ../inc/ directory.

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viii. Ideal driver: This ideal driver can be replaced with any real driver.
.include ../inc/filter_enc.inc
$ Ideal driver filter
X1_filt rxippad port1 vssx synth_driver $ Ideal driver hooks to rxippad port
X1_filt rxinpad port3 vssx synth_driver $ Ideal driver hooks to rxinpad port
ix. Backplane connection:
S1 port1 inpp port3 innn vssx mname=bp_name
.model bp_name s tstonefile=s.channel1.s4p
x. AC couple capacitance:
Cacp inpp rx_inp 1mf
Cacp innn rx_inn 1mf

$ AC cap on rx_inp node

$ AC cap on rx_inn node

xi. Equalizer gain setting:

.lib ../inc/rx_setting.inc dc_gain0

$ Equalizer gain setting. See table 7 for more settings.

xii. Equalizer DC gain setting:

.lib ../inc/rx_setting.inc dc_gain0

$ Equalizer DC gain setting. See table 8 for more settings.

xiii. Common mode voltage source:

.lib ../inc/rx_setting.inc vcm_0p9

$ Common mode voltage. Vcm=0.9v. See table 9 for more settings.

xiv. Termination resistor:

.lib ../inc/rx_setting.inc r100_tt

$ Internal termination resistor setting. See table 10 for more settings.

xv. Eye diagram generation & probing nodes:

eye veye 0 VOL=1e09*(TIME+55e-9)-dperc*int((TIME+55e-9)/dperc))
reye veye 0 10k.
.inc ../inc/rx_probe.inc
$ Probe RX interested nodes for viewing.