Release 0.

Stratix-II GX HSSI
Encrypted Spice Model
User Guide

Copyright 2007 Altera Corp.

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Release 0.2

1. Introduction:
This document is the spice model user guide for the High Speed Serial Interface (HSSI) Transmitter and Receiver for
Stratix II GX product family. The information in this document enables the user to configure the spice models to his/her
requirement. It contains 3 different spice templates for TX, RX and TX+RX combined.
The document will discuss the naming convention for the spice models, file layout and organization, control nodes for the
transmitter and receiver along with the procedure for using the various settings. Please go over the document before running
the simulations.

2. Directory Structure:
Figure 1 shows the directory structure of the Stratix II GX spice model kit.
SIIGX_IO
|_______inc
|
|
|_______ tx
|
|
|_______ rx
|
|
|_______ tx_rx

Figure 1. Directory structure of Stratix II GX HSSI spice modeling kit

The content of each directory is as follows:

inc: This directory contains the encrypted spice netlists for the I/O structures, the encrypted transistor process model libraries,
control setting files, data input files and script to generate data input patterns. Here is the detailed description of files under ../inc/
directory.
- Netlist:
i. tx.cir:
Encrypted TX driver netlist
ii. rx.cir:
Encrypted RX receiver netlist
iii. rx_run_w_tx_only.cir: Reduced RX receiver netlist when running with Altera TX (a few shared subckts are
taken out to avoid duplicated subckts get to redefined twice).
- Process Corner:
i. 2sgx_tt.inc : Encrypted process model for typical/typical corner
ii. 2sgx_ff.inc : Encrypted process model for fast/fast corner
iii. 2sgx_ss.inc : Encrypted process model for slow/slow corner
- Data input
i. tx_data_input: TX input data file
ii. rx_data_input: RX input data file (when running signal generator T-line RX)
iii. signal_generator.inc: Signal generator source
- Scripts:
i. tx_ingen: generates the spice input data file for TX. Type tx_ingen in ./inc/ directory for instruction. The
scripts can only be used under UNIX platform.
ii. de_gen & do_gen: sub-scripts of tx_ingen.
iii. rx_ingen: generates the spice input data file for RX.
iv. rgen: sub-script of rx_ingen
v. prbs7.bit: a sample of prbs7 binary bits.
vi. Example: Executing the command ./tx_ingen prbs7.bit inside the ./inc/ directory, a tx_data_input file will be
generated. Prbs7.bit can be replaced with any other binary file with 0100101011 pattern.
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Note: Change the permission for above scripts to executable by typing the following line in Unix/Linux window
under./inc/ directory: chmod a+x *gen*.
- Control setting files:
i. tx_setting.inc: library file to control all TX settings
ii. rx_setting.inc: library file to control all RX settings.
- Spice output file :
i. tx_probe.inc: probing nodes of TX blocks
ii. rx_probe.inc: probing nodes of RX block

tx: this directory contains the sample spice template using the transmitter model.
-

tx_nearend.spi : spice template using the transmitter block

rx: this directory contains the sample spice template using the receiver model.
-

Siggen_bp_rx.spi : spice template using the receiver block

tx_rx: this directory contains the sample spice template using both the transmitter and receiver model.
- tx_bp_rx.spi: spice template for TX Backplane (T-line) RX simulation

3. Transmitter

Driver Model:

Figure 2 is the TX driver block diagram. The left side are the TX input signals (VID) and the control nodes for pre-emphasis
settings, slew rate settings, termination resistor settings, and common mode voltage settings. The top has the power pins and
the bottom has the ground pins. The right has the near-end output pins (TXP_NEAR/TXN_NEAR). See the pin description
for more details.

TX_VOD_SEL[2:0]

VCCHTX

TX_CLK/TX_CLKB

VCCTX

VID

TX_PRE_EM_1T[3:0]
TX_PRE_EM_2T[2:0]
TX_PRE_EM_PT[2:0]
TX_SIGINV_2T
TX_SIGINV_PRE

TX
Driver

TXP_NEAR

TXN_NEAR

TX_R_SLEW

VSSX

TX_TERM_SEL[1:0]
TX_50[4:0]
TX_VTT[1:0]

Figure 2: A simplified TX driver

-

Pin description:
i. TX data input & Clocks
a. VID: TX input signals. VID is a short representation of 4 differential input signals (2 pairs). These 2
pairs are:
TX_DE/TX_DEB: Differential pair of TX even data inputs
TX_DO/TX_DOB: Differential pair of TX odd data inputs.

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Release 0.2
Note: The odd/even data input is running at half the real data rate. They are combined and serialized
into a single serial data inside the TX block. They are taken care in the tx_data_input file (which can
be automatically generated using the tx_ingen script).
For example:
TX_DE:
TX_DO:
TX_CLK
TX_CLKB
VID (Serial Input data):

b.

0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0
1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 0 1 1 1 1
10101010101010101010101010101010101010101010
01010101010101010101010101010101010101010101
____________________________________________
01010001011111010110111010011101010011011101

The bit patten of the serial input data (input to TX driver) is the same as the serial output data at
TXP_NEAR pin.
TX_CLK/TX_CLKB: Differential pair of Clocks to capture the above even/odd data and shift into the
TX driver. TX_CLK samples TX_DE & TX_CLKB samples TX_DO to produce VID.

ii. Output voltage control:

a. TX_VOD_SEL[2:0]: level control for differential output voltage (VOD) through current control at the
output
Table1: VOD settings
TX_VOD_SEL[2:0]
Output Current
Hspice Setting
000
2mA
vod_2ma
001
4mA
vod_4ma
010
6mA
vod_6ma
011
8mA
vod_8ma
100
10mA
vod_10ma
101
12mA
vod_12ma
110
14mA
vod_14ma
iii. Pre-emphasis:
a. TX_PRE_EM_1T[3:0]: level control for the pre-emphasis 1st tap.
Table2: First tap pre-emphasis settings
TX_PRE_EM_1T[3:0]
1st Tap Pre-em Level
Hspice Setting
0000
Disable the pre-emphasis 1st tap
tx_1tap0
0001
1
tx_1tap1
0010
2
tx_1tap2
0011
3
tx_1tap3
0100
4
tx_1tap4
0101
5
tx_1tap5
0110
6
tx_1tap6
0111
7
tx_1tap7
1000
8
tx_1tap8
1001
9
tx_1tap9
1010
10
tx_1tap10
1011
11
tx_1tap11
1100
12
tx_1tap12
Note: Please refer to table 5 for LEGAL pre-emphasis settings with different VOD voltage levels

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TX_PRE_EM_2T[2:0]: level control for the pre-emphasis 2nd tap.
Table3: Second tap pre-emphasis settings
TX_PRE_EM_2T[2:0]
2nd Tap Pre-em Level
Hspice Setting
000
Disable the pre-emphasis 2nd tap
tx_2tap0
001
1
tx_2tap1
010
2
tx_2tap2
011
3
tx_2tap3
100
4
tx_2tap4
101
5
tx_2tap5
110
6
tx_2tap6
111
7
tx_2tap7
Note: Please refer to table 5 for LEGAL pre-emphasis settings with different VOD voltage levels
b.

c.
Note:
refer to
LEGAL
emphasis
with
VOD
levels
d.

TX_PRE_EM_PT[2:0]: level control for the pre-emphasis pre-tap.

Table4: Pre-tap pre-emphasis settings
TX_PRE_EM_PT[2:0]
Pre-Tap Pre-em Level
Hspice Setting
000
Disable the pre-emphasis pre-tap
tx_prtap0
001
1
tx_prtap1
010
2
tx_prtap2
011
3
tx_prtap3
100
4
tx_prtap4
101
5
tx_prtap5
110
6
tx_prtap6
111
7
tx_prtap7

Please
table 5 for
presettings
different
voltage
TX_SIGIN

V_2T: polarity control of the pre-emphasis 2nd post-tap.

0:
Default (normal operation)
1:
Inverted (inverted operation)
e.

TX_SIGINV_PRE: polarity control of the pre-emphasis pre-tap.

0:
Default (normal operation)
1:
Inverted (inverted operation)

Table 5: LEGAL Hspice Settings for Pre-Emphasis taps with different VOD levels
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Level

VOD
(mv)

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Pre_Tap

1st Tap

2nd
Taps

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Level

VOD
(mv)

Pre_Tap

1st Tap

2nd Taps

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1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12

200
200
200
200
200
200
200
200
200
200
200
200
400
400
400
400
400
400
400
400
400
400
400
400
600
600
600
600
600
600
600
600
600
600
600
600
800
800
800
800
800
800
800
800
800
800
800
800

Tx_prtap1
Tx_prtap2
Tx_prtap3
Tx_prtap4
Tx_prtap5
NaN
NaN
NaN
NaN
NaN
NaN
NaN
Tx_prtap1
Tx_prtap2
Tx_prtap3
Tx_prtap4
Tx_prtap5
Tx_prtap6
Tx_prtap7
NaN
NaN
NaN
NaN
NaN
Tx_prtap1
Tx_prtap2
Tx_prtap3
Tx_prtap4
Tx_prtap5
Tx_prtap6
Tx_prtap7
NaN
NaN
NaN
NaN
NaN
Tx_prtap1
Tx_prtap2
Tx_prtap3
Tx_prtap4
Tx_prtap5
Tx_prtap6
Tx_prtap7
NaN
NaN
NaN
NaN
NaN

tx_1tap1
tx_1tap2
tx_1tap3
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
tx_1tap1
tx_1tap2
tx_1tap3
tx_1tap4
tx_1tap5
tx_1tap6
NaN
NaN
NaN
NaN
NaN
NaN
tx_1tap1
tx_1tap2
tx_1tap3
tx_1tap4
tx_1tap5
tx_1tap6
tx_1tap7
tx_1tap8
tx_1tap9
tx_1tap10
NaN
NaN
NaN
tx_1tap2
tx_1tap3
tx_1tap4
tx_1tap5
tx_1tap6
tx_1tap7
tx_1tap8
tx_1tap9
tx_1tap10
tx_1tap11
tx_1tap12

tx_2tap1
tx_2tap2
tx_2tap3
tx_2tap4
tx_2tap5
NaN
NaN
NaN
NaN
NaN
NaN
NaN
tx_2tap1
tx_2tap2
tx_2tap3
tx_2tap4
tx_2tap5
tx_2tap6
tx_2tap7
NaN
NaN
NaN
NaN
NaN
tx_2tap1
tx_2tap2
tx_2tap3
tx_2tap4
tx_2tap5
tx_2tap6
tx_2tap7
NaN
NaN
NaN
NaN
NaN
tx_2tap1
tx_2tap2
tx_2tap3
tx_2tap4
tx_2tap5
tx_2tap6
tx_2tap7
NaN
NaN
NaN
NaN
NaN

1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12

Note:

1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400

tx_prtap1
tx_prtap2
tx_prtap3
tx_prtap4
tx_prtap5
tx_prtap6
tx_prtap7
NaN
NaN
NaN
NaN
NaN
tx_prtap1
tx_prtap2
tx_prtap3
tx_prtap4
tx_prtap5
tx_prtap6
tx_prtap7
NaN
NaN
NaN
NaN
NaN
tx_prtap1
tx_prtap2
tx_prtap3
tx_prtap4
tx_prtap5
tx_prtap6
tx_prtap7
NaN
NaN
NaN
NaN
NaN

NaN
NaN
tx_1tap3
tx_1tap4
tx_1tap5
tx_1tap6
tx_1tap7
tx_1tap8
tx_1tap9
tx_1tap10
tx_1tap11
tx_1tap12
NaN
NaN
NaN
tx_1tap4
tx_1tap5
tx_1tap6
tx_1tap7
tx_1tap8
tx_1tap9
tx_1tap10
tx_1tap11
tx_1tap12
NaN
NaN
NaN
NaN
tx_1tap5
tx_1tap6
tx_1tap7
tx_1tap8
tx_1tap9
tx_1tap10
tx_1tap11
tx_1tap12

NaN

= illegal

settings

tx_2tap1
tx_2tap2
tx_2tap3
tx_2tap4
tx_2tap5
tx_2tap6
tx_2tap7
NaN
NaN
NaN
NaN
NaN
tx_2tap1
tx_2tap2
tx_2tap3
tx_2tap4
tx_2tap5
tx_2tap6
tx_2tap7
NaN
NaN
NaN
NaN
NaN
tx_2tap1
tx_2tap2
tx_2tap3
tx_2tap4
tx_2tap5
tx_2tap6
tx_2tap7
NaN
NaN
NaN
NaN
NaN

iv. Internal termination resistor:

TX_TERM_SEL[1:0]: control signal for TX differential output termination resistor
The internal termination resistance values may vary depending on the process corner and temperature.
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Release 0.2
TX_TERM_SEL[1:0]
00
01
10
11

Table 6: Internal Termination Resistance settings

Termination Resistance
Hspice Setting
r150_tt
150 Ohms (Default)
r150_ff
r150_ss
r120_tt
120 Ohms
r120_ff
r120_ss
r100_tt
100 Ohms
r100_ff
r100_ss
External Resistor (open drain)
rext

Note: TX_50[4:0] are internal control signals for termination resistance values. The user does not need to
worry about these nodes. The above HSpice settings (table 6) will take care of them.
v. Common mode voltage control:
TX_VTT[1:0]: control signals for common-mode termination voltage
TX_VTT[1:0]
00
01
10
11

Table 7: TX common model voltage settings

Common mode voltage level
Hspice Setting
Tri-state
pd
VCM=0.6v for PCI-E
vcm_op6
VCM=0.7v (not for PCI-E)
vcm_op7
Reserved bit
vcm_op55

vi. Power and Ground:

VCCTX: 1.2v power supply
VCCHTX: 1.5v power supply
VSSX:
Common ground
vii. TX data output:
TXP_NEAR: Positive differential output pin
TXN_NEAR: Negative differential output pin

Spice templates description:

This section provides example spice template tx_nearend.spi, describing in detail how to successfully perform a
simulation using Stratix II GX HSSI transmitter model; the spice template can be modified depending on the application.
i. Netlist:

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Release 0.2
.include ../inc/tx.cir

$ Get the TX circuit netlist.

Below statement assigns all the pin names to the TX_TOP sub-circuit instance.
XTX TXN_NEAR TXP_NEAR TX_504 TX_503 TX_502 TX_501 TX_500 TX_CLK TX_CLKB TX_DE
+ TX_DEB TX_DO TX_DOB TX_PRE_EM_1T3 TX_PRE_EM_1T2 TX_PRE_EM_1T1 TX_PRE_EM_1T0
+ TX_PRE_EM_2T2 TX_PRE_EM_2T1 TX_PRE_EM_2T0 TX_PRE_EM_PT2 TX_PRE_EM_PT1
+ TX_PRE_EM_PT0 TX_R_SLEW TX_SIGINV_2T TX_SIGINV_PRE TX_TERM_SEL1 TX_TERM_SEL0
+ TX_VOD_SEL2 TX_VOD_SEL1 TX_VOD_SEL0 TX_VTT1 TX_VTT0 VCCHTX VCCTX VSSX TX_TOP
+ s=1u
Note: s=1u specifies all device parameters inside the TX_TOP subckt are scaled with 1um.

ii. Hspice options:

.option hier_scale=1
.option scale=1.0

$ Hierarchical scale
$ Final Scale = scale * s = 1.0 * 1u = 1um

Note: when using this model with another device model other than Alteras, please make sure that these
scale options are set correctly. The default settings are s=1u in the subckt call, scale=1.0 and .option
hier_scale=1 is turned ON. If other device(s) use scale=1u or scale=1e-6, then the s=1u in the
subckt call should be changed to s=1 because the final scale is the product of these two scales.
.options badchr co=132 acct ingold=2 nomod probe captab=0
*.options badchr co=132 acct post=1 nomod probe captab=0
The first option line is for Viewtrace display, the second one is for Awave display.
badchr
$ warns if a nonprintable character in input
co=132
$ Set number of columns of output
scale=1e-6
$ Linear scaling factor for L & W dimensions (um)
acct
$ generate a detail accounting/statistic report.
ingold=2
$ Define output format as exponential
nomod
$ Suppress model parameter output
probe
$ Suppress post-analysis output to only variables in
$.probe, .print, .plot, & .graph statements
captab=0
$ 1=Report node capacitances at each operating point
csdf=2
$ Set output for Viewtrace element templates display
post=1
$ Set output for Awave element template display
accurate
$ 1= Sets timestep to give better TRAN accuracy
See spice manuals for more options.
iii. Process corner
.inc ../inc/2sgx_tt.inc

$ Typical/Typical corner
$ For Fast/Fast corner, change 2sgx_tt.inc to 2sgx_ff.inc
$ For Slow/Slow corner, change 2sgx_tt.inc to 2sgx_ss.inc

iv. Power/ground:
.param pwrq=1.2v
.param pwrqm=1.5v
vcchtx vcchtx 0 pwrqm
vcctx vcctx 0 pwrq
vssx vssx 0 0

$ Low voltage power supply

$ Medium voltage power supply
$ 1.5v power supply
$ 1.2v power supply
$ Ground

v. Temperature:
.temp 25

$ Typical temperature

vi. Input data pattern:

.param tdrate=6.375e9
.param trfx=30ps
.param bit_num=300
.inc ../inc/tx_data_input

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$ Operating data rate.

$ Rise/fall time of TX data input
$ Simulation time in term of number of data bits
$ Data input for TX. Spice data input can be converted
$ from any random data patterns 01010001 by using
$ tx_ingen script under ../inc/ directory.
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Release 0.2
vii. Clocks:
vtx_clk tx_clk 0 pulse(0 pwrq '1/tdrate-trfx/2' trfx trfx '1/tdrate-trfx' '2/tdrate')
Etx_clkb tx_clkb 0 VOL='( (v(tx_clk)-pwrq)*(-1) )'
viii. Pre-emphasis setup:
.lib ../inc/tx-setting.inc tx_prtap0 $ Disable the pre-tap pre-emphasis. See table 4 for more settings.
.lib ../inc/tx_setting.inc tx_1tap0 $ Disable the 1st tap pre-emphasis. See table 2 for more settings.
.lib ../inc/tx_setting.inc tx_2tap0 $ Disable the 2nd tap pre-emphasis. See table 3 for more settings.
ix. Termination resistor:
.lib ../inc/tx_setting.inc r100_tt

$ 100 internal termination resistor. See table 6 for more settings.

x. Common mode voltage source:

.lib ../inc/tx_setting.inc vcm_0p6 $ Common mode voltage. Vcm=0.6v. See table 7 for more settings.
xi. Output voltage opening control:
.lib ../inc/tx_setting.inc vod_8ma $ Differential output voltage (VOD) control. Output current = 8ma.
$ See table 1 for more settings.
xii. Pre-emphasis sign inversion control:
Vsiginv_pre tx_siginv_pre vssx 0 $ Pre-tap polarity control. Positive = 0, negative = pwrq.
Vsiginv_2t tx_siginv_2t vssx 0 $ Pre-tap polarity control. Positive = 0, negative = pwrq.
xiii. External termination for RX representation:
Rext txp_near txn_near 100
$ Set the external matching resistor to 100 ohms.
xiv. Eye diagram generation & probing nodes:
Eye veye 0 VOL=1e09*(TIME-dperc*int(TIME/dperc))
Reye veye 0 10k.
.inc ../inc/tx_probe.inc
$ Probe interested nodes of TX.
xv. Simulation transient:
.tran 0.01ns 'bit_num*perx+2ns+60ns' start=60ns
It takes a while for all the nodes to become stabilized. Thus to obtain a correct value, the start time to
record the waveforms should be at a time when all the nodes are stable. Thats why the above 60ns is
chosen for a good eye diagram.

4. RX Receiver:
Below (Figure 3) is the RX driver block diagram. The left has two TX input signals (RX_INP/RX_INN) and the rest are
RAM bits to control the equalizer, the dc gain, the common mode voltage, and the termination resistor. The top has the
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VCCRX

Release 0.2
power pins and the bottom has the ground pins. The right has RX output pins (RXP/RXN) to the CDR. See the pin
description for more detail of every pin.

RX_INP
RX_INN

RX_EQ (see table 7)

RX_RBIT_DC[1:0]

RXP

RX
Driver

RXN

RX_VTT[2:0]
RX_TERM[1:0]
VSSX

RX_B50[4:0]

Figure 3: A simple RX driver

-

Pin description:
i. RX data input
a. RX_INP: positive RX data input.
b. RX_INN: negative RX data input
ii. Equalizer gain:
a. RX_EQ: table 8 shows 16 available equalizer settings for RX driver
Gain level
Bypass (0dB)
Low Gain
(3-7dB)

Med Gain
(8-12dB)

High Gain
(12-16dB)

Table8: Equalizer settings

Equalizer Gain
Bypass
Low 0
Low 1
Low 2
Low 3
Low 4
Med 0
Med 1
Med 2
Med 3
Med 4
High 0
High 1
High 2
High 3
High 4

Hspice Setting
EQ_BP
EQ_L0
EQ_L1
EQ_L2
EQ_L3
EQ_L4
EQ_M0
EQ_M1
EQ_M2
EQ_M3
EQ_M4
EQ_H0
EQ_H1
EQ_H2
EQ_H3
EQ_H4

iii. DC gain level:

RX_RBIT_DC[1:0]: Programmable DC gain setting for the equalizer.

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Table 9: Equalizer DC gain settings

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Release 0.2
RX_RBIT_DC[1:0]
00
01
10
11

DC gain level
0 dB
3 dB
3 dB
6 dB

Hspice Setting
dc_gain0
dc_gain1
dc_gain2
dc_gain3

iv. Common mode voltage control:

RX_VTT[2:0]: Common mode voltage level control for RX. Support only 3 level settings: tri-state, 0.9v,
and 1.2v.
Table 10: Common mode voltage level settings
RX_VTT[2:0]
Voltage level
Hspice Setting
110
Tri-state
Vcm_tri
010
0.9v
Vcm_0p9
011
1.2v
Vcm_1p2
v. Internal termination resistor:
RX_TERM[1:0]: controlled signal for RX differential input termination resistor
The internal termination resistance values vary depending on the process corner and temperature.
RX_TERM[1:0]
00
01
10
11

Table 11: Internal Termination Resistance settings

Termination Resistance
Hspice Setting
r150_tt
150 Ohms (Default)
r150_ff
r150_ss
r120_tt
120 Ohms
r120_ff
r120_ss
r100_tt
100 Ohms
r100_ff
r100_ss
External Resistor (open drain)
rext

RX_B50[4:0]: are internal controlled signals for termination resistance values. The user needs not to worry
about these nodes. The above hspice settings (table 11) will take care of them.
vi. Power and Ground:
VCCRX: 1.2v power supply for RX driver
VSSX:
Common ground
vii. RX data output to the CDR:
RXP: Positive differential output pin
RXN: Negative differential output pin

Spice templates description:

To test the RX driver, the user can use an ideal driver or a real driver to drive the RX receiver directly or through a
backplane. The RX spice template is built for figure 4 which is an ideal driver driving a backplane, an AC cap, and
a real Altera RX receiver.

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12

Release 0.2
Inputs Must Start from a
common point

AC Coupled
RXIPPAD

SG_P

INPP

BP

Signal
Generator

RXINPAD

RXP

RX_INP

Rx

SG_N

BP

INNN

RX_INN

RXN

DC Block
(AC cap)
Figure 4: A signal generator drives Altera RX receiver through a backplane and an AC cap.
i. siggen_bp_rx.spi: RX spice template which can be modified depending on the application.
ii. Netlist:
.include ../inc/rx.cir

$ Get the RX circuit netlist.

Below statement assigns all the pin names to the RX_TOP sub-circuit instance.
XRX_TOP RX_EQA RX_EQB RX_EQC RX_EQD RX_EQV RX_INP RX_INN RX_RBIT_DC1
+ RX_RBIT_DC0 RXP RXN RX_B504 RX_B503 RX_B502 RX_B501 RX_B500 RX_TERM1
+ RX_TERM0 RX_VTT2 RX_VTT1 RX_VTT0 VCCRX VSSX RX_TOP
+ s=1u
Note: s=1u specifies all device parameters inside the TX_TOP subckt are scaled with 1um.

iii. Hspice options:

.option hier_scale=1
.option scale=1.0

$ Hierarchical scale
$ Final Scale = scale * s = 1.0 * 1u = 1um

.options badchr co=132 scale=1e-6 acct ingold=2 nomod probe captab=0

*.options badchr co=132 scale=1e-6 acct post=1 nomod probe captab=0
The first option line is for Viewtrace display, the second one is for Awave display.
badchr
$ warns if a nonprintable character in input
co=132
$ Set number of columns of output
scale=1e-6
$ Linear scaling factor for L & W dimensions (um)
acct
$ generate a detail accounting/statistic report.
ingold=2
$ Define output format as exponential
nomod
$ Suppress model parameter output
probe
$ Suppress post-analysis output to only variables in
$.probe, .print, .plot, & .graph statements
captab=0
$ 1=Report node capacitances at each operating point
csdf=2
$ Set output for Viewtrace element templates display
post=1
$ Set output for Awave element template display
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accurate
$ 1= Sets timestep to give better TRAN accuracy
See spice manuals for more options.
iv. Process corner
.inc ../inc/2sgx_tt.inc

v. Power/ground:
.param pwrq=1.2v
vccrx vccrx 0 pwrq
vvssx vssx 0 0
vi. Temperature:
.temp 25

$ Typical/Typical corner
$ For Fast/Fast corner, change 2sgx_tt.inc to 2sgx_ff.inc
$ For Slow/Slow corner, change 2sgx_tt.inc to 2sgx_ss.inc
$ Low voltage power supply
$ 1.2v power supply
$ Ground

$ Typical temperature

vii. Input data pattern

.param tdrate=6.375e9
.param trfx=10ps
.param vlox=-0.3v
.param vhix=0.3v
.param vcom=0v
.param bit_num=300
.inc ../inc/rx_data_input

$ Operating data rate. This number is at 6.5Gbps

$ Rise/fall time of ideal driver
$ Input voltage low of ideal driver
$ Input voltage high of ideal driver
$ Common input voltage of ideal driver
$ Simulation time in term of number of data bits
$ Data input to ideal driver. Spice data input can be converted
$ from any random data patterns 01010001 by using
$ rx_ingen script under ../inc/ directory.

viii. Ideal driver: This ideal driver can be replaced with any real driver.
.include ../inc/signal_generator.inc
$ Ideal Signal Generator
Xsiggen_p rxippad sg_p vssx signal_gen $ Signal generator hooks to rxippad port
Xsiggen_n rxinpad sg_n vssx signal_gen $ Signal generator hooks to rxinpad port
ix. Backplane connection:
*** Loss Less T-line ****
T_lossless_p sg_p vssx inpp vssx ZO=50 TD=0.05ns
T_lossless_n sg_n vssx innn vssx ZO=50 TD=0.05ns
For the backplane, a loss less transmission line is used here. The customer can replace the T-line with
his/her backplane S-parameter by replacing the T_lossless_p/_n with S1 (as shown below).
your_backplane.s4p is the s-parameter file name of the customer backplane.
*** S-parameter Backplane ***
S1 sg_p inpp sg_n innn vssx mname=bp_name
.model bp_name s tstonefile='../inc/your_backplane.s4p'
x. AC couple capacitance:
Cacp inpp rx_inp 1mf
$ AC cap on rx_inp node
Cacp innn rx_inn 1mf
$ AC cap on rx_inn node
Note: the capacitance value can be varied depending on the customers application.
xi. Equalizer gain setting:
.lib ../inc/rx_setting.inc EQ_BP

$ Equalizer gain setting. See table 8 for more settings.

xii. Equalizer DC gain setting:

.lib ../inc/rx_setting.inc dc_gain0

$ Equalizer DC gain setting. See table 9 for more settings.

xiii. Common mode voltage source:

.lib ../inc/rx_setting.inc vcm_0p9

$ Common mode voltage. Vcm=0.9v. See table 10 for more settings.

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xiv. Termination resistor:
.lib ../inc/rx_setting.inc r100_tt

$ Internal termination resistor setting. See table 11 for more settings.

xv. Eye diagram generation & probing nodes:

eye veye 0 VOL=1e09*(TIME+55e-9)-dperc*int((TIME+55e-9)/dperc))
reye veye 0 10k.
.inc ../inc/rx_probe.inc
$ Probe RX interested nodes for viewing.
xvi. Simulation transient:
.tran 0.01ns 'bit_num*perx+2ns+60ns' start=60ns
It takes a while for all nodes to become stabilized. Thus to obtain a correct value, the start time to record
the waveforms should be at the time all nodes are stable. Thats why the above 60ns is chosen for a good
eye diagram. Some backplanes may require longer or shorter stable times.

EYE mask for the output of the RX:

The outputs (RXP/RXN) are the input to the CDR. To make sure the CDR (clock data recovery)
works fine, the eye opening of the differential output at RXP/RXN pins must be larger than the EYE
mask.
-

X1_eye

Below 3.2 Gbps:

X1_eye = 0.275 UI
X2_eye = 0.400 UI
Y_eye = 165 mV

Y_eye

Above 3.2 Gbps:

X1_eye = 0.5 UI
X2_eye = 0.6 UI
Y_eye = 165 mV

X2_eye
Figure 5: Eye mask for the differential output of the RX

5. TX BP RX:
This section shows the Altera TX driver that drives the Altera RX receiver block through a backplane and AC caps. Figure 6
shows a simplified diagram for the connection of these two blocks. Please refer to the TX and RX sections for the settings.
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Release 0.2

AC Coupled
TXP_NEAR

VID

BP

RXP

RX_INP

TX

Rx
TXN_NEAR

BP

Figure 6: TX drives RX through a backplane and AC caps.

-

INPP

INNN

RX_INN

RXN

DC Block
(AC cap)

Pin description:
Please refer to the TX Driver and RX receiver sections for pin description and settings.

Spice templates description:

This section provides the spice template to check the link of Altera TX Backplane RX. The current
backplane is a lossless transmission line (T-line). The user can replace the T-line network with his/her backplane
s-parameter
The spice file tx_bp_rx.spi has 5 sections as follow:
i.
ii.
iii.
iv.

Part 1: contains the process, options, and temperature.

Part 2: is Altera TX driver. This portion is very similar to the TX driver section.
Part 3: contains the backplane. The loss less transmission line must be replaced with the customer backplane.
Part 4: is the Altera RX receiver. This portion is very similar to the RX receiver section. The only difference is
rx.cir is replaced by rx_run_w_tx_only.cir netlist. The reason is rx.cir shares some subckts with tx.cir. Thus
rx_run_w_tx_only.cir is a reduced version of rx.cir where shared subckt under rx.cir are removed to avoid
conflict.
v. Part 5: contains the simulation transient + the eye diagram generation.

Note:
1.

2.

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Please refer to the TX driver and RX receiver sections for more information.
The value of the AC caps varies depending to the customers application. If bigger cap value is used,
then it takes longer time for the TXP_NEAR/TXN_NEAR to settle down longer simulation run
time is needed.

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Release History
version

Date

Details of Release

0.1

February 2006

Stratix II GX preliminary HSSI Spice model release ( version 0.1)

0.2

March 2007

Stratix II GX Final HSSI Spice Model Release

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Release 0.2

101 Innovation Drive

San Jose, CA 95134
(408) 544-7000
www.altera.com

Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions
Company, the stylized Altera logo, specific device designations and all other words and logos
that are identified as trademarks and/or service marks are, unless noted otherwise, the
trademarks and service marks of Altera Corporation in the U.S. and other countries.* All other
product or service names are the property of their respective holders. Altera products are
protected under numerous U.S. and foreign patents and pending applications, mask work
rights, and copyrights.
Note: This is a non-public, draft document that is not intended or approved for release or
distribution outside of Altera or for any use by a third party, except pursuant to an executed
non-disclosure agreement. The specifications, data and information contained herein are
merely preliminary and may not be relied upon for any purpose unless and until a final
document has been published by Altera. Accordingly, except as expressly agreed to in a
writing signed by an officer of Altera, Altera and its licensors (i) assume no responsibility or
liability arising out of the application or use of any specifications, data, information, product, or
service described or provided herein, (ii) make no warranties, representations or guarantees
as to the accuracy, completeness or genuineness of such specifications, data, information,
product, or service, and (iii) specifically disclaim any implied warranties of merchantability, noninfringement, or fitness for a particular purpose as to such items.

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