DynamicCharacteristicsofCMOSInverter

PowerDissipationinInverterCircuits
Staticpowerdissipation(Ps)dueto
leakagecurrents
othercurrentdrawncontinuouslyfromthepowersupply

Dynamicpowerdissipation(Pd)duetochargingand
dischargingloadcapacitance
Shortcircuitpowerdissipation(Psc)duringthefinite
riseandfalltimesofinput

P=Ps+Pd+Psc

CMOSInverterStaticPower
NostaticcurrentinCMOSaslongasVin <VTN orVin >VDD +VTP
Leakagecurrent
isdeterminedbytheofftransistorinfluencedby
transistorwidth
supplyvoltage
MOSthresholdvoltage

Leakage(Static)PowerConsumption
DIBL

VDDIleakage
Subthresholdleakage
Drain(diode)leakage

Gateleakage

Subthresholdcurrentisthedominantfactor.
Allleakagecurrentincreaseexponentiallywith
temperature!
4

DynamicPowerDissipation
VOH

VOL

Vin,VOut

T/2

Pd

1
v t i t dt

T 0

T2

T
1

vout t iDN t dt VDD vout t iDP t dt

T 0
T

2
5

DynamicPowerDissipation
dVout
iDN t CL
dt
T2
dVout
1

Pd vout t CL
dt
T 0

dVout
iDP t CL
dt
T
dVout

dt VDD vout t CL
dt

T
2

dt

VDD
0

1
Pd CL vout t dVout CL VDD vout t dVout
T VDD

0
VDD
2 0
2

Vout
Vout
1
Pd CL
CL VDDVout

2 V
2 0
T

DD

Pd

1
2
CLVDD
T

Pd C V

2
L DD

f
6

ShortCircuitPowerConsumption

Duringswitching
Finiteslopeofinputsignalcausesadirectpath
betweenVDD andGNDforashortperiodoftime
Boththetransistorsareconducting

ShortCircuitPowerConsumption
Imax isdeterminedby
SaturationcurrentofNMOSandPMOS
Dependson
sizes
processtechnology
temperature
Imax isastrongfunctionof
Ratiobetweentheinputandoutputslopes
afunctionofCL

ShortCircuitPowerConsumption

ApproximateISC asatriangularfunction
Energypercycle
ESC

tr t f
I max tr I max t f
VDD

VDD I SC
2
2
2

PSC VDD I SC f

ImpactofCL onPSC

WithlargeCL
Inputmovesthroughthetransientregionbeforethe
outputstartstochange
VDS ofPMOSis 0duringthisperiod
PMOSshutsoffwithoutdeliveringanycurrent
ISC 0

10

ImpactofCL onPSC

WithsmallCL
Outputfalltimeismuchsmallerthantheinputrisetime
PMOSVDS VDD formostofthetransitionperiod
PMOSdeviceisinsaturation
ISC PMOSsaturationcurrent

11

ObservationsonPSC
Short circuit dissipation is minimized when
output rise (fall) time larger than input rise (fall) time

Output rise (fall) time too large slows down the gate
Can cause short circuit currents in the fan-out gates
Local vs. global conflict

Short circuit dissipation is minimized by

Matching the rise/fall times of the input and output signals
For the overall circuit, the rise (fall) times of all signals should
be kept within a range
12

ObservationsonPSC
Shortcircuitcurrentisreducedwhenthepowersupplyis
lowered.
WhenVDD <VTN +|VTP|,ISC =0
Shortcircuitdissipationisbecominglessimportantindeep
submicrontechnologies asthresholdvoltagesscalingata
slowerratethanVDD

13

NMOS/PMOSRatio
WidthofPMOSisincreasedsothattheresistancematchesthatof
NMOS
PMOStoNMOSwidthequalstotheratioof mobility(n/p),
typically2to3.5(ifstrainedsiliconisused,1)
Motivationbehindthisapproachistocreateaninverterwith
symmetricalVTC
PLH =PHL
Ratiomaynotyieldstheminimumoverallpropagationdelay
Ifsymmetryandreducednoisemarginsarenotofprimeconcern
speedupinverterbyreducingthewidthofthePMOSdevice
14

NMOS/PMOSRatio
Rationalitybehindthestatement wideningthe
PMOSis
ImprovesthetPLH oftheinverterbyincreasingthe
chargingcurrent
DegradesthetPLH becauseofalargerparasitic
capacitance

Whentwocontradictoryeffectsarepresent,
theremustexistatransistorratiothatoptimizes
thepropagationdelayoftheinverter

15

CascadedInverter
Considertwoidentical,cascadedCMOSinverters
Theloadcapacitanceofthefirstgateequals
CL = (Cdp1 + Cdn1) + (Cgp2 + Cgn2) + CW
WhenthePMOSdevicesare timeslargerthanthe
NMOS[ =(W/L)p/(W/L)n],alltransistorcapacitances
willscaleinapproximatelythesameway
Cdp1 Cdn1 and Cgp2 Cgn2
Thus,
CL = (1 + ) (Cdn1 + Cgn2) + CW

16

CascadedInverter
WithReqp (Reqn)theequivalentonresistanceofthe
PMOS(NMOS)overtheintervalofinterest
with PLH = Reqp CL and PHL = Reqn CL
Theaveragepropagationdelayis
Reqp

p 1 Cdn1 Cgn 2 Cw Reqn

p 1 Cdn1 Cgn 2 Cw 1 Reqn

2

r(=Reqp/Reqn)representstheresistanceratioof
identicallysizedPMOSandNMOStransistors.
17

CascadedInverter
r

1 C C C 1 R
2

dn1

gn 2

eqn

Theoptimalvalueof (opt)canbefoundbysetting
thefirstdifferentialofp withrespectto to0

Cw
opt r 1

Cdn1 Cdn 2
Ifwiringcapacitanceisnotnegligible,largervalueof
shouldbeused

18

CascadedInverter
Theoptimumvalueof isaround1.9
IfCw isnegligible,
(Cdn1+Cgn2>>Cw),opt=r0.5,
incontrasttothefactorr
normallyusedinthenon
cascadedcase.
Smallerdevicesizesyield
fasterdesignatthe
expenseofsymmetryand
noisemargin

19

SuperBuffer
Achainofinvertersdesignedtodrivealargecapacitiveloadwith
minimalsignalpropagationdelaytime.

SuperBuffer

CL

GivenalargecapacitiveloadCL
Howtosizetheinverters?
Howmanystagesareneededtominimizethedelay?
20

InverterSizing
LetCiref andRref bethereferenceintrinsiccapacitanceand
equivalentonresistanceoftheinverter,andSbethe
sizingfactor

p 0.69 Req Cintrinsic Cext

Cext
S

Cext
p 0.69 Rref Ciref 1
SC
iref

Cext
p p 0 1

SC
iref

p 0.69

Rref

SC

iref

21

InverterSizing

Cg andCintrinsic areproportionaltothegatesizeone
canwrite(thus isthesizingfactor)
Cintrinsic =Cg
NisNumberofinverterstages
Thedelayofjth inverterstagecanbewrittenas
Cg , j 1

C
ex
t
p , j p 0 1
p p 0 1

g, j

22
Ciref

InverterSizing

Totaldelaycanbecalculatedas
N
N
Cg , j 1
p p , j p 0 1

j 0
j 0
Cg , j
WithCg,N+1=CL
Minimump isobtainedbysetting
p

Cg , j

Cext
p p 0 1
C
iref

0 for each j
23

InverterSizing

p
Cg , j

Cg , j 1
Cg , j

Cg , j
Cg , j 1

; for j 1 N

Eachinverterissizedupbythesamefactorf withrespecttothe
precedinggate,andthussamedelay
GivenCg,0 andCL (Fistheeffectivesizeratio)

CL
f N 1
N 1 F
C g ,0
24

InverterSizing

Theminimumdelayis
Evaluating p 0

N 1 F
p N 1 p 0 1

N 1

N 1

F ln F
0
N 1

f e

1
f

f ln f 1

25

InverterSizing

Forthespecialcasewhen =0(noselfloading),

f ln f 1

f e

Inreality,theselfloadingcannotbeignored

26

BufferDesign
1

tp

64

65

18

64

15

64

2.8

15.3

64

16

2.8

64

22.6

27