IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO.

5, MAY 2013

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Compact Triple-Transistor Doherty Amplifier

Designs: Differential/Power Combining
Shichang Chen, Student Member, IEEE, and Quan Xue, Fellow, IEEE

AbstractThis paper investigates two novel triple-transistor Doherty power amplifier (DPA) designs. A compact fully differential
DPA topology will be firstly introduced. Three active devices, two
carriers, and one peaking are combined in a very judicious way to
amplify the differential signal like what a typical Doherty amplifier does. Due to the reduction of transistor number from four for a
classic differential DPA to three, the realization cost and layout dimension is reduced simultaneously. A second triple-transistor design, which amplifies an in-phase input signal and outputs a combined single-ended one, is introduced next. Similar to the differential design, a twin-carrier single-peaking configuration is applied.
The functions of Doherty amplification and power combining are
well integrated. Theoretical analysis will be given for a deep understanding of the operation principles regarding these two proposed architectures. To validate their effectiveness, prototypes corresponding to them are implemented based on Crees GaN HEMT
CGH40010. Experimental results demonstrate notably high drain
efficiencies at saturation and 6-dB back-off regions for both of the
designs.
Index TermsDifferential power amplifier (PA), Doherty amplifier, drain efficiency, load modulation network, power combining.

I. INTRODUCTION

HE power amplifier (PA) plays a very important role in a

communication system. As a power-hungry component,
it consumes most of the energy for an RF transmitter. From
this point of view, its efficiency is crucially important in order
to save power for cellular infrastructures or extend working
endurance for handsets. Besides, modulated signals used
today generally have very large peak-to-average power ratios
(PAPRs). Consequently, amplifier efficiency in the back-off
region becomes a primary concern for RF system designers.
As one of many effective ways to boost efficiency at back-off
power, the Doherty power amplifier (DPA) has become popular
in both industry and academia [1][9]. Recently, several new
Doherty amplifier structures have been developed to improve
a classic DPA characteristics in terms of linearity [3], average
efficiency [4], high-efficiency power range [5], [6], bandwidth
[7], [8], and size[9].
Manuscript received December 11, 2012; revised March 04, 2013; accepted
March 07, 2013. Date of publication March 29, 2013; date of current version
May 02, 2013. This work was supported by the Shenzhen Science and Technology Planning Project for the Establishment of the Key Laboratory in 2009
under Project CXB200903090021A.
The authors are with the State Key Laboratories of Millimeter Waves, City
University of Hong Kong, Kowloon, Hong Kong (e-mail: shichang.leo@my.
cityu.edu.hk).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2013.2253794

On the other hand, the quick advancement of modern wireless communication has put forward a much higher requirement
on the reliability and ruggedness of the whole system. Differential/balanced circuits are regaining popularity due to their inherent high immunity to the environmental disturbance. A variety of differential/balanced components, such as filters [10],
[11], low-noise amplifiers [12][14], antennas [15][17], and
PAs [18], [19] have been reported in the literature. A recent
work reported a balanced Doherty amplifier where two identical
DPAs replace the sub-amplifier cells in a classic balanced configuration [20]. However, four transistors must be used, which
increases the complexity and cost dramatically. In this paper, a
compact fully differential triple-transistor DPA supporting differential input and output is proposed. To be specific, two carrier
PAs are used for low power. Nevertheless, only one peaking PA
is applied for high power whose output power is equally shared
with the two carrier PAs. The proposed configuration can be
used directly to drive differential components, such as antennas
[15][17] and bandpass filters [10], [11], getting rid of baluns.
Besides, due to the reduction of transistor number and the affiliated circuitries, the proposed configuration is concise in structure and effective in cost.
Meanwhile, to meet the increasing demand on power-handling capacity at microwave and millimeter-wave bands, powercombining techniques are regularly adopted. Several schemes,
such as integrated planar power combining [21], and spatial or
quasi-optical power combining [22], [23] have been presented
thus far. Inspired by these designs, another triple-transistor DPA
is proposed in this paper, which amplifies an in-phase input and
provides a combined single-ended output. Similar to the differential DPA mentioned above, two carrier PAs plus one peaking
PA are applied in this design. The Doherty amplification and
power-combining functions are well integrated in a compact and
effective manner to reduce the whole circuit size and cost.
This paper is organized as follows. Section II gives the theoretical analysis and design rules of the two proposed tripletransistor Doherty amplifiers, respectively. In Section III and
IV, simulation and measurement results corresponding to the
two new DPAs will be given to demonstrate their practicalities.
Section V gives the conclusion.
II. THEORETICAL ANALYSIS AND DESIGN RULES
A. Fully Differential DPA
Fig. 1 shows the schematic of the proposed differential Doherty amplifier. The differential input power is distributed into
three paths by two equal-split Wilkinson dividers and a 180
hybrid. The signals delivered to the two carrier PAs are kept
out-of-phase, but equal in magnitude, while that to the peaking

0018-9480/$31.00 2013 IEEE

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considered as an ideal current source, and let

(1)
where
,
are currents for the two carrier PAs, respectively. Taking the phase delays of the transmission lines into
consideration, we can have
Fig. 1. Schematic of the fully differential DPA.

(2)
is the magnitude of the transformed carrier currents. According to the classic transmission-line theory, the impedance
seen at one end of a half-wavelength line is identical to the
impedance seen at the other end. Consequently, the peaking
PA shares its current equally with the two carrier PAs. In other
words, each carrier PA creates the Doherty amplifier along with
half of the peaking PA periphery. As a consequence,

(3)
is the current supported by the peaking PA. Similar
where
to the analysis in [2], the load impedances of the carrier PAs and
the peaking PA at saturation can be expressed as
(4)
(5)
as the fundamental current ratio
by defining
at saturation and letting
in
order to have an easier independent optimization of each subamplifier and further assembly. The characteristic impedances
of
and
should be written as
(6)
(7)
Fig. 2. Equivalent circuits for the fully differential DPA for: (a) low-power
region and (b) high-power region.

PA is twice larger in magnitude. A section of transmission line

is inserted before the peaking PA to balance the phase just as in
a conventional DPA.
Fig. 2(a) shows the equivalent circuit for the differential DPA
in the low-power region where the peaking PA is in the off-state
. By adding a 180 transmission line between the two
carrier PAs, they are completely isolated from each other due to
the differential input excitation. For each single-carrier PA, its
operation is the same to that of a conventional design.
When the input increases, the peaking PA starts to operate,
as shown in Fig. 2(b). Suppose that every transistor can be

Finally, the load impedance for the carrier PAs in the lowpower region is obtained as
(8)
In sum, the load impedance of the carrier amplifiers is modto , and from
to
for the
ulated from
peaking amplifier with the increase of power. Output matching
networks and offset lines should be designed to have transistors
optimally matched to
for the two carrier PAs in
the low-power region.
Moreover, we can see that the power fed to the peaking PA is
twice as large as that to the two carriers. Essentially, only half of
the input power is wasted when the peaking PA is off. This may
help to relieve the gain degradation if a larger-size peaking cell

CHEN AND XUE: COMPACT TRIPLE-TRANSISTOR DOHERTY AMPLIFIER DESIGNS

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Fig. 3. Schematic of the power-combining DPA.

is adopted with more input power feeding in order to balance

the currents [24].
B. Power-Combining DPA
Fig. 3 depicts the schematic of the second design called a
power-combining Doherty amplifier. It also consists of two
carrier PAs and one peaking PA as the aforementioned differential DPA. However, the input signal is now in-phase, which is
distributed into three paths by two equally split Wilkinson dividers and a T-junction combiner. Similarly, a section of transmission line is inserted before the peaking PA to make the phase
balanced. As its name suggests, the three amplifiers are combined in-phase at the output terminal. An attractive property
of this structure is that the Doherty amplification and power
combining are integrated into one circuit. Apart from this, the
triple-transistor configuration is very compact in size and effective in cost as well.
Fig. 4(a) depicts the equivalent circuit for the proposed
power-combining DPA in the low-power region. As the
peaking PA is turned off, the two carrier PAs operate only
and they drive the same load symmetrically. It is quite easy to
derive the load impedance for a single carrier as

Fig. 4. Equivalent circuits for the power-combining DPA for: (a) low-power
region and (b) high-power region.

where
is again defined as the fundamental
current ratio at maximum power. Let
, we can have

(12)

(9)

For the high-power operation, the active load modulation is

realized by the participation of the peaking PA. To better understand the modulation process in this design, mathematical
analysis is given again in a similar way as before. As shown in
Fig. 4(b), we assume

(10)
According to [2], the load impedance to the carrier PAs and
the peaking PA at saturation are given as

(11)

Substitute (12) into (9), the load impedance in the low-power

region for the carrier PAs is obtained as
, which
reduces gradually to
with the input power. It is noted that
the low-power impedance in this design is the same as that of
the aforementioned differential one. This indicates, to similar
drain efficiencies, at 6-dB back-off points for the two proposed
designs, as confirmed by both simulation and measurement results shown in the following sections.
III. SIMULATION RESULTS
In Section II, a detailed analysis of the two presented new
Doherty amplifier architectures has been intensively introduced.
Simulations are carried out to demonstrate the feasibilities of
these designs. It is common practice to bias the carrier and
peaking PAs to the class-AB and class-C modes for a typical Doherty amplifier. However, due to the low biasing for the peaking
cell, its maximum current swing will also be smaller, which,

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in turn, affects the load modulation. To make the currents balanced, an asymmetrical configuration with more input power
fed to the peaking cell may be applied [24], [25]. However, due
to the availability of active devices in hand, the same transistors GaN HEMTs CGH40010 from Cree are used for all the
sub-amplifier units in these two designs. Besides, as intended
for a second efficiency peak around 6-dB back-off power from
saturation, a common efficiency evaluation criterion [26], the
carrier PAs are output matched to over-driven mode in order
to limit the saturation power. The peaking PA is biased at light
class-C mode to make its current large enough for adequate load
modulation. The simulated current ratio is about 1.45 for both
designs. Following the design procedures shown above and in
[2], load modulation networks are implemented for the two architectures accordingly. Besides, an output matching network
and offset line are added after each sub-amplifier. After independent optimizations, the sub-amplifiers are assembled into the
presented DPA configurations by following the design procedures introduced in Section II. Input matching networks are also
designed to achieve high overall gain and efficiencies. All the
simulations are conducted in Agilents ADS with a transistor
model provided by Cree.
Moreover, to better characterize the amplifier performances,
several new parameters are defined. For the differential DPA,

Fig. 5. Simulated drain efficiency curves as a function of the total output power
for the proposed two DPAs.

the low- and high-power regions for the two proposed designs
largely account for their close total maximum power, drain efficiencies at saturation, and 6-dB back-off regions, respectively.
The slight efficiency discrepancy in the upper power ranges is
mainly attributed to the difference between the two load modulation networks, whose modulation efficiencies slightly differ.

IV. EXPERIMENTAL VERIFICATIONS

Gain

(13)

where
, , and Gain are the total output power, total drain
efficiency, and total gain. Here,
,
,
,
, and
means the output power at load 1, load 2, dc consumptions for
carrier #1, carrier #2, and peaking PA, respectively.
refers
to half the differential input power, as shown in Fig. 1.
Similarly, the total drain efficiency and gain for the powercombining DPA are defined as

Gain

(14)

where
,
,
, and
means the output power, dc consumptions for carrier #1, carrier #2, and peaking PA, respectively.
refers to the single input power, as shown in Fig. 3.
Fig. 5 compares the total drain efficiencies as a function of the
output power for the two proposed configurations. It can be seen
that the total saturation power reaches about 45 dBm for each
design. The differential DPA achieves 72% and 79% efficiencies at saturation and 6-dB back-off powers, respectively, which
shows an obvious Doherty amplifier characteristic. Regarding
the power-combining DPA, its saturation efficiency is 79%. At
6-dB back-off point, the drain efficiency is 70%. Again, typical Doherty amplification is achieved for the proposed design.
As mentioned before, the similar impedance conditions in both

To further demonstrate the introduced topologies, prototypes

corresponding to the two architectures are implemented, respectively, on Roger RT/Duroid 5870 substrates with
and 31-mil thickness. The operating frequency is 2.6 GHz for
both designs. All the carriers PAs are biased identically at deep
class-AB mode
mA , and the gate voltages of the
peaking cells are slightly tuned to achieve flat overall gains. All
the dc supply voltages at drain terminals are set to 28 V.
The measured total drain efficiency and gain profiles versus
the total output power for the two proposed DPAs under a
single-tone continuous wave (CW) excitation are depicted in
Fig. 6. For the differential DPA, we have 63% efficiency at
6-dB back-off point, while that of the peak power is 73%.
Moreover, larger than 40% efficiency is achieved in a 10-dB
power range from saturation. The maximum output power is
44.8 dBm, which agrees well with the simulation result. In contrast, the power-combining DPA obtains 61% and 72% drain
efficiencies at 6-dB back-off and peak powers, respectively, but
similar to the differential DPA, larger than 40% efficiency is
also achieved in an approximate 10-dB power range from the
saturation power of 44.6 dBm. We can see that the total gain
performances are much more similar to each other due to the
structure similarity of the two designs. The slight discrepancy is
attributed to the different input division networks and transistor
tolerance.
Fig. 7 shows dc currents of the sub-amplifiers against the
input power for the differential DPA. It can be noted that the
two current curves for the carrier PAs are very close to each
other, which indicates an accepted conformity between them.

CHEN AND XUE: COMPACT TRIPLE-TRANSISTOR DOHERTY AMPLIFIER DESIGNS

Fig. 6. Measured drain efficiency (DE) and total gain curves versus the output
power for the proposed differential and power-combining DPAs under CW excitation.

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Fig. 9. Measured dc supply currents as a function of the input power for the
proposed power-combining DPA under CW excitation.

Fig. 10. IMD3 comparison between the two proposed DPA configurations
under two-tone test.
Fig. 7. Measured dc supply currents as a function of the input power for the
proposed differential DPA under CW excitation.

Fig. 8. Power unbalance between the two output terminals as a function of the
total output power for the differential DPA.

The measured amplitude unbalance between the two output terminals as shown in Fig. 8 further confirms this. The power unbalance is limited to 0.35 dBm in the whole power range.

Fig. 9 shows the dc currents of the sub-amplifiers against the

input power for the power-combining DPA. It is obvious that
similar current swings are obtained with that of the differential
case. This confirms the similar load conditions in both the lowand high-power regions for both DPA configurations.
Moreover, a two-tone signal with 5-MHz spacing is used
to characterize the linearity property of each implemented
prototype. The measured third-order intermodulation distortion
(IMD3) results are depicted and compared in Fig. 10. It is
worth noting that very similar characteristics are exhibited in
the low-power regions, indicating similar operating conditions
for the carrier PAs in both configurations. The slightly larger
discrepancy at high powers is mainly attributed to the different
modulated loads and biasing conditions for the two peaking
PAs.
As introduced before, by saving one transistor and its adjunct
circuitry, the introduced triple-transistor configurations are
structurally neat and cost effective. Fig. 11 and Fig. 12 show
photographs of the two fabricated Doherty amplifiers. Their
sizes are 118 123 mm and 99 85 mm , respectively. The
space occupancy of the 180 hybrid accounts for a larger size
for the implemented differential circuit. It is believed that the
total size can be further reduced if a packaged commercial

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and 60% efficiency values are observed at saturation and 6-dB

back-off points for both of the implemented prototypes.
REFERENCES

Fig. 11. Photograph of the fabricated triple-transistor differential DPA.

Fig. 12. Photograph of the fabricated triple-transistor power-combining DPA.

product is used to replace the hybrid, as shown in Fig. 11. In

this particular design, a classic microstrip hybrid is used only
for demonstrative purposes.
It needs emphasizing that although the single-peaking twincarrier architectures are used in these two designs in this paper,
single-carrier twin-peaking architectures can be applied as alternative solutions. They are more useful in scenarios where large
dynamic ranges are admired.
V. CONCLUSION
In this work, two novel designs of compact triple-transistor
DPAs have been introduced. By judiciously share the current of
one amplifier cell with the remaining two cells, circuit miniaturization and cost reduction can be simultaneously achieved while
preserving the classic Doherty amplification characteristics. To
validate their feasibilities, extensive simulations and measurements were conducted. Test results reveal that higher than 70%

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Shichang Chen (S09) was born in Zhejiang, China,

in 1987. He received the B.S. degree in electronic engineering from the Nanjing University of Science and
Technology, Nanjing, China, in 2009, and is currently
working toward the Ph.D. degree in electronic engineering at City University of Hong Kong, Kowloon,
Hong Kong.
His research interest focuses on high-efficiency
PAs and integrated circuits.

1963

Quan Xue (M02SM04F11) received the B.S.,

M.S., and Ph.D. degrees in electronic engineering
from the University of Electronic Science and
Technology of China (UESTC), Chengdu, China, in
1988, 1990, and 1993, respectively.
In 1993, he joined UESTC, as a Lecturer. He became a Professor in 1997. From October 1997 to October 1998, he was a Research Associate and then
a Research Fellow with the Chinese University of
Hong Kong. In 1999, he joined the City University of
Hong Kong, Kowloon, Hong Kong, where he is currently a Chair Professor with the Department of Electronic Engineering. He is
also the Associate Vice President (Innovation Advancement and China Office),
the Deputy Director of CityU Shenzhen Research Institute, the Deputy Director
of State Key Laboratory of Millimeter Waves (Hong Kong), and the Director of
the Information and Communication Technology Center (ICTC Center). He has
authored or coauthored over 200 internationally referred journal papers and over
100 international conference papers with over 2000 citations by others. He is the
Editor of the International Journal of Antennas and Propagation. His research
interests include microwave passive components, active components, antennas,
monolithic microwave integrated circuits (MMICs), and RF integrated circuits
(RFICs).
Prof. Xue is an associate editor for the IEEE TRANSACTIONS ON MICROWAVE
THEORY AND TECHNIQUES and an associate editor for the IEEE TRANSACTIONS
ON INDUSTRIAL ELECTRONICS. He is an elected member of the IEEE Microwave
Theory and Techniques Society (IEEE MTT-S) Administrative Committee
(AdCom).